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* RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson2018-09-172-2/+6
* x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu2018-09-175-13/+94
* x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu2018-09-174-18/+24
* x86: Update disassembler for VexWIGH.J. Lu2018-09-172-1563/+619
* x86: Replace VexW=3 with VexWIGH.J. Lu2018-09-172-468/+475
* x86: Set VexW=3 on AVX vrsqrtssH.J. Lu2018-09-153-2/+7
* x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu2018-09-154-6/+12
* x86: Support VEX/EVEX WIG encodingH.J. Lu2018-09-144-932/+941
* x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu2018-09-143-2/+22
* x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu2018-09-143-4/+23
* i386: Reformat OP_E_memoryH.J. Lu2018-09-142-2/+6
* x86: fold CRC32 templatesJan Beulich2018-09-143-45/+12
* x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu2018-09-132-8/+8
* i386: Update VexW field for VEX instructionsH.J. Lu2018-09-133-36/+44
* x86: drop bogus IgnoreSize from a few further insnsJan Beulich2018-09-133-52/+61
* x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich2018-09-133-12/+18
* x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich2018-09-133-96/+102
* x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich2018-09-133-78/+84
* x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich2018-09-133-26/+32
* x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich2018-09-133-32/+38
* x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich2018-09-133-742/+748
* x86: drop bogus IgnoreSize from SHA insnsJan Beulich2018-09-133-16/+21
* x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich2018-09-133-266/+271
* x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich2018-09-133-238/+244
* x86: drop bogus IgnoreSize from AVX insnsJan Beulich2018-09-133-256/+262
* x86: drop bogus IgnoreSize from GNFI insnsJan Beulich2018-09-133-12/+17
* x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich2018-09-133-32/+37
* x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich2018-09-133-44/+49
* x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich2018-09-133-20/+26
* x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich2018-09-133-126/+132
* x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich2018-09-133-64/+70
* x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich2018-09-133-36/+41
* x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich2018-09-133-416/+421
* x86: drop bogus IgnoreSize from SSE insnsJan Beulich2018-09-133-118/+123
* x86: drop unnecessary {,No}Rex64Jan Beulich2018-09-133-10/+16
* x86: also allow D on 3-operand insnsJan Beulich2018-09-133-96/+18
* x86: use D attribute also for SIMD templatesJan Beulich2018-09-134-1277/+165
* x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2018-09-132-3/+21
* S12Z: Make disassebler work for --enable-targets=all config.John Darrington2018-09-082-0/+5
* RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson2018-08-312-16/+21
* RISC-V: Allow instruction require more than one extensionJim Wilson2018-08-303-630/+636
* sparc/leon: add support for partial write psr instructionMartin Aberg2018-08-292-0/+13
* [MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2018-08-292-0/+9
* [MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2018-08-292-0/+9
* [MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu2018-08-293-2/+14
* [MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu2018-08-293-0/+26
* [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu2018-08-293-65/+88
* [MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu2018-08-293-6/+30
* Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra2018-08-213-48/+82
* Fix s12z test regexpsAlan Modra2018-08-211-4/+3
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