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| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:08:58 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:08:58 +0800 |
| commit | a693765e23934996abbe4e44c4ba28eabdece4f9 (patch) | |
| tree | 15c5e0d72cbff340fcc1f4afd57263b5ffe96ba0 /opcodes | |
| parent | bdc6c06e3b08ec48ec5ee2174dedc846969c36fd (diff) | |
| download | binutils-gdb-a693765e23934996abbe4e44c4ba28eabdece4f9.tar.gz | |
[MIPS/GAS] Add Loongson EXT2 Instructions support.
bfd/
* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.
binutils/
* readelf.c (print_mips_ases): Add Loongson EXT2 extension.
gas/
* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and
OPTION_NO_LOONGSON_EXT2.
(md_longopts): Likewise.
(mips_ases): Define availability for EXT.
(mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to
AFL_ASE_LOONGSON_EXT2.
(md_show_usage): Add help for -mloongson-ext2 and
-mno-loongson-ext2.
* doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2.
* doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2,
.set loongson-ext2 and .set noloongson-ext2.
* testsuite/gas/mips/loongson-ext2.d: New test.
* testsuite/gas/mips/loongson-ext2.s: New test.
* testsuite/gas/mips/mips.exp: Run loongson-ext2 test.
include/
* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
opcodes/
* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
option.
(print_mips_disassembler_options): Document -M loongson-ext.
* mips-opc.c (LEXT2): New macro.
(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 11 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 7 |
3 files changed, 26 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 13a1e1597bf..7da724f49dd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,13 @@ 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext + option. + (print_mips_disassembler_options): Document -M loongson-ext. + * mips-opc.c (LEXT2): New macro. + (mips_opcodes): Add cto, ctz, dcto, dctz instructions. + +2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * mips-dis.c (mips_arch_choices): Add EXT to loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-ext option. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 277d79d41ca..894bc4fd997 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -947,6 +947,13 @@ parse_mips_ase_option (const char *option) mips_ase |= ASE_LOONGSON_CAM; return TRUE; } + + /* Put here for match ext2 frist */ + if (CONST_STRNEQ (option, "loongson-ext2")) + { + mips_ase |= ASE_LOONGSON_EXT2; + return TRUE; + } if (CONST_STRNEQ (option, "loongson-ext")) { @@ -2613,6 +2620,10 @@ static struct N_("Recognize the Loongson EXTensions (EXT) " " instructions.\n"), MIPS_OPTION_ARG_NONE }, + { "loongson-ext2", + N_("Recognize the Loongson EXTensions R2 (EXT2) " + " instructions.\n"), + MIPS_OPTION_ARG_NONE }, { "gpr-names=", N_("Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n"), MIPS_OPTION_ARG_ABI }, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 5e4690d44fc..f1ceaee51d6 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -420,6 +420,9 @@ decode_mips_operand (const char *p) /* Loongson EXTensions (EXT) instructions support. */ #define LEXT ASE_LOONGSON_EXT +/* Loongson EXTensions R2 (EXT2) instructions support. */ +#define LEXT2 ASE_LOONGSON_EXT2 + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -518,6 +521,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, {"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 }, {"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 }, +{"cto", "d,s", 0x70000062, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{"ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{"dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, +{"dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 }, /* R5900 VU0 Macromode instructions. */ {"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 }, |