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* x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich2022-01-142-31/+31
* x86: record further wrong uses of EVEX.bJan Beulich2022-01-141-0/+8
* x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich2022-01-145-268/+42
* x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich2022-01-144-137/+77
* aarch64: Add support for new SME instructionsRichard Sandiford2022-01-062-302/+338
* x86: drop NoAVX insn attributeJan Beulich2022-01-064-4520/+4516
* x86: drop NoAVX from POPCNTJan Beulich2022-01-062-2/+2
* x86: drop some "comm" template parametersJan Beulich2022-01-062-90/+90
* x86: templatize FMA insn templatesJan Beulich2022-01-062-1016/+830
* opcodes: Make i386-dis.c thread-safeVladimir Mezentsev2022-01-051-1738/+1774
* Update year range in copyright notice of binutils filesAlan Modra2022-01-02282-286/+301
* unify 64-bit bfd checksMike Frysinger2022-01-015-4/+265
* RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta2021-12-241-0/+21
* x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev2021-12-171-0/+1
* RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu2021-12-161-0/+7
* aarch64: Fix uninitialised memoryRichard Sandiford2021-12-032-1/+3
* Revert "Re: Don't compile some opcodes files when bfd is 32-bit only"Alan Modra2021-12-032-10/+10
* aarch64: Add BC instructionRichard Sandiford2021-12-022-47/+65
* aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford2021-12-023-15/+127
* aarch64: Add support for +mopsRichard Sandiford2021-12-029-32/+1535
* aarch64: Add Armv8.8-A system registersRichard Sandiford2021-12-021-0/+5
* aarch64: Add id_aa64isar2_el1Richard Sandiford2021-12-021-0/+1
* aarch64: Tweak insn sequence codeRichard Sandiford2021-12-021-26/+22
* aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford2021-12-022-35/+26
* Allow the --visualize-jumps feature to work with the AVR disassembler.Marcus Nilsson2021-12-022-5/+37
* aarch64: Add missing system registers [PR27145]Richard Sandiford2021-11-301-1/+166
* aarch64: Make LOR registers conditional on +lorRichard Sandiford2021-11-301-4/+6
* aarch64: Remove ZIDR_EL1Richard Sandiford2021-11-301-1/+0
* aarch64: Allow writes to MFAR_EL3Richard Sandiford2021-11-301-1/+1
* aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford2021-11-301-1/+1
* aarch64: Remove duplicate system register entriesRichard Sandiford2021-11-301-7/+1
* RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu2021-11-301-1/+1
* RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2021-11-302-3/+5
* opcodes: enable silent build rulesMike Frysinger2021-11-294-54/+94
* opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2021-11-262-9/+147
* Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton2021-11-254-32/+45
* Updated French translation for the opcodes directory.Nick Clifton2021-11-252-236/+264
* Update bug reporting addressAlan Modra2021-11-231-1/+1
* Re: Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra2021-11-182-10/+10
* RISC-V: Add instructions and operand set for z[fdq]inxjiawei2021-11-182-148/+152
* aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus2021-11-1710-191/+387
* aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus2021-11-171-1/+11
* aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus2021-11-1710-1514/+1641
* aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus2021-11-179-236/+605
* aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus2021-11-176-140/+204
* aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus2021-11-1710-175/+363
* aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus2021-11-176-133/+547
* aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus2021-11-171-0/+11
* RISC-V: Support rvv extension with released version 1.0.Nelson Chu2021-11-172-0/+893
* RISC-V: Scalar crypto instructions and operand set.jiawei2021-11-162-20/+80
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