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* RISC-V: Allocate "various" operand typeTsukasa OI2023-03-312-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit intends to move operands that require very special handling or operand types that are so minor (e.g. only useful on a few instructions) under "W". I also intend this "W" to be "temporary" operand storage until we can find good two character (or less) operand type. In this commit, prefetch offset operand "f" for 'Zicbop' extension is moved to "Wif" because of its special handling (and allocating single character "f" for this operand type seemed too much). Current expected allocation guideline is as follows: 1. 'W' 2. The most closely related single-letter extension in lowercase (strongly recommended but not mandatory) 3. Identify operand type The author currently plans to allocate following three-character operand types (for operands including instructions from unratified extensions). 1. "Wif" ('Zicbop': fetch offset) 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions) 3. "Wfm" / "WfM" 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling solely for widening conversion instructions. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from "f" to "Wif". opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Move from "f" to "Wif". * riscv-opc.c (riscv_opcodes): Reflect new operand type.
* x86: parse VEX and alike specifiers for .insnJan Beulich2023-03-311-0/+2
| | | | | | | | | | All encoding spaces can be used this way; there's a certain risk that the bits presently reserved could be used for other purposes down the road, but people using .insn are expected to know what they're doing anyway. Plus this way there's at least _some_ way to have those bits set. For now this will only allow operand-less insns to be encoded this way.
* x86: introduce .insn directiveJan Beulich2023-03-313-0/+5
| | | | For starters this deals with only very basic constructs.
* aarch64: Add the RPRFM instructionRichard Sandiford2023-03-306-885/+925
| | | | | | | | | | This patch adds the RPRFM (range prefetch) instruction. It was introduced as part of SME2, but it belongs to the prefetch hint space and so doesn't require any specific ISA flags. The aarch64_rprfmop_array initialiser (deliberately) only fills in the leading non-null elements.
* aarch64: Add the SVE FCLAMP instructionRichard Sandiford2023-03-302-759/+771
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* aarch64: Add new SVE shift instructionsRichard Sandiford2023-03-302-873/+909
| | | | | This patch adds the new SVE SQRSHRN, SQRSHRUN and UQRSHRN instructions.
* aarch64: Add new SVE saturating conversion instructionsRichard Sandiford2023-03-302-752/+788
| | | | | This patch adds the SVE SQCVTN, SQCVTUN and UQCVTN instructions, which are available when FEAT_SME2 is implemented.
* aarch64: Add new SVE dot-product instructionsRichard Sandiford2023-03-306-841/+923
| | | | | | | This patch adds the SVE FDOT, SDOT and UDOT instructions, which are available when FEAT_SME2 is implemented. The patch also reorders the existing SVE_Zm3_22_INDEX to keep the operands numerically sorted.
* aarch64: Add the SVE BFMLSL instructionsRichard Sandiford2023-03-302-742/+793
| | | | | This patch adds the SVE BFMLSLB and BFMLSLT instructions, which are available when FEAT_SME2 is implemented.
* aarch64: Add the SME2 UZP and ZIP instructionsRichard Sandiford2023-03-302-338/+438
| | | | | This patch adds UZP and ZIP, which combine UZP{1,2} and ZIP{1,2} into single instructions.
* aarch64: Add the SME2 UNPK instructionsRichard Sandiford2023-03-302-709/+757
| | | | | | This patch adds SUNPK and UUNPK, which unpack one register's worth of elements to two registers' worth, or two registers' worth to four registers' worth.
* aarch64: Add the SME2 shift instructionsRichard Sandiford2023-03-309-505/+679
| | | | | | | | | | | | | | | There are two instruction formats here: - SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two or four registers. - SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of four registers. These are the first SME2 instructions to have immediate operands. The patch makes sure that, when parsing SME2 instructions with immediate operands, the new predicate-as-counter registers are parsed as registers rather than as #-less immediates.
* aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford2023-03-306-468/+592
| | | | | | | | | | There are two instruction formats here: - SQCVT, SQCVTU and UQCVT, which operate on lists of two or four registers. - SQCVTN, SQCVTUN and UQCVTN, which operate on lists of four registers.
* aarch64: Add the SME2 FP<->FP conversion instructionsRichard Sandiford2023-03-302-948/+1000
| | | | | This patch adds the BFCVT{,N} and FCVT{,N} instructions, which narrow a pair of .S registers to a single .H register.
* aarch64: Add the SME2 FP<->int conversion instructionsRichard Sandiford2023-03-302-749/+945
| | | | | | This patch adds the SME2 versions of the FP<->integer conversion instructions FCVT* and *CVTF. It also adds FP rounding instructions FRINT*, which share the same format.
* aarch64: Add the SME2 CLAMP instructionsRichard Sandiford2023-03-302-820/+892
| | | | | FCLAMP, SCLAMP and UCLAMP share the same format, although FCLAMP doesn't have a .B form.
* aarch64: Add the SME2 MOPA and MOPS instructionsRichard Sandiford2023-03-302-717/+789
| | | | [BSU]MOP[AS] share the same format.
* aarch64: Add the SME2 vertical dot-product instructionsRichard Sandiford2023-03-302-669/+789
| | | | | | | | | There are three instruction formats here: - BFVDOT + FVDOT - SVDOT + UVDOT - SUVDOT + USVDOT There are also 64-bit forms of SVDOT and UVDOT.
* aarch64: Add the SME2 dot-product instructionsRichard Sandiford2023-03-302-753/+1353
| | | | | | | BFDOT, FDOT and USDOT share the same instruction format. SDOT and UDOT share a different format. SUDOT does not have the multi vector x multi vector forms, since they would be redundant with USDOT.
* aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford2023-03-306-851/+1599
| | | | | | | SMLALL, SMLSLL, UMLALL and UMLSLL have the same format. USMLALL and SUMLALL allow the same operand types as those instructions, except that SUMLALL does not have the multi-vector x multi-vector forms (which would be redundant with USMLALL).
* aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford2023-03-308-665/+1485
| | | | | | | The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same encoding. They are the first instance of a ZA (as opposed to ZA tile) operand having a range of offsets. As with ZA tiles, the expected range size is encoded in the operand-specific data field.
* aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford2023-03-306-529/+753
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* aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford2023-03-304-439/+979
| | | | | | This patch adds the SME2 multi-register forms of F{MAX,MIN}{,NM} and {S,U}{MAX,MIN}. SQDMULH, SRSHL and URSHL have the same form as SMAX etc., so the patch adds them too.
* aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford2023-03-308-487/+750
| | | | | | | | | | | | | | | | | | | | | | Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. These are the first instructions to have tied register list operands, as opposed to tied single registers. The parse_operands change prevents unsuffixed Z registers (width==-1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' becomes: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
* aarch64: Add the SME2 ZT0 instructionsRichard Sandiford2023-03-308-397/+686
| | | | | | | | SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>], which is the first time that this syntax has been used.
* aarch64: Add the SME2 predicate-related instructionsRichard Sandiford2023-03-3010-821/+1270
| | | | | | | | | | | | | | | | | Implementation-wise, the main things to note here are: - the WHILE* instructions have forms that return a pair of predicate registers. This is the first time that we've had lists of predicate registers, and they wrap around after register 15 rather than after register 31. - the predicate-as-counter WHILE* instructions have a fourth operand that specifies the vector length. We can treat this as an enumeration, except that immediate values aren't allowed. - PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>]. This is the first instance of a vector/predicate index having no suffix.
* aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford2023-03-3010-448/+2088
| | | | | | | | | | | | | | | SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers. The registers can be consecutive or strided. In the strided case, 2-register lists have a stride of 8, starting at register x0xxx. 4-register lists have a stride of 4, starting at register x00xx. The instructions are predicated on a predicate-as-counter register in the range pn8-pn15. Although we already had register fields with upper bounds of 7 and 15, this is the first plain register operand to have a nonzero lower bound. The patch uses the operand-specific data field to record the minimum value, rather than having separate inserters and extractors for each lower bound. This in turn required adding an extra bit to the field.
* aarch64: Add the SME2 MOVA instructionsRichard Sandiford2023-03-3010-312/+674
| | | | | | | | | | | | | | SME2 defines new MOVA instructions for moving multiple registers to and from ZA. As with SME, the instructions are also available through MOV aliases. One notable feature of these instructions (and many other SME2 instructions) is that some register lists must start at a multiple of the list's size. The patch uses the general error "start register out of range" when this constraint isn't met, rather than an error specifically about multiples. This ensures that the error is consistent between these simple consecutive lists and later strided lists, for which the requirements aren't a simple multiple.
* aarch64: Add support for predicate-as-counter registersRichard Sandiford2023-03-306-1597/+1647
| | | | | | | | | | | | SME2 adds a new format for the existing SVE predicate registers: predicates as counters rather than predicates as masks. In assembly code, operands that interpret predicates as counters are written pn<N> rather than p<N>. This patch adds support for these registers and extends some existing instructions to support them. Since the new forms are just a programmer convenience, there's no need to make them more restrictive than the earlier predicate-as-mask forms.
* aarch64; Add support for vector offset rangesRichard Sandiford2023-03-301-9/+48
| | | | | | | | | | | Some SME2 instructions operate on a range of consecutive ZA vectors. This is indicated by syntax such as: za[<Wv>, <imml>:<immh>] Like with the earlier vgx2 and vgx4 support, we get better error messages if the parser allows all ZA indices to have a range. We can then reject invalid cases during constraint checking.
* aarch64: Add support for vgx2 and vgx4Richard Sandiford2023-03-301-8/+41
| | | | | | | | | | | | | | | | | | | | | | | Many SME2 instructions operate on groups of 2 or 4 ZA vectors. This is indicated by adding a "vgx2" or "vgx4" group size to the ZA index. The group size is optional in assembly but preferred for disassembly. There is not a binary distinction between mnemonics that have group sizes and mnemonics that don't, nor between mnemonics that take vgx2 and mnemonics that take vgx4. We therefore get better error messages if we allow any ZA index to have a group size during parsing, and wait until constraint checking to reject invalid sizes. A quirk of the way errors are reported means that if an instruction is wrong both in its qualifiers and its use of a group size, we'll print suggested alternative instructions that also have an incorrect group size. But that's a general property that also applies to things like out-of-range immediates. It's also not obviously the wrong thing to do. We need to be relatively confident that we're looking at the right opcode before reporting detailed operand-specific errors, so doing qualifier checking first seems resonable.
* aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford2023-03-303-7/+7
| | | | | | | SME2 adds various new fields that are similar to AARCH64_OPND_SME_ZA_array, but are distinguished by the size of their offset fields. This patch adds _off4 to the name of the field that we already have.
* aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford2023-03-306-8/+8
| | | | | SME2 adds various new 3-bit immediate fields, so this patch adds an lsb position suffix to the name of the field that we already have.
* aarch64: Prefer register ranges & support wrappingRichard Sandiford2023-03-301-1/+1
| | | | | | | | | | | | | Until now, binutils has supported register ranges such as { v0.4s - v3.4s } as an unofficial shorthand for { v0.4s, v1.4s, v2.4s, v3.4s }. The SME2 ISA embraces this form and makes it the preferred disassembly. It also embraces wrapped lists such as { z31.s - z2.s }, which is something that binutils didn't previously allow. The range form was already binutils's preferred disassembly for 3- and 4-register lists. This patch prefers it for 2-register lists too. The patch also adds support for wrap-around.
* aarch64: Add support for strided register listsRichard Sandiford2023-03-302-23/+56
| | | | | | | | | | | | | | | | | SME2 has instructions that accept strided register lists, such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this patch is to extend binutils to support such lists. The parsing code already had (unused) support for strides of 2. The idea here is instead to accept all strides during parsing and reject invalid strides during constraint checking. The SME2 instructions that accept strided operands also have non-strided forms. The errors about invalid strides therefore take a bitmask of acceptable strides, which allows multiple possibilities to be summed up in a single message. I've tried to update all code that handles register lists.
* aarch64: Sort fields alphanumericallyRichard Sandiford2023-03-302-163/+164
| | | | | This patch just sorts the field enum alphanumerically, which makes it easier to see if a particular field has already been defined.
* aarch64: Resync field namesRichard Sandiford2023-03-301-7/+7
| | | | | This patch just makes the comments in aarch64-opc.c:fields match the names of the associated FLD_* enum.
* aarch64: Regularise FLD_* suffixesRichard Sandiford2023-03-306-55/+55
| | | | | | | | | | | Some FLD_imm* suffixes used a counting scheme such as FLD_immN, FLD_immN_2, FLD_immN_3, etc., while others used the lsb as the suffix. The latter seems more mnemonic, and was a big help in doing the SME2 work. Similarly, the _10 suffix on FLD_SME_size_10 was nonobvious. Presumably it indicated a 2-bit field, but it actually starts in bit 22.
* aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford2023-03-301-0/+13
| | | | | | | | | | | | | | Quite a lot of SME2 instructions have an opcode bit that selects between 32-bit and 64-bit forms of an instruction, with the 32-bit forms being part of base SME2 and with the 64-bit forms being part of an optional extension. It's nevertheless useful to have a single opcode entry for both forms since (a) that matches the ISA definition and (b) it tends to improve error reporting. This patch therefore adds a libopcodes function called aarch64_cpu_supports_inst_p that tests whether the target supports a particular instruction. In future it will depend on internal libopcodes routines.
* aarch64: Reorder some OP_SVE_* macrosRichard Sandiford2023-03-301-16/+16
| | | | This patch just moves some out-of-order-looking OP_SVE_* macros.
* aarch64: Rename aarch64-tbl.h OP_SME_* macrosRichard Sandiford2023-03-301-81/+77
| | | | | | | | This patch renames the OP_SME_* macros in aarch64-tbl.h so that they follow the same scheme as the OP_SVE_* ones. It also uses OP_SVE_ as the prefix, since there is no real distinction between the SVE and SME uses of qualifiers: a macro defined for one can be useful for the other too.
* aarch64: Try to report invalid variants against the closest matchRichard Sandiford2023-03-303-19/+30
| | | | | | | | | | | | | If an instruction has invalid qualifiers, GAS would report the error against the final opcode entry that got to the qualifier- checking stage. It seems better to report the error against the opcode entry that had the closest match, just like we pick the closest match within an opcode entry for the "did you mean this?" message. This patch adds the number of invalid operands as an argument to AARCH64_OPDE_INVALID_VARIANT and then picks the AARCH64_OPDE_INVALID_VARIANT with the lowest argument.
* aarch64: Make AARCH64_OPDE_REG_LIST take a bitfieldRichard Sandiford2023-03-301-1/+1
| | | | | | | | | | | | | | | | | AARCH64_OPDE_REG_LIST took a single operand that specified the expected number of registers. However, there are quite a few SME2 instructions that have both 2-register forms and (separate) 4-register forms. If the user tries to use a 3-register list, it isn't obvious which opcode entry they meant. Saying that we expect 2 registers and saying that we expect 4 registers would both be wrong. This patch therefore switches the operand to a bitfield. If a AARCH64_OPDE_REG_LIST is reported against multiple opcode entries, the patch ORs up the expected lengths. This has no user-visible effect yet. A later patch adds more error strings, alongside tests that use them.
* aarch64: Add an operand class for SVE register listsRichard Sandiford2023-03-303-14/+13
| | | | | | | | | | | | SVE register lists were classified as SVE_REG, since there had been no particular reason to separate them out. However, some SME2 instructions have tied register list operands, and so we need to distinguish registers and register lists when checking whether two operands match. Also, the register list operands used a general error message, even though we already have a dedicated error code for register lists that are the wrong length.
* aarch64: Commonise checks for index operandsRichard Sandiford2023-03-301-18/+32
| | | | | This patch splits out the constraint checking for index operands, so that it can be reused by new SME2 operands.
* aarch64: Add an error code for out-of-range registersRichard Sandiford2023-03-301-6/+14
| | | | | | | | libopcodes currently reports out-of-range registers as a general AARCH64_OPDE_OTHER_ERROR. However, this means that each register range needs its own hard-coded string, which is a bit cumbersome if the range is determined programmatically. This patch therefore adds a dedicated error type for out-of-range errors.
* aarch64: Move w12-w15 range check to libopcodesRichard Sandiford2023-03-301-6/+20
| | | | | | | | | | | | | | | | | | | In SME, the vector select register had to be in the range w12-w15, so it made sense to enforce that during parsing. However, SME2 adds instructions for which the range is w8-w11 instead. This patch therefore moves the range check from the parsing stage to the constraint-checking stage. Also, the previous error used a capitalised range W12-W15, whereas other register range errors used lowercase ranges like p0-p7. A quick internal poll showed a preference for the lowercase form, so the patch uses that. The patch uses "selection register" rather than "vector select register" so that the terminology extends more naturally to PSEL.
* aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford2023-03-303-25/+67
| | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the range checks on ZA vector select offsets from gas to libopcodes. Doing the checks there means that the error messages contain the expected range. It also fits in better with the error severity scheme, which becomes important later. (This is because out-of-range indices are treated as more severe than syntax errors, on the basis that parsing must have succeeded if we get to the point of checking the completed opcode.) The patch also adds a new check_za_access function for checking ZA accesses. That's a bit over the top for one offset check, but the function becomes more complex with later patches. sme-9-illegal.s checked for an invalid .q suffix using: psel p1, p15, p3.q[w15] but this is doubly invalid because it misses the immediate part of the index. The patch keeps that test but adds another with a zero index, so that .q is the only thing wrong. The aarch64-tbl.h change includes neatening up the backslash positions.
* aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford2023-03-301-3/+3
| | | | | | | | | A later patch moves the range checking for ZA vector select offsets from gas to libopcodes. That in turn requires the immediate field to be big enough to support all parsed values. This shouldn't be a particularly size-sensitive structure, so there should be no memory problems with doing this.
* aarch64: Rename za_tile_vector to za_indexRichard Sandiford2023-03-303-36/+36
| | | | | | | | | za_tile_vector is also used for indexing ZA as a whole, rather than just for indexing tiles. The former is more common than the latter in SME2, so this patch generalises the name to "indexed_za". The patch also names the associated structure, so that later patches can reuse it during parsing.
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