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* Support Intel AMX-COMPLEXHaochen Jiang2023-04-071-3900/+3936
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel AMX-COMPLEX. * config/tc-i386.c: Add amx_complex. * doc/c-i386.texi: Document .amx_complex. * testsuite/gas/i386/i386.exp: Run AMX-COMPLEX tests. * testsuite/gas/i386/amx-complex-inval.l: New test. * testsuite/gas/i386/amx-complex-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-complex-bad.d: Ditto. * testsuite/gas/i386/x86-64-amx-complex-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-complex-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-complex.d: Ditto. * testsuite/gas/i386/x86-64-amx-complex.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_VEX_0F386C_X86_64_W_0): New. (PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0): Ditto. (X86_64_VEX_0F386C): Ditto. (VEX_LEN_0F386C_X86_64_W_0_M_1): Ditto. (VEX_W_0F386C_X86_64): Ditto. (mod_table): Add MOD_VEX_0F386C_X86_64_W_0. (prefix_table): Add PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0. (x86_64_table): Add X86_64_VEX_0F386C. (vex_len_table): Add VEX_LEN_0F386C_X86_64_W_0_M_1. (vex_w_table): Add VEX_W_0F386C_X86_64. * i386-gen.c (cpu_flag_init): Add CPU_AMX_COMPLEX_FLAGS and CPU_ANY_AMX_COMPLEX_FLAGS. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuAMX_COMPLEX): New. (i386_cpu_flags): Add cpuamx_complex. * i386-opc.tbl: Add AMX-COMPLEX instructions. * i386-tbl.h: Regenerated.
* x86: introduce .insn directiveJan Beulich2023-03-311-0/+1
| | | | For starters this deals with only very basic constructs.
* x86: VexVVVV is now merely a booleanJan Beulich2023-03-201-49/+49
| | | | | | | | | | With the SDM long having dropped the NDS/NDD/DDS concept of identifying encoding variants, we can finally do away with this concept as well. Of the few consumers of the attribute, only an assertion was still checking for a particular value, which we don't really need to retain. When touching lines anyway, modernize other aspects as well. This often improves similarity to adjacent lines.
* x86: re-work build_modrm_byte()'s register assignmentJan Beulich2023-03-201-44/+44
| | | | | | | | | | | | | | | | | | The function has accumulated a number of special cases for no real reason. Some were necessary because insn attributes (SwapSources in particular) weren't suitably utilized instead. Note that the addition of SwapSources actually increases consistency among the templates: Like others which already have the attribute, these are all insns where the VEX.VVVV-encoded register comes first (or last when looking at the SDM). Note that the vexvvvv attribute now has merely boolean meaning anymore, in line with the SDM long having dropped the NDS/NDD/DDS concept of identifying encoding variants. The fallout will be taken care of subsequently, though, to not further clutter the change here. As to the TILEZERO special case: If more instructions like this appeared, a new attribute would likely be the way to go. But as long as it's only a single insn, going from the mnemonic is cheaper.
* x86: MONITOR/MWAIT are not SSE3 insnsJan Beulich2023-02-241-6613/+6613
| | | | | These have their own CPUID bit and hence they should also have their own separate control.
* x86-64: don't permit LAHF/SAHF with "generic64"Jan Beulich2023-02-241-4727/+4751
| | | | | | | | The feature isn't universally available on 64-bit CPUs. Note that in i386-gen.c:isa_dependencies[] I'm only adding it to models where I'm certain the functionality exists. For Nocona and Core I'm uncertain in particular.
* x86: have insns acting on segment selector values allow for consistent operandsJan Beulich2023-02-241-892/+954
| | | | | | While MOV to/from segment register as well as selector storing insns already permit 32- and 64-bit GPR operands, selector loading insns and ARPL do not. Split templates accordingly.
* x86: restrict insn templates accepting negative 8-bit immediatesJan Beulich2023-02-241-96/+96
| | | | | | | | | | | | | | | | | | | | For shifts (but not ordinary rotates) and other cases where an immediate describes e.g. a bit count or position, allowing negative operands is at best confusing. An extreme example would be the two rotate-through-carry insns, where a negative value would _not_ mean rotating the corresponding number of bits in the other direction. To refuse such, give meaning to the combination of Imm8 and Imm8S in templates (so far these weren't used together anywhere). The issue was with smallest_imm_type() blindly setting .imm8 for signed numbers determined to fit in a byte. VPROT{B,W,D,Q} is a little special: The rotate count there is a signed quantity, so Imm8 is replaced by Imm8S. Adjust affected testcases accordingly as well. Another small adjustment to the testsuite is necessary: AAM and AAD were never sensible to use with 0xffffff90 operands. This should have been an error.
* x86-64: LAR and LSL don't need REX.WJan Beulich2023-02-221-4/+4
| | | | | | | | | | Just like we suppress emitting REX.W for e.g. MOV from/to segment register, there's also no need for it for LAR and LSL - these can only ever return 32-bit values and hence always zero-extend their results anyway. While there also drop the redundant Word from the first operand of the second template each - this is already implied by Reg16.
* x86: optimize BT{,C,R,S} $imm,%regJan Beulich2023-02-221-4/+4
| | | | | | In 64-bit mode BT can have REX.W or a data size prefix dropped in certain cases. Outside of 64-bit mode all 4 insns can have the data size prefix dropped in certain cases.
* x86: {LD,ST}TILECFG use an extension opcodeJan Beulich2023-02-141-2/+2
| | | | | It being zero and happening to work right now doesn't mean the insns shouldn't be spelled out properly.
* PR30120: fix x87 fucomp misassembledMichael Matz2023-02-131-1/+1
| | | | | this fixes the entry for 'fucomp' to use the correct Reg value (otherwise it's assembled as 'fucom').
* x86: drop use of VEX3SOURCESJan Beulich2023-02-101-7636/+3818
| | | | | | | | | | | | The attribute really specifies that the sum of register and memory operands is 4. Express it like that in most places, while using the 2nd (apart from XOP) CPU feature flags (FMA4) in reversed operand matching logic. With the use in build_modrm_byte() gone, part of an assertion there also becomes meaningless - simplify that at the same time. With all uses of the opcode modifier field gone, also drop that.
* x86: drop use of XOP2SOURCESJan Beulich2023-02-101-24/+24
| | | | | | | | | | The few XOP insns which used it wrongly didn't have VexVVVV specified. With that added, the only further missing piece to use more generic code elsewhere is SwapSources - see e.g. the BMI2 insns for similar operand patterns. With the only users gone, drop the #define as well as the special case code.
* x86: limit use of XOP2SOURCESJan Beulich2023-02-101-4/+4
| | | | | | | | | The VPROT* forms with an immediate operand are entirely standard in the way their ModR/M bytes are built. There's no reason to invoke special case code. With that the handling of an immediate there can also be dropped; it was partially bogus anyway, as in its "no memory operands" portion it ignores the possibility of an immediate operand (which was okay only because that case was already handled by more generic code).
* x86: move (and rename) opcodespace attributeJan Beulich2023-02-101-10947/+10947
| | | | | | | | | | | | This really isn't a "modifier" and rather ought to live next to the base opcode anyway. Use the bits we presently have available to fit in the field, renaming it to opcode_space. As an intended side effect this helps readability at the use sites, by shortening the references quite a bit. In generated code arrange for human readable output, by using the SPACE_* constants there rather than raw numbers. This may aid debugging down the road.
* x86: use ModR/M for FPU insns with operandsJan Beulich2023-01-271-142/+142
| | | | | This is the correct way of expressing things; encoding the ModR/M byte directly in base_opcode has always been bogus.
* x86: re-use insn mnemonic strings as much as possibleJan Beulich2023-01-201-2211/+1860
| | | | | | | Compact the mnemonic string table such that the tails of longer mnemonics are re-used for shorter ones, going beyond what compilers would typically do, but matching what ELF linkers may do when processing SHF_MERGE|SHF_STRINGS sections. This reduces table size by about 12.5%.
* x86: move insn mnemonics to a separate tableJan Beulich2023-01-201-3818/+6144
| | | | | | | | | | | | | | Using full pointers to reference the insn mnemonic strings is not very efficient. With overall string size presently just slightly over 20k, even a 16-bit value would suffice. Use "unsigned int" for now, as there's no good use we could presently make of the otherwise saved 16 bits. For 64-bit builds this reduces table size by 6.25% (prior to the recent ISA extension additions it would have been 12.5%), with a similar effect on cache occupation of table entries accessed. For PIE builds of gas this also reduces the number of base relocations quite a bit (obviously independent of bitness).
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
| | | | | | The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
* x86: change representation of extension opcodeJan Beulich2022-12-161-2/+2
| | | | | | | Having a "None" field in the vast majority of entries is needlessly cluttering the overall table. Instead of this being a separate field, use a representation matching that of Intel SDM and AMD PM for the main use of the field: Append the value after a / as the separator.
* x86: further re-work insn/suffix recognition to also cover MOVSXJan Beulich2022-12-121-937/+889
| | | | | | | | | PR gas/29524 Having templates with a suffix explicitly present has always been quirky. After prior adjustment all that's left to also eliminate the anomaly from move-with-sign-extend is to consolidate the insn templates and to make may_need_pass2() cope (plus extend testsuite coverage).
* x86: drop (now) stray IsStringJan Beulich2022-12-121-13/+13
| | | | | | | | The need for them on the operand-less string insns has gone away with the removal of maybe_adjust_templates() and associated logic. Since i386_index_check() needs adjustment then anyway, take the opportunity and also simplify it, possible again as a result of said removal (plus the opcode template adjustments done here).
* x86: re-work insn/suffix recognitionJan Beulich2022-12-121-1275/+1114
| | | | | | | | | | | | | | | | | | | | | | | | | Having templates with a suffix explicitly present has always been quirky. Introduce a 2nd matching pass in case the 1st one couldn't find a suitable template _and_ didn't itself already need to trim off a suffix to find a match at all. This requires error reporting adjustments (albeit luckily fewer than I was afraid might be necessary), as errors previously reported during matching now need deferring until after the 2nd pass (because, obviously, we must not emit any error if the 2nd pass succeeds). While also related to PR gas/29524, it was requested that move-with-sign-extend be left as broken as it always was. PR gas/29525 Note that with the dropped CMPSD and MOVSD Intel Syntax string insn templates taking operands, mixed IsString/non-IsString template groups (with memory operands) cannot occur anymore. With that maybe_adjust_templates() becomes unnecessary (and is hence being removed). PR gas/29526 Note further that while the additions to the intel16 testcase aren't really proper Intel syntax, we've been permitting all of those except for the MOVD variant. The test therefore is to avoid re-introducing such an inconsistency.
* x86: generate template sets data at build timeJan Beulich2022-12-121-0/+2329
| | | | | | | | Speed up gas startup by avoiding runtime allocation of the instances of type "templates". At the same time cut the memory requirement to just very little over half (not even accounting for any overhead notes_alloc() may incur) by reusing the "end" slot of a preceding entry for the "start" slot of the subsequent one.
* x86: drop sentinel from i386_optab[]Jan Beulich2022-12-121-13/+0
| | | | | | | Now that the table is local to gas, ARRAY_SIZE() can be used to determine the end of the table. Re-arrange the processing loop in md_begin() accordingly, at the same time folding the two calls to notes_alloc() into just one.
* x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodesJan Beulich2022-12-121-3/+3
| | | | | | | | | | | | Unlike many other architectures, x86 does not share an opcode table between assembly and disassembly. Any consumer of libopcodes would only ever access one of the two. Since gas is the only consumer of the assembly data, move it there. While doing so mark respective entities "static" in i386-gen (we may want to do away with i386_regtab_size altogether). This also shrinks the number of relocations to be processed for libopcodes.so by about 30%.
* x86: Allow 16-bit register source for LAR and LSLH.J. Lu2022-12-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
* x86: also use D for XCHG and TESTJan Beulich2022-12-021-51/+6
| | | | | | Leverage the C (commutative) attribute to also reduce the number of XCHG and TEST templates we have. This way the reg <-> r/m (and reg <-> reg for XCHG) forms can also be folded into a single template each, utilizing D.
* x86: drop No_ldSufJan Beulich2022-12-011-11149/+11149
| | | | | With LONG_DOUBLE_MNEM_SUFFIX gone there'salso no use for No_ldSuf anymore.
* x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-011-2/+2
| | | | | | With the removal of its use for FPU insns the suffix is now finally properly misnamed. Drop its use altogether, replacing it by a separate boolean instead.
* x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIXJan Beulich2022-12-011-4/+4
| | | | | | | | As a comment near the top of match_template() already says: We really only need this pseudo-suffix for far branch handling. Stop "deriving" it for floating point insns. (Don't bother renaming the now properly misnamed LONG_DOUBLE_MNEM_SUFFIX, to e.g. FAR_BRANCH_SUFFIX - it's going to disappear anyway.)
* x86: clean up after removal of support for gcc <= 2.8.1Jan Beulich2022-11-301-32/+2
| | | | | | | | | | | | | | | | | At the very least a comment in process_operands() is stale. Beyond that there are effectively two options: 1) It is possible that FADDP and FMULP were mistakenly not marked as being in need of dealing with the compiler anomaly, and hence the respective templates weren't removed at the time when they should have been. 2) It is also possible that there are indeed uses known beyond compiler generated output for these two commutative opcodes, and hence the templates need to stay. To be on the safe side assume 2: Update the comment and fold the templates into their "normal" ones (utilizing D), adjusting consuming code accordingly. For FMULP also add a comment paralleling a similar one FADDP has.
* x86: drop FloatRJan Beulich2022-11-301-11243/+11183
| | | | | | | | | | | | | | There are just 4 templates using it, which can be easily identified by other means, as D is set only on a very limited number of FPU templates. Also move the respective conditional out of the code path taken by all "reverse match" insns (it probably should have been this way already before, to avoid the one conditional in the common case). With this the templates which had FloatR dropped no longer differ from their AT&T syntax + mnemonic counterparts - the only difference is now which of the two would be recognized. For this, however, we don't need two templates - we can simply arrange the condition for setting Opcode_FloatR accordingly.
* x86: widen applicability and use of CheckRegSizeJan Beulich2022-11-241-7/+7
| | | | | | | | | | | | | | | | | | | | | | | First of all make operand_type_register_match() apply to all sized operands, i.e. in Intel Syntax also to respective memory ones. This addresses gas wrongly accepting certain SIMD insns where register and memory operand sizes should match but don't. This apparently has affected all templates with one memory-only operand and one or more register ones, both permitting at least two sizes, due to CheckRegSize not taking effect. Then also add CheckRegSize to a couple of non-SIMD templates matching that same pattern of memory-only vs register operands. This replaces bogus (for Intel Syntax) diagnostics referring to a wrong suffix (when none was used at all) by "type mismatch" ones, just like already emitted for insns where the template allows a register operand alongside a memory one at any particular position. This also is a prereq to limiting (ideally eliminating in the long run) suffix "derivation" in Intel Syntax mode. While making the code adjustment also flip order of checks to do the cheaper one first in both cases.
* x86: add missing CheckRegSizeJan Beulich2022-11-241-3/+3
| | | | | | To properly and predictably determine operand size encoding (operand size or REX.W prefixes), consistent operand sizes need to be specified. Add CheckRegSize where this was previously missing.
* x86: correct handling of LAR and LSLJan Beulich2022-11-241-2/+32
| | | | | | | | Both uniformly only ever take 16-bit memory operands while at the same time requiring matching (in size) register operands, which then also should disassemble that way. This in particular requires splitting each of the templates for the assembler and separating decode of the register and memory forms in the disassembler.
* Add AMD znver4 processor supportTejas Joshi2022-11-151-3838/+3868
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com> gas/ * config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH. (md_assemble): Expand comment before swap_operands() with rmpquery. * doc/c-i386.texi: Add znver4. * testsuite/gas/i386/arch-14-1.d: New. * testsuite/gas/i386/arch-14-1.s: New. * testsuite/gas/i386/arch-14-znver4.d: New. * testsuite/gas/i386/i386.exp: Add new znver4 test cases. * testsuite/gas/i386/rmpquery.d: New. * testsuite/gas/i386/rmpquery.s: New. * testsuite/gas/i386/x86-64-arch-4-1.d: New. * testsuite/gas/i386/x86-64-arch-4-1.s: New. * testsuite/gas/i386/x86-64-arch-4-znver4.d: New. opcodes/ * i386-dis.c (x86_64_table): Add rmpquery. * i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and CPU_RMPQUERY_FLAGS. (cpu_flags): Add CpuRMPQUERY. * i386-opc.h (enum): Add CpuRMPQUERY. (i386_cpu_flags): Add cpurmpquery. * i386-opc.tbl: Add rmpquery insn. * i386-init.h: Re-generated. * i386-tbl.h: Re-generated.
* x86: fold special-operand insn attributes into a single enumJan Beulich2022-11-141-11176/+11176
| | | | | | | | Attributes which aren't used together in any single insn template can be converted from individual booleans to a single enum, as was done for a few other attributes before. This is more space efficient. Collect together all attributes which express special operand constraints (and which fit the criteria for folding).
* x86: drop stray IsString from PadLock insnsJan Beulich2022-11-111-16/+16
| | | | | The need for IsString on the PadLock insns went away with the introduction of RepPrefixOk. Drop these leftovers.
* Support Intel RAO-INTKong Lingling2022-11-081-3923/+3983
| | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel RAO-INT. * config/tc-i386.c: Add raoint. * doc/c-i386.texi: Document .raoint. * testsuite/gas/i386/i386.exp: Run RAO_INT tests. * testsuite/gas/i386/raoint-intel.d: New test. * testsuite/gas/i386/raoint.d: Ditto. * testsuite/gas/i386/raoint.s: Ditto. * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. * testsuite/gas/i386/x86-64-raoint.d: Ditto. * testsuite/gas/i386/x86-64-raoint.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F38FC): New. (prefix_table): Add PREFIX_0F38FC. * i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and CPU_ANY_RAO_INT_FLAGS. * i386-init.h: Regenerated. * i386-opc.h: (CpuRAO_INT): New. (i386_cpu_flags): Add cpuraoint. * i386-opc.tbl: Add RAO_INT instructions. * i386-tbl.h: Regenerated.
* Support Intel AVX-NE-CONVERTkonglin12022-11-041-3914/+4064
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel AVX-NE-CONVERT. * config/tc-i386.c: Add avx_ne_convert. * doc/c-i386.texi: Document .avx_ne_convert. * testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests. * testsuite/gas/i386/avx-ne-convert-intel.d: New test. * testsuite/gas/i386/avx-ne-convert.d: Ditto. * testsuite/gas/i386/avx-ne-convert.s: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto. * testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Mw): New. (PREFIX_VEX_0F3872): Ditto. (PREFIX_VEX_0F38B0_W_0): Ditto. (PREFIX_VEX_0F38B1_W_0): Ditto. (VEX_W_0F3872_P_1): Ditto. (VEX_W_0F38B0): Ditto. (VEX_W_0F38B1): Ditto. (prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0, PREFIX_VEX_0F38B1_W_0. (vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1. * i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and CPU_ANY_AVX_NE_CONVERT_FLAGS. (cpu_flags): Add CpuAVX_NE_CONVERT. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX_NE CONVERT): New. (i386_cpu_flags): Add cpuavx_ne_convert. * i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions. * i386-tbl.h: Regenerated.
* x86: drop bogus TbyteJan Beulich2022-11-021-2/+2
| | | | | | | | | | | Prior to commit 1cb0ab18ad24 ("x86/Intel: restrict suffix derivation") the Tbyte modifier on the FLDT and FSTPT templates was pointless, as No_ldSuf would have prevented it being accepted. Due to the special nature of LONG_DOUBLE_MNEM_SUFFIX said commit, however, has led to these insns being accepted in Intel syntax mode even when "tbyte ptr" was present. Restore original behavior by dropping Tbyte there. (Note that these insns in principle should by marked AT&T syntax only, but since they haven't been so far we probably shouldn't change that.)
* Support Intel MSRLISTHu, Lin12022-11-021-3913/+3939
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated.
* Support Intel WRMSRNSHu, Lin12022-11-021-3913/+3926
| | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated.
* Support Intel CMPccXADDHaochen Jiang2022-11-021-3885/+4395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Support Intel CMPccXADD. * config/tc-i386.c: Add cmpccxadd. (build_modrm_byte): Add operations for Vex.VVVV reg on operand 0 while have memory operand. * doc/c-i386.texi: Document .cmpccxadd. * testsuite/gas/i386/i386.exp: Run CMPccXADD tests. * testsuite/gas/i386/cmpccxadd-inval.s: New test. * testsuite/gas/i386/cmpccxadd-inval.l: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto. * testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto. opcodes/ChangeLog: * i386-dis.c (Mdq): New. (X86_64_VEX_0F38E0): Ditto. (X86_64_VEX_0F38E1): Ditto. (X86_64_VEX_0F38E2): Ditto. (X86_64_VEX_0F38E3): Ditto. (X86_64_VEX_0F38E4): Ditto. (X86_64_VEX_0F38E5): Ditto. (X86_64_VEX_0F38E6): Ditto. (X86_64_VEX_0F38E7): Ditto. (X86_64_VEX_0F38E8): Ditto. (X86_64_VEX_0F38E9): Ditto. (X86_64_VEX_0F38EA): Ditto. (X86_64_VEX_0F38EB): Ditto. (X86_64_VEX_0F38EC): Ditto. (X86_64_VEX_0F38ED): Ditto. (X86_64_VEX_0F38EE): Ditto. (X86_64_VEX_0F38EF): Ditto. (x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1, X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4, X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7, X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA, X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF. * i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and CPU_ANY_CMPCCXADD_FLAGS. (cpu_flags): Add CpuCMPCCXADD. * i386-init.h: Regenerated. * i386-opc.h (CpuCMPCCXADD): New. (i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0. * i386-opc.tbl: Add Intel CMPccXADD instructions. * i386-tbl.h: Regenerated.
* Support Intel AVX-VNNI-INT8Cui,Lili2022-11-021-390/+492
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * NEWS: Support Intel AVX-VNNI-INT8. * config/tc-i386.c: Add avx_vnni_int8. * doc/c-i386.texi: Document avx_vnni_int8. * testsuite/gas/i386/avx-vnni-int8-intel.d: New file. * testsuite/gas/i386/avx-vnni-int8.d: Likewise. * testsuite/gas/i386/avx-vnni-int8.s: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise. * testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests. opcodes/ * i386-dis.c: (PREFIX_VEX_0F3850) New. (PREFIX_VEX_0F3851): Likewise. (VEX_W_0F3850_P_0): Likewise. (VEX_W_0F3850_P_1): Likewise. (VEX_W_0F3850_P_2): Likewise. (VEX_W_0F3850_P_3): Likewise. (VEX_W_0F3851_P_0): Likewise. (VEX_W_0F3851_P_1): Likewise. (VEX_W_0F3851_P_2): Likewise. (VEX_W_0F3851_P_3): Likewise. (VEX_W_0F3850): Delete. (VEX_W_0F3851): Likewise. (prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851. (vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851, delete VEX_W_0F3850 and VEX_W_0F3851. (vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2 VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2 and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851. * i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS and CPU_ANY_AVX_VNNI_INT8_FLAGS. (cpu_flags): Add CpuAVX_VNNI_INT8. * i386-opc.h (CpuAVX_VNNI_INT8): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Support Intel AVX-IFMAHongyu Wang2022-11-021-3888/+3922
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
* Support Intel PREFETCHICui, Lili2022-10-311-3887/+3913
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog: * NEWS: Add support for Intel PREFETCHI instruction. * config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches. (md_assemble): Add warning for illegal input of PREFETCHI. * doc/c-i386.texi: Document .prefetchi. * testsuite/gas/i386/i386.exp: Run PREFETCHI tests. * testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI. * testsuite/gas/i386/x86-64-lfence-load.s: Likewise. * testsuite/gas/i386/x86-64-prefetch.d: New test. * testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise.. * testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise. * testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise. * testsuite/gas/i386/x86-64-prefetchi.d: Likewise. * testsuite/gas/i386/x86-64-prefetchi.s: Likewise. opcodes/ChangeLog: * i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7 (x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0. (mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7. (prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and PREFIX_0F18_REG_7_MOD_0_X86_64. (PREFETCHI_Fixup): New. * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS. (cpu_flags): Add CpuPREFETCHI. * i386-opc.h (CpuPREFETCHI): New. (i386_cpu_flags): Add cpuprefetchi. * i386-opc.tbl: Add Intel PREFETCHI instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
* Support Intel AMX-FP16Cui,Lili2022-10-211-3854/+3871
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gas/ * NEWS: Add support for Intel AMX-FP16 instruction. * config/tc-i386.c: Add amx_fp16. * doc/c-i386.texi: Document .amx_fp16. * testsuite/gas/i386/i386.exp: Add AMX-FP16 tests. * testsuite/gas/i386/x86-64-amx-fp16-intel.d: New test. * testsuite/gas/i386/x86-64-amx-fp16.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16.s: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.d: Likewise. * testsuite/gas/i386/x86-64-amx-fp16-bad.s: Likewise. opcodes/ * i386-dis.c (MOD_VEX_0F385C_X86_64_P_3_W_0): New. (VEX_LEN_0F385C_X86_64_P_3_W_0_M_0): Likewise. (VEX_W_0F385C_X86_64_P_3): Likewise. (prefix_table): Add VEX_W_0F385C_X86_64_P_3. (vex_len_table): Add VEX_LEN_0F385C_X86_64_P_3_W_0_M_0. (vex_w_table): Add VEX_W_0F385C_X86_64_P_3. (mod_table): Add MOD_VEX_0F385C_X86_64_P_3_W_0. * i386-gen.c (cpu_flag_init): Add AMX-FP16_FLAGS. (CPU_ANY_AMX_TILE_FLAGS): Add CpuAMX_FP16. (cpu_flags): Add CpuAMX-FP16. * i386-opc.h (enum): Add CpuAMX-FP16. (i386_cpu_flags): Add cpuamx_fp16. * i386-opc.tbl: Add Intel AMX-FP16 instruction. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
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