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path: root/opcodes/i386-opc.tbl
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* x86: Add int1 as one byte opcode 0xf1H.J. Lu2021-07-141-0/+1
* x86: optimize LEAJan Beulich2021-04-261-1/+1
* x86: move some opcode table entriesJan Beulich2021-03-291-30/+31
* x86: VPSADBW's source operands are also commutativeJan Beulich2021-03-291-3/+3
* x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich2021-03-291-567/+281
* x86: undo Prefix_0X<nn> use in opcode tableJan Beulich2021-03-291-369/+365
* x86-64: don't accept supposedly disabled MOVQ formsJan Beulich2021-03-261-2/+2
* x86: fix AMD Zen3 insnsJan Beulich2021-03-251-3/+7
* x86: derive opcode length from opcode valueJan Beulich2021-03-241-3409/+3409
* x86: don't use opcode_length to identify pseudo prefixesJan Beulich2021-03-241-13/+8
* x86: split opcode prefix and opcode space representationJan Beulich2021-03-231-2142/+2149
* x86: fold some prefix related attributes into a single oneJan Beulich2021-03-091-41/+48
* x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich2021-03-091-1/+1
* x86: infer operand count of templatesJan Beulich2021-03-031-3419/+3419
* x86: CVTPI2PD has special behaviorJan Beulich2021-02-161-1/+3
* x86: have preprocessor expand macrosJan Beulich2021-02-161-0/+5
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-201-0/+26
* Enhancement for avx-vnni patchCui,Lili2020-10-161-4/+4
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-0/+10
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-0/+6
* x86: Support Intel UINTRLili Cui2020-10-141-0/+10
* x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu2020-10-141-344/+344
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-131-2140/+2144
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-0/+9
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-0/+16
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-301-10/+11
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-0/+23
* x86: FMA4 scalar insns ignore VEX.LJan Beulich2020-07-081-16/+16
* x86: Add SwapSourcesH.J. Lu2020-07-021-5/+5
* i386-opc.tbl: Add a blank lineH.J. Lu2020-06-261-0/+1
* x86: Correct VexSIB128 to VecSIB128H.J. Lu2020-06-261-27/+27
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-261-78/+81
* x86: Correct xsusldtrk mnemonicH.J. Lu2020-06-141-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-0/+7
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+6
* x86: use template for AVX512 integer comparison insnsJan Beulich2020-03-091-48/+10
* x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich2020-03-091-100/+13
* x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich2020-03-091-496/+22
* x86: use template for SSE floating point comparison insnsJan Beulich2020-03-091-64/+10
* x86: allow opcode templates to be templatedJan Beulich2020-03-091-90/+6
* x86: reduce amount of various VCVT* templatesJan Beulich2020-03-061-30/+20
* x86: drop/replace IgnoreSizeJan Beulich2020-03-061-699/+699
* x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich2020-03-061-3/+3
* x86: replace NoRex64 on VEX-encoded insnsJan Beulich2020-03-061-25/+25
* x86: drop Rex64 attributeJan Beulich2020-03-061-18/+18
* x86: add missing IgnoreSizeJan Beulich2020-03-061-18/+18
* x86: refine TPAUSE and UMWAITJan Beulich2020-03-061-4/+4
* x86: support VMGEXITJan Beulich2020-03-041-0/+1
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-031-0/+3
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