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* x86: Add CpuCMOV and CpuFXSRH.J. Lu2018-08-111-34/+34
* x86: drop NoRex64 from {,v}pmov{s,z}x*Jan Beulich2018-08-031-24/+24
* x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich2018-07-311-4/+4
* x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich2018-07-311-155/+91
* x86/Intel: correct permitted operand sizes for AVX512 scatter/gatherJan Beulich2018-07-311-62/+62
* x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich2018-07-241-8/+8
* x86: fold narrowing VCVT* templatesJan Beulich2018-07-191-39/+30
* x86: fold VFPCLASSP{D,S} templatesJan Beulich2018-07-191-13/+9
* x86: fold various AVX512* templatesJan Beulich2018-07-191-117/+35
* x86: fold various AVX512DQ templatesJan Beulich2018-07-191-58/+20
* x86: fold various AVX512BW templatesJan Beulich2018-07-191-309/+106
* x86: fold various AVX512CD templatesJan Beulich2018-07-191-20/+4
* x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich2018-07-191-978/+326
* x86: pre-process opcodes table before parsingJan Beulich2018-07-191-0/+6
* x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu2018-07-181-4/+8
* x86: adjust monitor/mwait templatesJan Beulich2018-07-111-14/+12
* x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich2018-07-111-4/+4
* x86: fold MOV to/from segment register templatesJan Beulich2018-06-011-10/+4
* x86: don't emit REX.W for SLDT and STRJan Beulich2018-06-011-2/+2
* x86/Intel: accept "oword ptr" for INVPCIDJan Beulich2018-06-011-2/+2
* x86: Remove Disp<N> from movidir{i,64b}H.J. Lu2018-05-091-3/+3
* Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu2018-05-071-0/+9
* x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu2018-05-071-10/+10
* Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist2018-04-271-10/+0
* Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist2018-04-261-0/+10
* x86: fold various non-memory operand AVX512VL templatesJan Beulich2018-04-261-228/+148
* x86: drop VexImmExtJan Beulich2018-04-261-70/+70
* x86: drop redundant AVX512VL shift templatesJan Beulich2018-04-251-6/+0
* Enable Intel CLDEMOTE instruction.Igor Tsimbalist2018-04-171-0/+6
* x86: Allow 32-bit registers for tpause and umwaitH.J. Lu2018-04-151-4/+2
* Enable Intel WAITPKG instructions.Igor Tsimbalist2018-04-111-0/+13
* x86: drop VecESizeJan Beulich2018-03-281-543/+543
* x86: convert broadcast insn attribute to booleanJan Beulich2018-03-281-1085/+1085
* x86: fold to-scalar-int conversion insnsJan Beulich2018-03-281-43/+21
* x86: drop pointless VecESizeJan Beulich2018-03-221-477/+477
* x86: drop remaining redundant DispNJan Beulich2018-03-221-75/+75
* x86: fix swapped operand handling for BNDMOVJan Beulich2018-03-221-2/+2
* x86/Intel: fix fallout from earlier template foldingJan Beulich2018-03-221-10/+15
* x86: fold a few XOP templatesJan Beulich2018-03-221-16/+8
* x86-64: Also optimize "clr reg64"H.J. Lu2018-03-081-1/+1
* x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu2018-03-081-8/+0
* x86: fold several AVX512VL templatesJan Beulich2018-03-081-185/+90
* x86: fold certain AVX512 rotate and shift templatesJan Beulich2018-03-081-84/+45
* x86: fold VEX-encoded GFNI templatesJan Beulich2018-03-081-8/+3
* x86: fold a few AVX512F templatesJan Beulich2018-03-081-24/+12
* x86: fold LWP templatesJan Beulich2018-03-081-8/+4
* x86: fold FMA and FMA4 templatesJan Beulich2018-03-081-120/+60
* x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich2018-03-081-1/+1
* x86: drop bogus NoAVXJan Beulich2018-03-081-7/+7
* x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich2018-03-081-2/+2
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