summaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.h
Commit message (Expand)AuthorAgeFilesLines
* C99 opcodes configuryAlan Modra2021-04-051-3/+0
* x86: drop seg_entryJan Beulich2021-03-301-14/+1
* x86: drop REGNAM_{AL,AX,EAX}Jan Beulich2021-03-301-5/+0
* x86: adjust st(<N>) parsingJan Beulich2021-03-301-3/+3
* x86: shrink some struct insn_template fieldsJan Beulich2021-03-291-4/+4
* x86: derive opcode length from opcode valueJan Beulich2021-03-241-3/+0
* x86: don't use opcode_length to identify pseudo prefixesJan Beulich2021-03-241-8/+11
* x86: re-number PREFIX_0X<nn>Jan Beulich2021-03-231-5/+6
* x86: re-order two fields of struct insn_templateJan Beulich2021-03-231-3/+3
* x86: split opcode prefix and opcode space representationJan Beulich2021-03-231-16/+21
* x86: fold some prefix related attributes into a single oneJan Beulich2021-03-091-20/+11
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Add AMD znver3 processor supportGanesh Gopalasubramanian2020-10-201-0/+9
* Enhancement for avx-vnni patchCui,Lili2020-10-161-3/+3
* x86: Support Intel AVX VNNIH.J. Lu2020-10-141-0/+6
* x86: Add support for Intel HRESET instructionLili Cui2020-10-141-0/+3
* x86: Support Intel UINTRLili Cui2020-10-141-0/+3
* x86: Rename VexOpcode to OpcodePrefixH.J. Lu2020-10-131-2/+12
* Add support for Intel TDX instructions.Cui,Lili2020-09-241-0/+3
* Enable support to Intel Keylocker instructionsTerry Guo2020-09-231-0/+6
* x86: Add {disp16} pseudo prefixH.J. Lu2020-07-301-0/+12
* x86: Add support for Intel AMX instructionsLili Cui2020-07-101-1/+15
* x86: Add SwapSourcesH.J. Lu2020-07-021-0/+4
* x86: Rename VecSIB to SIB for Intel AMXH.J. Lu2020-06-261-6/+6
* x86: restrict use of register aliasesJan Beulich2020-06-081-1/+1
* Add support for intel TSXLDTRK instructions$Cui,Lili2020-04-071-0/+3
* Add support for intel SERIALIZE instructionLiliCui2020-04-021-0/+3
* x86: drop Rex64 attributeJan Beulich2020-03-061-3/+0
* x86: support VMGEXITJan Beulich2020-03-041-0/+3
* x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu2020-03-031-4/+4
* x86: Remove CpuABM and add CpuPOPCNTH.J. Lu2020-02-171-6/+6
* x86: drop ShortForm attributeJan Beulich2020-02-111-3/+0
* x86: Accept Intel64 only instruction by defaultH.J. Lu2020-02-101-6/+11
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-141-11/+8
* x86: make JumpAbsolute an insn attributeJan Beulich2019-11-141-3/+3
* x86: make AnySize an insn attributeJan Beulich2019-11-141-5/+4
* x86: fold EsSeg into IsStringJan Beulich2019-11-121-6/+8
* x86: eliminate ImmExt abuseJan Beulich2019-11-121-2/+3
* x86: introduce operand type "instance"Jan Beulich2019-11-121-11/+14
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-081-7/+2
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-081-6/+2
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-081-9/+3
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-081-3/+1
* x86: introduce operand type "class"Jan Beulich2019-11-081-4/+13
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-071-0/+6
* x86: slightly rearrange struct insn_templateJan Beulich2019-10-301-4/+4
* x86: drop stray WJan Beulich2019-10-301-1/+3
* x86: drop stale Mem enumeratorJan Beulich2019-07-171-3/+1
* x86: make RegMem an opcode modifierJan Beulich2019-07-161-7/+6
View Lorry Controller Status