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* Add znver1 processorGanesh Gopalasubramanian2015-03-171-0/+5
* ChangeLog rotatation and copyright year updateAlan Modra2015-01-021-2/+2
* Add AVX512VBMI instructionsIlya Tocar2014-11-171-0/+3
* Add AVX512IFMA instructionsIlya Tocar2014-11-171-0/+3
* Add pcommit instructionIlya Tocar2014-11-171-0/+3
* Add clwb instructionIlya Tocar2014-11-171-0/+3
* Add AVX512DQ instructions and their AVX512VL variants.Ilya Tocar2014-07-221-0/+3
* Add support for AVX512BW instructions and their AVX512VL versions.Ilya Tocar2014-07-221-0/+3
* Add support for AVX512VL. Add AVX512VL versions of AVX512F instructions.Ilya Tocar2014-07-221-0/+3
* Add support for Intel SGX instructionsIlya Tocar2014-04-041-0/+3
* Update copyright yearsAlan Modra2014-03-051-3/+2
* Fix various copyright issuesAlan Modra2014-03-031-2/+1
* Add support for CPUID PREFETCHWT1Ilya Tocar2014-02-211-0/+3
* Don't output trailing spaceH.J. Lu2014-02-191-4/+13
* Add clflushopt, xsaves, xsavec, xrstorsIlya Tocar2014-02-121-0/+9
* Update copyright year to 2014H.J. Lu2014-01-081-2/+2
* Remove CpuNop from CPU_K6_2_FLAGSH.J. Lu2013-11-081-1/+1
* Add AMD bdver4 support.Saravanan Ekanathan2013-09-301-0/+2
* Add Intel AVX-512 supportH.J. Lu2013-07-261-2/+33
* Support Intel SHAH.J. Lu2013-07-251-0/+3
* Support Intel MPXH.J. Lu2013-07-241-0/+7
* gas/Saravanan Ekanathan2013-05-151-1/+1
* Implement Intel SMAP instructionsH.J. Lu2013-02-191-0/+3
* Add OPERAND_TYPE_IMM32_64H.J. Lu2013-01-161-0/+2
* Update copyright year to 2013H.J. Lu2013-01-021-2/+2
* Add AMD bdver3 support.Nagajyothi Eggone2012-10-091-0/+2
* Add missing Cpu flags in bd and bt coresH.J. Lu2012-09-251-4/+4
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-201-8/+11
* Add AMD btver1 and btver2 supportH.J. Lu2012-08-171-0/+4
* Enable FMA instructions for bdver2H.J. Lu2012-08-101-1/+1
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-0/+9
* gas/Roland McGrath2012-06-221-8/+9
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-0/+7
* Add vmfuncH.J. Lu2012-01-131-0/+3
* Add initial Intel K1OM support.H.J. Lu2011-07-221-1/+4
* Support AVX Programming Reference (June, 2011).H.J. Lu2011-06-101-2/+15
* Add CpuF16C to CPU_BDVER2_FLAGS.Quentin Neill2011-06-031-1/+1
* 2011-05-10 Quentin Neill <quentin.neill@amd.com>Quentin Neill2011-05-111-0/+2
* * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bitsQuentin Neill2011-04-191-1/+1
* Add support for TBM instructions.Quentin Neill2011-01-171-0/+3
* Implement BMI instructions.H.J. Lu2011-01-051-0/+3
* Update copyright in comments to 2011.H.J. Lu2011-01-011-2/+2
* Update copyright to 2011.H.J. Lu2011-01-011-1/+1
* Add CpuNop to CPU_GENERIC64_FLAGS.H.J. Lu2010-10-161-1/+1
* Add CheckRegSize to instructions which require register size check.H.J. Lu2010-10-141-0/+1
* Don't generate multi-byte NOPs for i686.H.J. Lu2010-08-061-12/+17
* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-011-0/+12
* Update copyright.H.J. Lu2010-02-111-2/+2
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-02-111-0/+3
* 2010-02-03 Quentin Neill <quentin.neill@amd.com>Sebastian Pop2010-02-031-1/+1
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