summaryrefslogtreecommitdiff
path: root/opcodes/aarch64-dis-2.c
Commit message (Expand)AuthorAgeFilesLines
* This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton2018-07-121-903/+906
* Fix AArch64 encodings for by element instructions.Tamar Christina2018-06-291-69/+70
* Correct negs aliasing on AArch64.Tamar Christina2018-06-221-3/+3
* Fix disassembly mask for vector sdot on AArch64.Tamar Christina2018-05-161-158/+178
* Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina2018-05-151-62/+63
* Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton2018-03-281-515/+548
* Add support for the AArch64's CSDB instruction.James Greenhalgh2018-01-091-899/+900
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* Add assembler and disassembler support for the new Armv8.4-a instructions for...Tamar Christina2017-11-161-2924/+3464
* Adds the new Fields and Operand types for the new instructions in Armv8.4-a.Tamar Christina2017-11-091-89/+95
* [AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang2017-07-241-1686/+1686
* [AArch64] Add dot product support for AArch64 to binutilsTamar Christina2017-06-281-179/+203
* [AArch64] Additional SVE instructionsRichard Sandiford2017-02-241-1856/+2294
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* [Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2016-12-131-2/+2
* [AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2016-11-181-2121/+2158
* [AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy2016-11-181-1151/+1184
* [AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy2016-11-181-1270/+1281
* [AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2016-11-181-1197/+1221
* [AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy2016-11-111-1508/+1640
* [AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2016-11-111-1430/+1442
* [AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy2016-11-111-1442/+1640
* [AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy2016-11-111-786/+799
* [AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford2016-09-211-115/+7931
* [AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford2016-09-211-10/+16
* [AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford2016-09-211-25/+32
* [AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford2016-09-211-38/+62
* [AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford2016-09-211-18/+27
* [AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford2016-09-211-19/+57
* [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford2016-09-211-6/+8
* [AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford2016-09-211-5/+7
* [AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford2016-09-211-0/+20
* [AArch64][SVE 16/32] Use specific insert/extract methods for fpimmRichard Sandiford2016-09-211-1/+2
* Copyright update for binutilsAlan Modra2016-01-011-1/+1
* [AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab2015-12-141-674/+682
* [AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab2015-12-141-898/+903
* [AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab2015-12-141-754/+809
* [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab2015-12-141-1154/+1156
* [AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab2015-12-141-1264/+1308
* [AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab2015-12-141-863/+907
* [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab2015-12-141-1184/+1228
* [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab2015-12-141-874/+1094
* [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab2015-12-141-1385/+1704
* [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab2015-12-141-727/+826
* [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab2015-12-141-978/+1242
* [AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab2015-12-111-18/+21
* [AArch64][PATCH 1/2] Add support for RAS instruction ESB.Matthew Wahab2015-12-101-18/+19
* [AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab2015-11-271-437/+537
* [AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab2015-11-271-494/+496
* [AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab2015-11-271-548/+549
View Lorry Controller Status