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* sframe: fix the defined SFRAME_FRE_TYPE_*_LIMIT constantsIndu Bhagat2023-01-062-4/+7
* Add new NT_ARM_ZA and NT_ARM_SSVE register set constants.Luis Machado2023-01-032-0/+9
* Update year range in copyright notice of binutils filesAlan Modra2023-01-01316-316/+316
* Add markers for 2.40 branchNick Clifton2022-12-311-0/+4
* sync libiberty sources with gcc mainlineNick Clifton2022-12-311-0/+20
* RISC-V: Fix T-Head Fmv vendor extension encodingChristoph Müllner2022-12-271-2/+2
* sim: drop unused SIM_ADDR type [PR sim/7504]Mike Frysinger2022-12-221-6/+0
* sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger2022-12-221-2/+4
* sframe.h: add support for .cfi_b_key_frameIndu Bhagat2022-12-221-6/+19
* sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger2022-12-2015-0/+0
* libsframe: provide new access API for mangled RA bitIndu Bhagat2022-12-161-0/+7
* sframe.h: add support for .cfi_negate_ra_stateIndu Bhagat2022-12-161-8/+15
* libsframe asan: avoid generating misaligned loadsIndu Bhagat2022-12-151-2/+6
* libsframe: rename API sframe_fde_func_info to sframe_fde_create_func_infoIndu Bhagat2022-12-091-2/+2
* sframe: gas: libsframe: define constants and remove magic numbersIndu Bhagat2022-12-091-0/+15
* sframe.h: make some macros more preciseIndu Bhagat2022-12-091-3/+4
* Compression tidy and fixesAlan Modra2022-12-071-3/+0
* xtensa: allow dynamic configurationMax Filippov2022-11-281-0/+442
* riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner2022-11-251-0/+68
* RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI2022-11-191-13/+13
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-172-0/+9
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-172-0/+9
* readelf/objdump: support for SFrame sectionIndu Bhagat2022-11-151-0/+3
* bfd: linker: merge .sframe sectionsIndu Bhagat2022-11-153-1/+3
* libsframe: add the SFrame libraryWeimin Pan2022-11-151-0/+231
* sframe.h: Add SFrame format definitionIndu Bhagat2022-11-151-0/+303
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-141-1/+5
* sim: drop unused CORE_ADDR_TYPEMike Frysinger2022-11-081-7/+0
* sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger2022-11-021-3/+2
* sim: reg: constify store helperMike Frysinger2022-10-311-1/+2
* sim: common: change sim_read & sim_write to use void* buffersMike Frysinger2022-10-311-2/+2
* include: Define macro to ignore -Wdeprecated-declarations on GCCTsukasa OI2022-10-281-0/+3
* PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2022-10-271-15/+18
* aarch64-pe support for LD, GAS and BFDJedidiah Thompson2022-10-191-0/+22
* e200 LSP supportAlan Modra2022-10-141-0/+5
* RISC-V: Move certain arrays to riscv-opc.cTsukasa OI2022-10-141-11/+2
* RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI2022-10-041-0/+2
* RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu2022-10-041-7/+7
* RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich2022-10-041-0/+3
* Fix self-move warning check for GCC 13+Jan-Benedict Glaw2022-10-032-0/+8
* LoongArch: Update ELF e_flags handling according to specification.liuzhensong2022-09-301-23/+21
* Support AT_USRSTACKBASE and AT_USRSTACKLIM.John Baldwin2022-09-231-0/+2
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-232-0/+9
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-222-0/+18
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-222-0/+135
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-222-0/+27
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-222-0/+21
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-222-0/+9
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-222-0/+42
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+17
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