PowerPC: Add support for RFC02653 - Dense Math Facility

gas/
	* config/tc-ppc.c (pre_defined_registers): Add dense math registers.
	(md_assemble): Check dmr specified in correct operand.
	* testsuite/gas/ppc/outerprod.s <dmsetaccz, dmxvbf16ger2,
	dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp,
	dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp,
	dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp,
	dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp,
	dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8,
	dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxmfacc,
	dmxxmtacc, pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np,
	pmdmxvbf16ger2pn, pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn,
	pmdmxvf16ger2np, pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger,
	pmdmxvf32gernn, pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp,
	pmdmxvf64ger, pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn,
	pmdmxvf64gerpp, pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s,
	pmdmxvi16ger2spp, pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4,
	pmdmxvi8ger4pp, pmdmxvi8ger4spp>: Add new tests.
	* testsuite/gas/ppc/outerprod.d: Likewise.
	* testsuite/gas/ppc/rfc02653.s: New test.
	* testsuite/gas/ppc/rfc02653.d: Likewise.
	* testsuite/gas/ppc/ppc.exp: Run it.

include/
	* opcode/ppc.h (PPC_OPERAND_DMR): Define.  Renumber following
	PPC_OPERAND defines.

opcodes/
	* ppc-dis.c (print_insn_powerpc): Prepend 'dm' when printing DMR regs.
	* ppc-opc.c (insert_p2, (extract_p2, (insert_xa5, (extract_xa5,
	insert_xb5, (extract_xb5): New functions.
	(insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a): Disallow
	operand overlap only on Power10.
	(DMR, DMRAB, P1, P2, XA5p, XB5p, XDMR_MASK, XDMRDMR_MASK, XX2ACC_MASK,
	XX2DMR_MASK, XX3DMR_MASK): New defines.
	(powerpc_opcodes): Add dmmr, dmsetaccz, dmsetdmrz, dmxor, dmxvbf16ger2,
	dmxvbf16ger2nn, dmxvbf16ger2np, dmxvbf16ger2pn, dmxvbf16ger2pp,
	dmxvf16ger2, dmxvf16ger2nn, dmxvf16ger2np, dmxvf16ger2pn, dmxvf16ger2pp,
	dmxvf32ger, dmxvf32gernn, dmxvf32gernp, dmxvf32gerpn, dmxvf32gerpp,
	dmxvf64ger, dmxvf64gernn, dmxvf64gernp, dmxvf64gerpn, dmxvf64gerpp,
	dmxvi16ger2, dmxvi16ger2pp, dmxvi16ger2s, dmxvi16ger2spp, dmxvi4ger8,
	dmxvi4ger8pp, dmxvi8ger4, dmxvi8ger4pp, dmxvi8ger4spp, dmxxextfdmr256,
	dmxxextfdmr512, dmxxinstdmr256, dmxxinstdmr512, dmxxmfacc, dmxxmtacc,
	pmdmxvbf16ger2, pmdmxvbf16ger2nn, pmdmxvbf16ger2np, pmdmxvbf16ger2pn,
	pmdmxvbf16ger2pp, pmdmxvf16ger2, pmdmxvf16ger2nn, pmdmxvf16ger2np,
	pmdmxvf16ger2pn, pmdmxvf16ger2pp, pmdmxvf32ger, pmdmxvf32gernn,
	pmdmxvf32gernp, pmdmxvf32gerpn, pmdmxvf32gerpp, pmdmxvf64ger,
	pmdmxvf64gernn, pmdmxvf64gernp, pmdmxvf64gerpn, pmdmxvf64gerpp,
	pmdmxvi16ger2, pmdmxvi16ger2pp, pmdmxvi16ger2s, pmdmxvi16ger2spp,
	pmdmxvi4ger8, pmdmxvi4ger8pp, pmdmxvi8ger4, pmdmxvi8ger4pp,
	pmdmxvi8ger4spp.

1 files changed, 18 insertions, 15 deletions

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 930d13d3026..004b51db670 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -384,6 +384,9 @@ extern const unsigned int num_powerpc_operands;
 /* This operand names a VSX accumulator.  */
 #define PPC_OPERAND_ACC (0x20)
 
+/* This operand names a dense math register.  */
+#define PPC_OPERAND_DMR (0x40)
+
 /* This operand may use the symbolic names for the CR fields (even
    without -mregnames), which are
        lt  0	gt  1	eq  2	so  3	un  3
@@ -391,60 +394,60 @@ extern const unsigned int num_powerpc_operands;
        cr4 4	cr5 5	cr6 6	cr7 7
    These may be combined arithmetically, as in cr2*4+gt.  These are
    only supported on the PowerPC, not the POWER.  */
-#define PPC_OPERAND_CR_BIT (0x40)
+#define PPC_OPERAND_CR_BIT (0x80)
 
 /* This is a CR FIELD that does not use symbolic names (unless
    -mregnames is in effect).  If both PPC_OPERAND_CR_BIT and
    PPC_OPERAND_CR_REG are set then treat the field as per
    PPC_OPERAND_CR_BIT for assembly, but as if neither of these
    bits are set for disassembly.  */
-#define PPC_OPERAND_CR_REG (0x80)
+#define PPC_OPERAND_CR_REG (0x100)
 
 /* This operand names a special purpose register.  */
-#define PPC_OPERAND_SPR (0x100)
+#define PPC_OPERAND_SPR (0x200)
 
 /* This operand names a paired-single graphics quantization register.  */
-#define PPC_OPERAND_GQR (0x200)
+#define PPC_OPERAND_GQR (0x400)
 
 /* This operand is a relative branch displacement.  The disassembler
    prints these symbolically if possible.  */
-#define PPC_OPERAND_RELATIVE (0x400)
+#define PPC_OPERAND_RELATIVE (0x800)
 
 /* This operand is an absolute branch address.  The disassembler
    prints these symbolically if possible.  */
-#define PPC_OPERAND_ABSOLUTE (0x800)
+#define PPC_OPERAND_ABSOLUTE (0x1000)
 
 /* This operand takes signed values.  */
-#define PPC_OPERAND_SIGNED (0x1000)
+#define PPC_OPERAND_SIGNED (0x2000)
 
 /* This operand takes signed values, but also accepts a full positive
    range of values when running in 32 bit mode.  That is, if bits is
    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
    this flag is ignored.  */
-#define PPC_OPERAND_SIGNOPT (0x2000)
+#define PPC_OPERAND_SIGNOPT (0x4000)
 
 /* The next operand should be wrapped in parentheses rather than
    separated from this one by a comma.  This is used for the load and
    store instructions which want their operands to look like
        reg,displacement(reg)
    */
-#define PPC_OPERAND_PARENS (0x4000)
+#define PPC_OPERAND_PARENS (0x8000)
 
 /* This operand is for the DS field in a DS form instruction.  */
-#define PPC_OPERAND_DS (0x8000)
+#define PPC_OPERAND_DS (0x10000)
 
 /* This operand is for the DQ field in a DQ form instruction.  */
-#define PPC_OPERAND_DQ (0x10000)
+#define PPC_OPERAND_DQ (0x20000)
 
 /* This operand should be regarded as a negative number for the
    purposes of overflow checking (i.e., the normal most negative
    number is disallowed and one more than the normal most positive
    number is allowed).  This flag will only be set for a signed
    operand.  */
-#define PPC_OPERAND_NEGATIVE (0x20000)
+#define PPC_OPERAND_NEGATIVE (0x40000)
 
 /* Valid range of operand is 0..n rather than 0..n-1.  */
-#define PPC_OPERAND_PLUS1 (0x40000)
+#define PPC_OPERAND_PLUS1 (0x80000)
 
 /* This operand is optional, and is zero if omitted.  This is used for
    example, in the optional BF field in the comparison instructions.  The
@@ -452,7 +455,7 @@ extern const unsigned int num_powerpc_operands;
    and the number of operands remaining for the opcode, and decide
    whether this operand is present or not.  The disassembler should
    print this operand out only if it is not zero.  */
-#define PPC_OPERAND_OPTIONAL (0x80000)
+#define PPC_OPERAND_OPTIONAL (0x100000)
 
 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
    is omitted, then for the next operand use this operand value plus
@@ -460,7 +463,7 @@ extern const unsigned int num_powerpc_operands;
    hack is needed because the Power rotate instructions can take
    either 4 or 5 operands.  The disassembler should print this operand
    out regardless of the PPC_OPERAND_OPTIONAL field.  */
-#define PPC_OPERAND_NEXT (0x100000)
+#define PPC_OPERAND_NEXT (0x200000)
 
 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
    only optional when generating 32-bit code.  */