summaryrefslogtreecommitdiff
path: root/include/opcode
Commit message (Expand)AuthorAgeFilesLines
* riscv: Add AIA extension support (Smaia, Ssaia)Christoph Müllner2022-11-251-0/+68
* RISC-V: Add 'Ssstateen' extension and its CSRsTsukasa OI2022-11-191-13/+13
* RISC-V: Add T-Head Int vendor extensionChristoph Müllner2022-11-172-0/+9
* RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner2022-11-172-0/+9
* aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira2022-11-141-1/+5
* PowerPC: Add support for RFC02653 - Dense Math FacilityPeter Bergner2022-10-271-15/+18
* e200 LSP supportAlan Modra2022-10-141-0/+5
* RISC-V: Move certain arrays to riscv-opc.cTsukasa OI2022-10-141-11/+2
* RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI2022-10-041-0/+2
* RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu2022-10-041-7/+7
* RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich2022-10-041-0/+3
* RISC-V: Add Zawrs ISA extension supportChristoph Müllner2022-09-232-0/+9
* RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner2022-09-222-0/+18
* RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner2022-09-222-0/+135
* RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner2022-09-222-0/+27
* RISC-V: Add T-Head MAC vendor extensionChristoph Müllner2022-09-222-0/+21
* RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner2022-09-222-0/+9
* RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner2022-09-222-0/+42
* RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner2022-09-221-0/+17
* RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner2022-09-222-0/+18
* RISC-V: Add T-Head CMO vendor extensionChristoph Müllner2022-09-222-0/+66
* ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2022-09-121-0/+3
* RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI2022-08-301-0/+1
* ppc/svp64: introduce non-zero operand flagDmitry Selyutin2022-08-111-0/+5
* ppc/svp64: support LibreSOC architectureDmitry Selyutin2022-08-111-0/+3
* libopcodes/aarch64: add support for disassembler stylingAndrew Burgess2022-07-291-1/+27
* RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI2022-07-071-3/+4
* opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess2022-06-291-1/+1
* RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI2022-06-281-0/+10
* RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI2022-06-281-0/+62
* RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI2022-06-281-0/+42
* RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu2022-06-222-25/+26
* RISC-V: Add zhinx extension supports.jiawei2022-05-301-2/+3
* Remove use of bfd_uint64_t and similarAlan Modra2022-05-272-32/+32
* ppc: extend opindex to 16 bitsDmitry Selyutin2022-05-251-1/+7
* RISC-V: Remove RV128-only fmv instructionsTsukasa OI2022-05-201-6/+0
* AArch64: Enable FP16 by default for Armv9-A.Tamar Christina2022-05-181-0/+1
* RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu2022-05-172-0/+77
* RISC-V: Add missing DECLARE_INSNs for Zicbo{m,p,z}Christoph Muellner2022-04-221-0/+9
* gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong2022-03-201-2/+2
* RISC-V: Cache management instructionsTsukasa OI2022-03-182-0/+11
* RISC-V: Prefetch hint instructions and operand setTsukasa OI2022-03-182-0/+8
* Delete PowerPC macro insn supportAlan Modra2022-03-161-26/+0
* PowerPC64 extended instructions in powerpc_macrosAlan Modra2022-03-161-3/+5
* RISC-V: Updated CSRs to privileged spec v1.12 and debug spec v1.0.Nelson Chu2022-02-231-34/+49
* RISC-V: Add Privileged Architecture 1.12 CSRsTsukasa OI2022-02-231-0/+138
* Update year range in copyright notice of binutils filesAlan Modra2022-01-0270-70/+70
* RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta2021-12-241-0/+100
* RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/testsVineet Gupta2021-12-241-20/+0
* arm: Add support for Armv9.1-A to Armv9.3-ARichard Sandiford2021-12-161-0/+7
View Lorry Controller Status