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author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/m32c/sample.ld | |
parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
download | binutils-gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/m32c/sample.ld')
-rw-r--r-- | sim/testsuite/m32c/sample.ld | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/sim/testsuite/m32c/sample.ld b/sim/testsuite/m32c/sample.ld new file mode 100644 index 00000000000..112012a9df0 --- /dev/null +++ b/sim/testsuite/m32c/sample.ld @@ -0,0 +1,41 @@ +/* sample2.ld --- linker script for sample2.x + +Copyright (C) 2005-2021 Free Software Foundation, Inc. +Contributed by Red Hat, Inc. + +This file is part of the GNU simulators. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +/* See the 'sample2.x' target in Makefile.in. */ + +ENTRY(_start) + +MEMORY { + RAM1 (w) : ORIGIN = 0xc800, LENGTH = 0x0200 + RAM2 (w) : ORIGIN = 0xca56, LENGTH = 0x1000 + ROM (w) : ORIGIN = 0x30000, LENGTH = 0x1000 +} + +SECTIONS { + .data : { + *(.data*) + } > RAM1 + .text : { + *(.text*) + } > RAM2 + .fardata : { + *(.fardata*) + } > ROM +} |