sim: testsuite: flatten tree

Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.

1 files changed, 211 insertions, 0 deletions

diff --git a/sim/testsuite/frv/mqmacxhs.cgs b/sim/testsuite/frv/mqmacxhs.cgs
new file mode 100644
index 00000000000..0be1151c69a
--- /dev/null
+++ b/sim/testsuite/frv/mqmacxhs.cgs
@@ -0,0 +1,211 @@
+# frv testcase for mqmacxhs $GRi,$GRj,$ACCk
+# mach: fr400
+
+	.include "testutils.inc"
+
+	start
+
+	.global mqmacxhs
+mqmacxhs:
+	; Positive operands
+	set_fr_iimmed  	2,3,fr8		; multiply small numbers
+	set_fr_iimmed  	2,3,fr10
+	set_fr_iimmed  	0,1,fr9		; multiply by 0
+	set_fr_iimmed  	0,2,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_immed 	6,acc0
+	test_accg_immed 	0,accg1
+	test_acc_immed 	6,acc1
+	test_accg_immed 	0,accg2
+	test_acc_immed 	0,acc2
+	test_accg_immed 	0,accg3
+	test_acc_immed 	0,acc3
+
+	set_fr_iimmed  	2,1,fr8		; multiply by 1
+	set_fr_iimmed  	2,1,fr10
+	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
+	set_fr_iimmed  	0x3fff,2,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_immed 	8,acc0
+	test_accg_immed 	0,accg1
+	test_acc_immed 	8,acc1
+	test_accg_immed 	0,accg2
+	test_acc_limmed	0,0x7ffe,acc2
+	test_accg_immed 	0,accg3
+	test_acc_limmed	0,0x7ffe,acc3
+
+	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
+	set_fr_iimmed  	0x4000,2,fr10
+	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
+	set_fr_iimmed	0x7fff,0x7fff,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_limmed	0x0000,0x8008,acc0
+	test_accg_immed 	0,accg1
+	test_acc_limmed	0x0000,0x8008,acc1
+	test_accg_immed 	0,accg2
+	test_acc_limmed 0x3fff,0x7fff,acc2
+	test_accg_immed 	0,accg3
+	test_acc_limmed 0x3fff,0x7fff,acc3
+
+	; Mixed operands
+	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
+	set_fr_iimmed  	2,0xfffd,fr10
+	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
+	set_fr_iimmed  	0xfffe,1,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_limmed 0x0000,0x8002,acc0
+	test_accg_immed 	0,accg1
+	test_acc_limmed 0x0000,0x8002,acc1
+	test_accg_immed 	0,accg2
+	test_acc_limmed 0x3fff,0x7ffd,acc2
+	test_accg_immed 	0,accg3
+	test_acc_limmed 0x3fff,0x7ffd,acc3
+
+	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
+	set_fr_iimmed  	0xfffe,0,fr10
+	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
+	set_fr_iimmed  	0x2001,0xfffe,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_limmed 0x0000,0x8002,acc0
+	test_accg_immed 	0,accg1
+	test_acc_limmed 0x0000,0x8002,acc1
+	test_accg_immed 	0,accg2
+	test_acc_limmed	0x3fff,0x3ffb,acc2
+	test_accg_immed 	0,accg3
+	test_acc_limmed	0x3fff,0x3ffb,acc3
+
+	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
+	set_fr_iimmed  	0x4000,0xfffe,fr10
+	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
+	set_fr_iimmed	0x7fff,0x8000,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_limmed	0x0000,0x0002,acc0
+	test_accg_immed 	0,accg1
+	test_acc_limmed	0x0000,0x0002,acc1
+	test_accg_immed 	0xff,accg2
+	test_acc_limmed	0xffff,0xbffb,acc2
+	test_accg_immed 	0xff,accg3
+	test_acc_limmed	0xffff,0xbffb,acc3
+
+	; Negative operands
+	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
+	set_fr_iimmed  	0xfffe,0xfffd,fr10
+	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
+	set_fr_iimmed  	0xffff,0xfffe,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_limmed	0x0000,0x0008,acc0
+	test_accg_immed 	0,accg1
+	test_acc_limmed	0x0000,0x0008,acc1
+	test_accg_immed 	0xff,accg2
+	test_acc_limmed	0xffff,0xbffd,acc2
+	test_accg_immed 	0xff,accg3
+	test_acc_limmed	0xffff,0xbffd,acc3
+
+	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
+	set_fr_iimmed	0x8001,0x8001,fr10
+	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
+	set_fr_iimmed	0x8000,0x8000,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
+	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
+	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
+	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
+	test_accg_immed 	0,accg0
+	test_acc_immed 	0x3fff0009,acc0
+	test_accg_immed 	0,accg1
+	test_acc_immed 	0x3fff0009,acc1
+	test_accg_immed 	0,accg2
+	test_acc_immed 	0x3fffbffd,acc2
+	test_accg_immed 	0,accg3
+	test_acc_immed 	0x3fffbffd,acc3
+
+	set_accg_immed 	0x7f,accg0		; saturation
+	set_acc_immed	0xffffffff,acc0
+	set_accg_immed 	0x7f,accg1
+	set_acc_immed	0xffffffff,acc1
+	set_accg_immed 	0x7f,accg2		; saturation
+	set_acc_immed	0xffffffff,acc2
+	set_accg_immed 	0x7f,accg3
+	set_acc_immed	0xffffffff,acc3
+	set_fr_iimmed  	1,1,fr8
+	set_fr_iimmed  	1,1,fr10
+	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
+	set_fr_iimmed  	0x7fff,0x7fff,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
+	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
+	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
+	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
+	test_accg_immed 	0x7f,accg0
+	test_acc_limmed	0xffff,0xffff,acc0
+	test_accg_immed 	0x7f,accg1
+	test_acc_limmed	0xffff,0xffff,acc1
+	test_accg_immed 	0x7f,accg2
+	test_acc_limmed	0xffff,0xffff,acc2
+	test_accg_immed 	0x7f,accg3
+	test_acc_limmed	0xffff,0xffff,acc3
+
+	set_accg_immed 	0x80,accg0		; saturation
+	set_acc_immed	0,acc0
+	set_accg_immed 	0x80,accg1
+	set_acc_immed	0,acc1
+	set_accg_immed 	0x80,accg2		; saturation
+	set_acc_immed	0,acc2
+	set_accg_immed 	0x80,accg3
+	set_acc_immed	0,acc3
+	set_fr_iimmed  	0xffff,0,fr8
+	set_fr_iimmed  	0xffff,1,fr10
+	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
+	set_fr_iimmed  	0x7fff,0x7fff,fr11
+	mqmacxhs      	fr8,fr10,acc0
+	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
+	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
+	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
+	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
+	test_accg_immed 	0x80,accg0
+	test_acc_immed	0,acc0
+	test_accg_immed 	0x80,accg1
+	test_acc_immed	0,acc1
+	test_accg_immed 	0x80,accg2
+	test_acc_immed	0,acc2
+	test_accg_immed 	0x80,accg3
+	test_acc_immed	0,acc3
+
+	pass
+
+