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| author | Mike Frysinger <vapier@gentoo.org> | 2021-01-05 22:09:57 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-15 19:18:34 -0500 |
| commit | 1368b914e93a3af332f787d3d41c106d11bb90da (patch) | |
| tree | 9893ccae5d2d8cbf2ce855e09d6b8f30b56a21bc /sim/testsuite/frv/cfckra.cgs | |
| parent | e403a898b5893337baea73bcb001ece74042f351 (diff) | |
| download | binutils-gdb-1368b914e93a3af332f787d3d41c106d11bb90da.tar.gz | |
sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.
We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim". Since we have no
other dirs in this tree, and no plans to add any, should be fine.
Diffstat (limited to 'sim/testsuite/frv/cfckra.cgs')
| -rw-r--r-- | sim/testsuite/frv/cfckra.cgs | 490 |
1 files changed, 490 insertions, 0 deletions
diff --git a/sim/testsuite/frv/cfckra.cgs b/sim/testsuite/frv/cfckra.cgs new file mode 100644 index 00000000000..0cabd8f47c1 --- /dev/null +++ b/sim/testsuite/frv/cfckra.cgs @@ -0,0 +1,490 @@ +# frv testcase for cfckra $CCj_float,$CCi,$cond +# mach: all + + .include "testutils.inc" + + start + + .global cfckra +cfckra: + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,1 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc0,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc4,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,0 + test_spr_immed 0x1bdb,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc1,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc5,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc2,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc2,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc6,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc6,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x0 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x1 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x2 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x3 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x4 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x5 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x6 0 + cfckra cc3,cc3,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x7 0 + cfckra cc3,cc3,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x8 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0x9 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xa 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xb 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xc 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xd 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xe 0 + cfckra cc3,cc7,0 + test_spr_immed 0x1b1b,cccr + + set_spr_immed 0x1b5b,cccr + set_fcc 0xf 0 + cfckra cc3,cc7,1 + test_spr_immed 0x1b1b,cccr + + pass |