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| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 17:39:33 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 19:33:09 +0800 |
| commit | 716c08de28589a5560b3337f1b935ed84a49b5e5 (patch) | |
| tree | 2da190bad9fdefcdace20dfdbac83ddbff79fc4c /opcodes/mips-opc.c | |
| parent | 36eb4c5f9bbe675a4522a763652f463e5519a955 (diff) | |
| download | binutils-gdb-716c08de28589a5560b3337f1b935ed84a49b5e5.tar.gz | |
[MIPS/GAS] Split Loongson CAM Instructions from loongson3a
bfd/
* elfxx-mips.c (print_mips_ases): Add CAM extension.
binutils/
* readelf.c (print_mips_ases): Add CAM extension.
gas/
* NEWS: Mention Loongson Content Address Memory (CAM)
support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
OPTION_NO_LOONGSON_CAM.
(md_longopts): Likewise.
(mips_ases): Define availability for CAM.
(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
AFL_ASE_LOONGSON_CAM.
(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
(md_show_usage): Add help for -mloongson-cam and
-mno-loongson-cam.
* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
.set loongson-cam and .set noloongson-cam.
* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
* testsuite/gas/mips/loongson-cam.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
* testsuite/gas/mips/loongson-cam.s: Here.
* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
* testsuite/gas/mips/mips.exp: Run loongson-cam test.
include/
* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
* opcode/mips.h (ASE_LOONGSON_CAM): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
descriptors.
(parse_mips_ase_option): Handle -M loongson-cam option.
(print_mips_disassembler_options): Document -M loongson-cam.
* mips-opc.c (LCAM): New macro.
(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
instructions.
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 31532f88a8d..5c9f28a5d1f 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -415,6 +415,9 @@ decode_mips_operand (const char *p) /* Loongson MultiMedia extensions Instructions (MMI) support. */ #define LMMI ASE_LOONGSON_MMI +/* Loongson Content Address Memory (CAM) support. */ +#define LCAM ASE_LOONGSON_CAM + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -459,10 +462,10 @@ const struct mips_opcode mips_builtin_opcodes[] = /* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 instructions. Put them here so that disassembler will find them first. The assemblers uses a hash table based on the instruction name anyhow. */ -{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, -{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, -{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 }, -{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, +{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 }, +{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, {"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, {"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, {"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, |