diff options
| author | Jan Beulich <jbeulich@novell.com> | 2018-04-26 08:48:56 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-04-26 08:48:56 +0200 |
| commit | 59ef5df41e8a2addac4c74bb838fe8295cc79ebf (patch) | |
| tree | 42051518164fa26aa716d64e4db439fa9cb38acc /opcodes/i386-gen.c | |
| parent | 6e041cf4b0b00e85bee85bee98c411f16bd15747 (diff) | |
| download | binutils-gdb-59ef5df41e8a2addac4c74bb838fe8295cc79ebf.tar.gz | |
x86: CpuXSAVE is a prereq for various other features
All of AVX, LWP, MPX, and PKU require XSAVE, and hence it as well as
XRSTOR should be enabled when enabling these ISA extensions. Leverage
these implications to shorten some of the cpu_flag_init[] entries.
Diffstat (limited to 'opcodes/i386-gen.c')
| -rw-r--r-- | opcodes/i386-gen.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 025f00ab8cc..826aa04a8b6 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -88,7 +88,7 @@ static initializer cpu_flag_init[] = { "CPU_AMDFAM10_FLAGS", "CPU_K8_FLAGS|CpuFISTTP|CPU_SSE4A_FLAGS|CpuABM" }, { "CPU_BDVER1_FLAGS", - "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_SSE4_2_FLAGS|CpuSSE4A|CpuABM|CpuFMA4|CpuXOP|CpuLWP|CpuSVME|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" }, + "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_XOP_FLAGS|CpuABM|CpuLWP|CpuSVME|CpuAES|CpuPCLMUL|CpuLZCNT|CpuPRFCHW" }, { "CPU_BDVER2_FLAGS", "CPU_BDVER1_FLAGS|CpuFMA|CpuBMI|CpuTBM|CpuF16C" }, { "CPU_BDVER3_FLAGS", @@ -96,11 +96,11 @@ static initializer cpu_flag_init[] = { "CPU_BDVER4_FLAGS", "CPU_BDVER3_FLAGS|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuMWAITX" }, { "CPU_ZNVER1_FLAGS", - "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_SSE4_2_FLAGS|CpuSSE4A|CpuABM|CpuSVME|CpuXsave|CpuAES|CpuAVX|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" }, + "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuABM|CpuSVME|CpuAES|CpuPCLMUL|CpuLZCNT|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" }, { "CPU_BTVER1_FLAGS", "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuABM|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME|CpuLZCNT" }, { "CPU_BTVER2_FLAGS", - "CPU_BTVER1_FLAGS|CPU_SSE4_2_FLAGS|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuAVX|CpuMovbe|CpuXsave|CpuXsaveopt|CpuPRFCHW" }, + "CPU_BTVER1_FLAGS|CPU_AVX_FLAGS|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuMovbe|CpuXsaveopt|CpuPRFCHW" }, { "CPU_8087_FLAGS", "Cpu8087" }, { "CPU_287_FLAGS", @@ -148,7 +148,7 @@ static initializer cpu_flag_init[] = { "CPU_XOP_FLAGS", "CPU_SSE4A_FLAGS|CPU_FMA4_FLAGS|CpuXOP" }, { "CPU_LWP_FLAGS", - "CpuLWP" }, + "CPU_XSAVE_FLAGS|CpuLWP" }, { "CPU_BMI_FLAGS", "CpuBMI" }, { "CPU_TBM_FLAGS", @@ -192,7 +192,7 @@ static initializer cpu_flag_init[] = { "CPU_ABM_FLAGS", "CpuABM" }, { "CPU_AVX_FLAGS", - "CPU_SSE4_2_FLAGS|CpuAVX" }, + "CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|CpuAVX" }, { "CPU_AVX2_FLAGS", "CPU_AVX_FLAGS|CpuAVX2" }, { "CPU_AVX512F_FLAGS", @@ -240,7 +240,7 @@ static initializer cpu_flag_init[] = { "CPU_SMAP_FLAGS", "CpuSMAP" }, { "CPU_MPX_FLAGS", - "CpuMPX" }, + "CPU_XSAVE_FLAGS|CpuMPX" }, { "CPU_SHA_FLAGS", "CPU_SSE2_FLAGS|CpuSHA" }, { "CPU_CLFLUSHOPT_FLAGS", @@ -260,7 +260,7 @@ static initializer cpu_flag_init[] = { "CPU_MWAITX_FLAGS", "CpuMWAITX" }, { "CPU_OSPKE_FLAGS", - "CpuOSPKE" }, + "CPU_XSAVE_FLAGS|CpuOSPKE" }, { "CPU_RDPID_FLAGS", "CpuRDPID" }, { "CPU_PTWRITE_FLAGS", |