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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:57:43 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:57:43 +0100 |
| commit | 047cd301d40288d13e44f3322541ac28ebe06078 (patch) | |
| tree | 4aa6ac53c8f70e677ea23c6627d94c8e914de3aa /opcodes/aarch64-tbl.h | |
| parent | 165d4950855493dd904a7996e7fcf58880d54219 (diff) | |
| download | binutils-gdb-047cd301d40288d13e44f3322541ac28ebe06078.tar.gz | |
[AArch64][SVE 29/32] Add new SVE core & FP register operands
SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.
gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 367e42bc3ab..f2d5a463307 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2970,6 +2970,10 @@ struct aarch64_opcode aarch64_opcode_table[] = "an SVE predicate register") \ Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ "an SVE predicate register") \ + Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \ + "an integer register or zero") \ + Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \ + "an integer register or SP") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \ F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ @@ -2994,6 +2998,10 @@ struct aarch64_opcode aarch64_opcode_table[] = "an 8-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \ "an 8-bit unsigned immediate") \ + Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \ Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ "an SVE vector register") \ Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ |