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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:15:13 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 20:15:37 +0000 |
| commit | 3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38 (patch) | |
| tree | f8ceee98b93206d0fc7b4180e361dbfa461800b7 /opcodes/aarch64-opc.h | |
| parent | 01a4d0822025084609380fb989d43bda0667db72 (diff) | |
| download | binutils-gdb-3dd032c5fb4eb7fc6bc0341d348da5c75e2d8e38.tar.gz | |
aarch64: [SME] Add SME mode selection and state access instructions
This patch is adding new SME mode selection and state access instructions:
* Add SMSTART and SMSTOP instructions.
* Add SVCR system register.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_sm_za): New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-8-illegal.d: New test.
* testsuite/gas/aarch64/sme-8-illegal.l: New test.
* testsuite/gas/aarch64/sme-8-illegal.s: New test.
* testsuite/gas/aarch64/sme-8.d: New test.
* testsuite/gas/aarch64/sme-8.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_SM_ZA.
(enum aarch64_insn_class): New instruction classes
sme_start and sme_stop.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_pstatefield): New inserter.
(aarch64_ins_sme_sm_za): New inserter.
* aarch64-dis.c (aarch64_ext_imm): New extractor.
(aarch64_ext_pstatefield): New extractor.
(aarch64_ext_sme_sm_za): New extractor.
* aarch64-opc.c (operand_general_constraint_met_p):
New pstatefield value for SME instructions.
(aarch64_print_operand): Printout for OPND_SME_SM_ZA.
(SR_SME): New register SVCR.
* aarch64-opc.h (F_REG_IN_CRM): New register endcoding.
* aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding.
(PSTATE_ENCODE_CRM): Encode CRm field.
(PSTATE_DECODE_CRM): Decode CRm field.
(PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field.
(PSTATE_DECODE_CRM_IMM): Decode CRm immediate field.
(PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate
field.
* aarch64-tbl.h (struct aarch64_opcode): New SMSTART
and SMSTOP instructions.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-opc.h')
| -rw-r--r-- | opcodes/aarch64-opc.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 62aad8bf392..f3000fca4ce 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -243,6 +243,32 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma, #define F_REG_WRITE (1 << 4) /* Register can only be written to but not read from. */ +#undef F_REG_IN_CRM +#define F_REG_IN_CRM (1 << 5) /* Register extra encoding in CRm. */ + +/* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm". + Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME. + In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below + macros to encode and decode CRm encoding. +*/ +#define PSTATE_ENCODE_CRM(val) (val << 6) +#define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f) + +#undef F_IMM_IN_CRM +#define F_IMM_IN_CRM (1 << 10) /* Immediate extra encoding in CRm. */ + +/* Also CRm may contain, in addition to <pstatefield> immediate. + E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode + immediate mask. +*/ +#define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11) +#define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f) + +/* Helper macro to ENCODE CRm and its immediate. */ +#define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \ + (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \ + | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK)) + /* HINT operand flags. */ #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */ |