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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
| commit | ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a (patch) | |
| tree | 9dec9ddf10c70e8d8c16f5f0820eb23eefe4a733 /opcodes/aarch64-opc.c | |
| parent | 80752eb0989b85e88af7f1f4627dbed8a42dfe6d (diff) | |
| download | binutils-gdb-ed429b33c1ee8d6d8f8e640e58f04ec800bc7b2a.tar.gz | |
aarch64: Add the SME2 MLAL and MLSL instructions
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same
encoding. They are the first instance of a ZA (as opposed to ZA tile)
operand having a range of offsets. As with ZA tiles, the expected
range size is encoded in the operand-specific data field.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index cd37f8ac910..9555df186a4 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -319,9 +319,12 @@ const aarch64_field fields[] = { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ + { 2, 1 }, /* imm1_2: general immediate in bits [2]. */ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ { 10, 1 }, /* imm1_10: general immediate in bits [10]. */ + { 15, 1 }, /* imm1_15: general immediate in bits [15]. */ { 16, 1 }, /* imm1_16: general immediate in bits [16]. */ + { 0, 2 }, /* imm2_0: general immediate in bits [1:0]. */ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */ { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */ @@ -1769,6 +1772,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_10: size = get_operand_fields_width (get_operand_from_code (type)) - 4; if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15, 0, (1 << size) - 1)) @@ -1872,6 +1877,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_ZA_array_off2x2: + if (!check_za_access (opnd, mismatch_detail, idx, 8, 3, 2, + get_opcode_dependent_value (opcode))) + return 0; + break; + + case AARCH64_OPND_SME_ZA_array_off3x2: + if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 2, + get_opcode_dependent_value (opcode))) + return 0; + break; + case AARCH64_OPND_SME_ZA_HV_idx_srcxN: case AARCH64_OPND_SME_ZA_HV_idx_destxN: size = aarch64_get_qualifier_esize (opnd->qualifier); @@ -3938,6 +3955,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zn_INDEX: case AARCH64_OPND_SME_Zm_INDEX1: case AARCH64_OPND_SME_Zm_INDEX2: + case AARCH64_OPND_SME_Zm_INDEX3_2: + case AARCH64_OPND_SME_Zm_INDEX3_10: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: @@ -3990,8 +4009,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, print_sme_za_list (buf, size, opnd->reg.regno, styler); break; + case AARCH64_OPND_SME_ZA_array_off2x2: case AARCH64_OPND_SME_ZA_array_off3_0: case AARCH64_OPND_SME_ZA_array_off3_5: + case AARCH64_OPND_SME_ZA_array_off3x2: case AARCH64_OPND_SME_ZA_array_off4: snprintf (buf, size, "%s[%s, %s%s%s%s%s]", style_reg (styler, "za%s%s", |