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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:56 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:56 +0000 |
| commit | e14c9cb6c88e3dbcbaef4e0f62f8e07ece17b51b (patch) | |
| tree | aba47ab38cf70e915e3dd89b2b4530f64ab1f147 /opcodes/aarch64-opc.c | |
| parent | 175eafaf378659f6798c5b1b7591e9a3b1abd042 (diff) | |
| download | binutils-gdb-e14c9cb6c88e3dbcbaef4e0f62f8e07ece17b51b.tar.gz | |
aarch64: Add id_aa64isar2_el1
Armv8.8-A defines a read-only system register called id_aa64isar2_el1.
The register was previously RES0 and should therefore be accepted
at all architecture levels.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en]
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add id_aa64isar2_el1.
gas/
* testsuite/gas/aarch64/sysreg-diagnostic.s: Test writes to
id_aa64isar2_el1.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update accordingly.
* testsuite/gas/aarch64/sysreg-diagnostic.l: Likewise.
* testsuite/gas/aarch64/sysreg.s: Test reads from
id_aa64isar2_el1.
* testsuite/gas/aarch64/sysreg.d: Update accordingly.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 289df9e8848..9b7d7efd437 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4082,6 +4082,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("id_aa64dfr1_el1", CPENC (3,0,C0,C5,1), F_REG_READ), SR_CORE ("id_aa64isar0_el1", CPENC (3,0,C0,C6,0), F_REG_READ), SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ), + SR_CORE ("id_aa64isar2_el1", CPENC (3,0,C0,C6,2), F_REG_READ), SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ), SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ), SR_CORE ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ), |