diff options
| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-04 20:47:06 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-11-04 20:54:13 +0000 |
| commit | 55cc0128349868bec27c472d083cd5aa4271828b (patch) | |
| tree | fd6c990616f890768fd2bd4e4355a90c0ae7cba4 /opcodes/aarch64-opc.c | |
| parent | 9c91c7259122af572d50e5422c982201e4003d04 (diff) | |
| download | binutils-gdb-55cc0128349868bec27c472d083cd5aa4271828b.tar.gz | |
aarch64: Update feature RAS system registers
This patch:
+ updates RAS feature system registers with new RAS 1.1 regs.
+ extends RAS/RAS 1.1 support for all architecture levels of Armv8-A.
Please note that early Armv8-A architectures do not officially support RAS
extension.
Rationale of the patch:
To ease development so that user-friendly RAS system registers operands can be
used. Certain use cases require developers to enable only more generic
architecture (e.g. -march=armv8-a) during system development. Users must use
RAS extension registers bearing in mind that system they use must support it.
The RAS (Reliability, Availability, Serviceability) extension is a
system-level extension that defines a number of system registers.
RAS 1.1 (FEAT_RASv1p1) introduces five new system registers:
ERXPFGCTL_EL1, ERXPFGCDN_EL1, ERXMISC2_EL1, ERXMISC3_EL1 and
ERXPFGF_EL1.
For details see [0].
[0] https://developer.arm.com/docs/ddi0595/i/
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 290a438e5aa..3f142879ed2 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4017,6 +4017,11 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0), SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0), SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0), + SR_RAS ("erxmisc2_el1", CPENC (3,0,C5,C5,2), 0), + SR_RAS ("erxmisc3_el1", CPENC (3,0,C5,C5,3), 0), + SR_RAS ("erxpfgcdn_el1", CPENC (3,0,C5,C4,6), 0), + SR_RAS ("erxpfgctl_el1", CPENC (3,0,C5,C4,5), 0), + SR_RAS ("erxpfgf_el1", CPENC (3,0,C5,C4,4), F_REG_READ), SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0), SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0), SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0), |