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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:11 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:11 +0100 |
| commit | 503fae12992e5dbf48b4e30cea8d35f31d87effe (patch) | |
| tree | c1bd390a4f96d3ac0632de6ce917683fccf56667 /opcodes/aarch64-opc.c | |
| parent | 586c62819f6eb9a77978628afd53ba12c91a11e7 (diff) | |
| download | binutils-gdb-503fae12992e5dbf48b4e30cea8d35f31d87effe.tar.gz | |
aarch64: Add support for predicate-as-counter registers
SME2 adds a new format for the existing SVE predicate registers:
predicates as counters rather than predicates as masks. In assembly
code, operands that interpret predicates as counters are written
pn<N> rather than p<N>.
This patch adds support for these registers and extends some
existing instructions to support them. Since the new forms
are just a programmer convenience, there's no need to make them
more restrictive than the earlier predicate-as-mask forms.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 4df1dc2cda8..1944b8fe87d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3679,6 +3679,19 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, aarch64_get_qualifier_name (opnd->qualifier))); break; + case AARCH64_OPND_SVE_PNd: + case AARCH64_OPND_SVE_PNg4_10: + case AARCH64_OPND_SVE_PNn: + case AARCH64_OPND_SVE_PNt: + if (opnd->qualifier == AARCH64_OPND_QLF_NIL) + snprintf (buf, size, "%s", + style_reg (styler, "pn%d", opnd->reg.regno)); + else + snprintf (buf, size, "%s", + style_reg (styler, "pn%d.%s", opnd->reg.regno, + aarch64_get_qualifier_name (opnd->qualifier))); + break; + case AARCH64_OPND_SVE_Za_5: case AARCH64_OPND_SVE_Za_16: case AARCH64_OPND_SVE_Zd: |