diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:25 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:25 +0000 |
| commit | 3de8c82a4af7c9a0b5901d154cd74b59490aa16e (patch) | |
| tree | 672c25035d4945a84eac519ce6a20b4975d7a263 /opcodes/aarch64-opc.c | |
| parent | ed96bdcba59ec5bba01de1b1db398f338f9200b1 (diff) | |
| download | binutils-gdb-3de8c82a4af7c9a0b5901d154cd74b59490aa16e.tar.gz | |
aarch64: Make LOR registers conditional on +lor
We have a +lor feature flag for the Limited Ordering Regions
extension, but the associated registers didn't use it.
opcodes/
* aarch64-opc.c (SR_LOR): New macro.
(aarch64_sys_regs): Use it for lorc_el1, lorea_el1, lorn_el1 and
lorsa_el1.
gas/
* testsuite/gas/aarch64/sysreg-7.s: Enable +lor.
* testsuite/gas/aarch64/illegal-sysreg-7.s: Test for LOR registers
without +lor.
* testsuite/gas/aarch64/illegal-sysreg-7.d: Update accordingly.
* testsuite/gas/aarch64/illegal-sysreg-7.l: Likewise.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ace7032b7fb..a0959155787 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3990,6 +3990,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, #define SR_V8_3(n,e,f) SR_FEAT (n,e,f,V8_3) #define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4) #define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4) +#define SR_LOR(n,e,f) SR_FEAT (n,e,f,LOR) #define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN) #define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS) #define SR_SME(n,e,f) SR_FEAT (n,e,f,SME) @@ -4714,10 +4715,11 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0), SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ), - SR_CORE ("lorc_el1", CPENC (3,0,C10,C4,3), 0), - SR_CORE ("lorea_el1", CPENC (3,0,C10,C4,1), 0), - SR_CORE ("lorn_el1", CPENC (3,0,C10,C4,2), 0), - SR_CORE ("lorsa_el1", CPENC (3,0,C10,C4,0), 0), + SR_LOR ("lorc_el1", CPENC (3,0,C10,C4,3), 0), + SR_LOR ("lorea_el1", CPENC (3,0,C10,C4,1), 0), + SR_LOR ("lorn_el1", CPENC (3,0,C10,C4,2), 0), + SR_LOR ("lorsa_el1", CPENC (3,0,C10,C4,0), 0), + SR_CORE ("icc_ctlr_el3", CPENC (3,6,C12,C12,4), 0), SR_CORE ("icc_sre_el1", CPENC (3,0,C12,C12,5), 0), SR_CORE ("icc_sre_el2", CPENC (3,4,C12,C9,5), 0), |