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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
| commit | 99e01a66b4c619fb8c7d6f978038eb7a3661c160 (patch) | |
| tree | 7493699028bd43202975111c09e89213f1dd8df7 /opcodes/aarch64-asm.h | |
| parent | b408ebbf526e7293f08825d04b34c7d2ad7fc753 (diff) | |
| download | binutils-gdb-99e01a66b4c619fb8c7d6f978038eb7a3661c160.tar.gz | |
aarch64: Add the SME2 predicate-related instructions
Implementation-wise, the main things to note here are:
- the WHILE* instructions have forms that return a pair of predicate
registers. This is the first time that we've had lists of predicate
registers, and they wrap around after register 15 rather than after
register 31.
- the predicate-as-counter WHILE* instructions have a fourth operand
that specifies the vector length. We can treat this as an enumeration,
except that immediate values aren't allowed.
- PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>].
This is the first instance of a vector/predicate index having
no suffix.
Diffstat (limited to 'opcodes/aarch64-asm.h')
| -rw-r--r-- | opcodes/aarch64-asm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index f74cb718f3e..4cc48dfdcb6 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -110,6 +110,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_pred_reg_with_index); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30); +AARCH64_DECL_OPD_INSERTER (ins_simple_index); #undef AARCH64_DECL_OPD_INSERTER |