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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
| commit | b408ebbf526e7293f08825d04b34c7d2ad7fc753 (patch) | |
| tree | 3331d54d3c7cafb02746194a07d78646b65f5c73 /opcodes/aarch64-asm.h | |
| parent | d8773a8a5f5614f508d9919cb7626ae0497b8141 (diff) | |
| download | binutils-gdb-b408ebbf526e7293f08825d04b34c7d2ad7fc753.tar.gz | |
aarch64: Add the SME2 multivector LD1 and ST1 instructions
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided. In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.
The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15. Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound. The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound. This in turn required adding
an extra bit to the field.
Diffstat (limited to 'opcodes/aarch64-asm.h')
| -rw-r--r-- | opcodes/aarch64-asm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index eb881707b65..f74cb718f3e 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -96,6 +96,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_index); AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov); AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index); AARCH64_DECL_OPD_INSERTER (ins_sve_reglist); +AARCH64_DECL_OPD_INSERTER (ins_sve_strided_reglist); AARCH64_DECL_OPD_INSERTER (ins_sve_scale); AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm); AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm); |