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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:07 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:07 +0100 |
| commit | db3c06bf93f577b9eb40e2cc5d67bfd0671d3c11 (patch) | |
| tree | d1cd2d63644a790b06a36afea900ccc5a509c302 /include | |
| parent | 56ead579a51f797beebc0d7745a613895383fe51 (diff) | |
| download | binutils-gdb-db3c06bf93f577b9eb40e2cc5d67bfd0671d3c11.tar.gz | |
aarch64: Add an operand class for SVE register lists
SVE register lists were classified as SVE_REG, since there had been
no particular reason to separate them out. However, some SME2
instructions have tied register list operands, and so we need to
distinguish registers and register lists when checking whether two
operands match.
Also, the register list operands used a general error message,
even though we already have a dedicated error code for register
lists that are the wrong length.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 6615dec41a7..d09897f48d4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -224,6 +224,7 @@ enum aarch64_operand_class AARCH64_OPND_CLASS_SISD_REG, AARCH64_OPND_CLASS_SIMD_REGLIST, AARCH64_OPND_CLASS_SVE_REG, + AARCH64_OPND_CLASS_SVE_REGLIST, AARCH64_OPND_CLASS_PRED_REG, AARCH64_OPND_CLASS_ZA_ACCESS, AARCH64_OPND_CLASS_ADDRESS, |