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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
| commit | b408ebbf526e7293f08825d04b34c7d2ad7fc753 (patch) | |
| tree | 3331d54d3c7cafb02746194a07d78646b65f5c73 /include | |
| parent | d8773a8a5f5614f508d9919cb7626ae0497b8141 (diff) | |
| download | binutils-gdb-b408ebbf526e7293f08825d04b34c7d2ad7fc753.tar.gz | |
aarch64: Add the SME2 multivector LD1 and ST1 instructions
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers.
The registers can be consecutive or strided. In the strided case,
2-register lists have a stride of 8, starting at register x0xxx.
4-register lists have a stride of 4, starting at register x00xx.
The instructions are predicated on a predicate-as-counter register in
the range pn8-pn15. Although we already had register fields with upper
bounds of 7 and 15, this is the first plain register operand to have a
nonzero lower bound. The patch uses the operand-specific data field
to record the minimum value, rather than having separate inserters
and extractors for each lower bound. This in turn required adding
an extra bit to the field.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 4d2e054c7f8..d34cea5efca 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -489,6 +489,8 @@ enum aarch64_opnd AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ + AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ + AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */ AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ @@ -496,6 +498,7 @@ enum aarch64_opnd AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */ AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ + AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */ |