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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:12 +0100 |
| commit | d8773a8a5f5614f508d9919cb7626ae0497b8141 (patch) | |
| tree | 5ba56e29d3a94109568b7f1d01c7330863d007e2 /include | |
| parent | 503fae12992e5dbf48b4e30cea8d35f31d87effe (diff) | |
| download | binutils-gdb-d8773a8a5f5614f508d9919cb7626ae0497b8141.tar.gz | |
aarch64: Add the SME2 MOVA instructions
SME2 defines new MOVA instructions for moving multiple registers
to and from ZA. As with SME, the instructions are also available
through MOV aliases.
One notable feature of these instructions (and many other SME2
instructions) is that some register lists must start at a multiple
of the list's size. The patch uses the general error "start register
out of range" when this constraint isn't met, rather than an error
specifically about multiples. This ensures that the error is
consistent between these simple consecutive lists and later
strided lists, for which the requirements aren't a simple multiple.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 34893584065..4d2e054c7f8 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -485,13 +485,21 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ + AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ + AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ + AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */ AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */ AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */ + AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */ AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ @@ -669,9 +677,11 @@ enum aarch64_insn_class sme_mov, sme_ldr, sme_psel, + sme_size_22, sme_str, sme_start, sme_stop, + sme2_mov, sve_cpy, sve_index, sve_limm, |