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| author | Ruiling Song <ruiling.song@intel.com> | 2014-05-16 11:26:30 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2014-05-16 20:01:54 +0800 |
| commit | 3cdc1037d0a7c11b6d35f0b0474fa96656c4c98d (patch) | |
| tree | eb2aa6a1be6cdb2b953d601bef6da17daf7dfec1 /src/intel/intel_defines.h | |
| parent | 9d93bfe2a1e7684b526a2d4ba0fee95e2a6e0b30 (diff) | |
| download | beignet-3cdc1037d0a7c11b6d35f0b0474fa96656c4c98d.tar.gz | |
Runtime: Fix a bug in L3 configuration.
We forgot to set L3SQCREG1 register.
And also add a more suitable configuration.
This patch improves Luxmark score above 50%.
Signed-off-by: Ruiling Song <ruiling.song@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Diffstat (limited to 'src/intel/intel_defines.h')
| -rw-r--r-- | src/intel/intel_defines.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/intel_defines.h b/src/intel/intel_defines.h index 5139e439..02ffde47 100644 --- a/src/intel/intel_defines.h +++ b/src/intel/intel_defines.h @@ -299,6 +299,7 @@ IS_G4X(intel->device_id) ? 384 : 256) // L3 cache stuff +#define GEN7_L3_SQC_REG1_ADDRESS_OFFSET (0XB010) #define GEN7_L3_CNTL_REG2_ADDRESS_OFFSET (0xB020) #define GEN7_L3_CNTL_REG3_ADDRESS_OFFSET (0xB024) |