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Diffstat (limited to 'src/VBox/Devices/Graphics/DevVGA.h')
-rw-r--r--src/VBox/Devices/Graphics/DevVGA.h145
1 files changed, 140 insertions, 5 deletions
diff --git a/src/VBox/Devices/Graphics/DevVGA.h b/src/VBox/Devices/Graphics/DevVGA.h
index f576fda9..aad2b43c 100644
--- a/src/VBox/Devices/Graphics/DevVGA.h
+++ b/src/VBox/Devices/Graphics/DevVGA.h
@@ -4,7 +4,7 @@
*/
/*
- * Copyright (C) 2006-2007 Oracle Corporation
+ * Copyright (C) 2006-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
@@ -64,6 +64,12 @@
#endif /* VBOX_WITH_HGSMI */
#include "DevVGASavedState.h"
+#ifdef VBOX_WITH_VMSVGA
+# include "DevVGA-SVGA.h"
+#endif
+
+# include <iprt/list.h>
+
#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT 0x20
@@ -195,6 +201,16 @@ typedef void FNCURSORDRAWLINE(struct VGAState *s, uint8_t *d, int y);
typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
#endif
+#ifdef VBOX_WITH_VIDEOHWACCEL
+#define VBOX_VHWA_MAX_PENDING_COMMANDS 1000
+
+typedef struct _VBOX_VHWA_PENDINGCMD
+{
+ RTLISTNODE Node;
+ PVBOXVHWACMD pCommand;
+} VBOX_VHWA_PENDINGCMD;
+#endif
+
typedef struct VGAState {
#ifndef VBOX
VGA_STATE_COMMON
@@ -259,8 +275,7 @@ typedef struct VGAState {
PPDMDEVINSRC pDevInsRC;
/** Pointer to the GC vram mapping. */
RCPTRTYPE(uint8_t *) vram_ptrRC;
- /** Pointer to vgaGCLFBAccessHandler(). */
- RTRCPTR RCPtrLFBHandler;
+ uint32_t PaddingMinus1;
/** Pointer to the device instance - R3 Ptr. */
PPDMDEVINSR3 pDevInsR3;
@@ -278,6 +293,9 @@ typedef struct VGAState {
/** LUN\#0: VBVA callbacks interface */
PDMIDISPLAYVBVACALLBACKS IVBVACallbacks;
# endif
+# if HC_ARCH_BITS == 32
+ uint32_t Padding0;
+# endif
/** Pointer to base interface of the driver. */
R3PTRTYPE(PPDMIBASE) pDrvBase;
/** Pointer to display connector interface of the driver. */
@@ -291,6 +309,81 @@ typedef struct VGAState {
/** The R0 vram pointer... */
R0PTRTYPE(uint8_t *) vram_ptrR0;
+#ifdef VBOX_WITH_VMSVGA
+ struct
+ {
+ /** The host window handle */
+ uint64_t u64HostWindowId;
+ /** The R3 FIFO pointer. */
+ R3PTRTYPE(uint32_t *) pFIFOR3;
+ /** The R0 FIFO pointer. */
+ R0PTRTYPE(uint32_t *) pFIFOR0;
+ /** R3 Opaque pointer to svga state. */
+ R3PTRTYPE(void *) pSVGAState;
+ /** R3 Opaque pointer to 3d state. */
+ R3PTRTYPE(void *) p3dState;
+ /** R3 Opaque pointer to a copy of the first 32k of the framebuffer before switching into svga mode. */
+ R3PTRTYPE(void *) pFrameBufferBackup;
+#if HC_ARCH_BITS == 32
+ uint32_t Padding3;
+#endif
+ /** Guest physical address of the FIFO memory range. */
+ RTGCPHYS GCPhysFIFO;
+ /** Size in bytes of the FIFO memory range. */
+ uint32_t cbFIFO;
+ /** SVGA id. */
+ uint32_t u32SVGAId;
+ /** SVGA extensions enabled or not. */
+ uint32_t fEnabled;
+ /** SVGA memory area configured status. */
+ uint32_t fConfigured;
+ /** Device is busy handling FIFO requests. */
+ uint32_t fBusy;
+ /** Traces (dirty page detection) enabled or not. */
+ uint32_t fTraces;
+ /** Guest OS identifier. */
+ uint32_t u32GuestId;
+ /** Scratch region size. */
+ uint32_t cScratchRegion;
+ /** Scratch array. */
+ uint32_t au32ScratchRegion[VMSVGA_SCRATCH_SIZE];
+ /** Irq status. */
+ uint32_t u32IrqStatus;
+ /** Irq mask. */
+ uint32_t u32IrqMask;
+ /** Pitch lock. */
+ uint32_t u32PitchLock;
+ /** Current GMR id. (SVGA_REG_GMR_ID) */
+ uint32_t u32CurrentGMRId;
+ /** Register caps. */
+ uint32_t u32RegCaps;
+ /** Physical address of command mmio range. */
+ uint32_t Padding2;
+ RTIOPORT BasePort;
+ /** Port io index register. */
+ uint32_t u32IndexReg;
+ /** FIFO request semaphore. */
+ RTSEMEVENT FIFORequestSem;
+ /** FIFO IO Thread. */
+ R3PTRTYPE(PPDMTHREAD) pFIFOIOThread;
+ int32_t iWidth;
+ int32_t iHeight;
+ uint32_t iBpp;
+ uint32_t cbScanline;
+ /** Maximum width supported. */
+ uint32_t u32MaxWidth;
+ /** Maximum height supported. */
+ uint32_t u32MaxHeight;
+ /** Action flags */
+ uint32_t u32ActionFlags;
+ /** SVGA 3d extensions enabled or not. */
+ bool f3DEnabled;
+ /** VRAM page monitoring enabled or not. */
+ bool fVRAMTracking;
+ bool Padding6[2];
+ } svga;
+#endif
+
/** The number of monitors. */
uint32_t cMonitors;
/** Current refresh timer interval. */
@@ -310,12 +403,18 @@ typedef struct VGAState {
bool fRemappedVGA;
/** Whether to render the guest VRAM to the framebuffer memory. False only for some LFB modes. */
bool fRenderVRAM;
+#ifdef VBOX_WITH_VMSVGA
+ /* Whether the SVGA emulation is enabled or not. */
+ bool fVMSVGAEnabled;
+ bool Padding1[1];
+#else
bool Padding1[2];
+#endif
/** The physical address the VRAM was assigned. */
RTGCPHYS GCPhysVRAM;
- /** The critical section. */
- PDMCRITSECT lock;
+ /** The critical section protect the instance data. */
+ PDMCRITSECT CritSect;
/** The PCI device. */
PCIDEVICE Dev;
@@ -418,6 +517,21 @@ typedef struct VGAState {
uint8_t Padding10[14];
# endif
# endif /* VBOX_WITH_HGSMI */
+
+ struct {
+ volatile uint32_t cPending;
+ uint32_t Padding1;
+ union
+ {
+ RTLISTNODE PendingList;
+ /* make sure the structure sized cross different contexts correctly */
+ struct
+ {
+ R3PTRTYPE(void *) dummy1;
+ R3PTRTYPE(void *) dummy2;
+ } dummy;
+ };
+ } pendingVhwaCommands;
#endif /* VBOX */
} VGAState;
#ifdef VBOX
@@ -479,10 +593,13 @@ int VBVAInit (PVGASTATE pVGAState);
void VBVADestroy (PVGASTATE pVGAState);
int VBVAUpdateDisplay (PVGASTATE pVGAState);
void VBVAReset (PVGASTATE pVGAState);
+void VBVAPause (PVGASTATE pVGAState, bool fPause);
+int VBVAGetScreenInfo(PVGASTATE pVGAState, unsigned uScreenId, struct VBVAINFOSCREEN *pScreen, void **ppvVram);
bool VBVAIsEnabled(PVGASTATE pVGAState);
void VBVARaiseIrq (PVGASTATE pVGAState, uint32_t fFlags);
+void VBVARaiseIrqNoWait(PVGASTATE pVGAState, uint32_t fFlags);
/* @return host-guest flags that were set on reset
* this allows the caller to make further cleaning when needed,
@@ -494,6 +611,8 @@ int vbvaVHWACommandCompleteAsynch(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVHW
int vbvaVHWAConstruct (PVGASTATE pVGAState);
int vbvaVHWAReset (PVGASTATE pVGAState);
+void vbvaTimerCb(PVGASTATE pVGAState);
+
int vboxVBVASaveStatePrep (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
int vboxVBVASaveStateDone (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
# endif
@@ -506,6 +625,10 @@ int vboxVBVASaveStateDone (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
int vboxVDMACrHgsmiCommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVDMACMD_CHROMIUM_CMD pCmd, int rc);
int vboxVDMACrHgsmiControlCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVDMACMD_CHROMIUM_CTL pCmd, int rc);
# endif
+int vboxCmdVBVACmdHostCtl(PPDMIDISPLAYVBVACALLBACKS pInterface,
+ struct VBOXCRCMDCTL* pCmd, uint32_t cbCmd,
+ PFNCRCTLCOMPLETION pfnCompletion,
+ void *pvCompletion);
int vboxVBVASaveStateExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
int vboxVBVALoadStateExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t u32Version);
@@ -515,14 +638,26 @@ int vboxVBVALoadStateDone (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
typedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
int vboxVDMAConstruct(PVGASTATE pVGAState, uint32_t cPipeElements);
int vboxVDMADestruct(PVBOXVDMAHOST pVdma);
+int vboxVDMAReset(PVBOXVDMAHOST pVdma);
void vboxVDMAControl(PVBOXVDMAHOST pVdma, PVBOXVDMA_CTL pCmd, uint32_t cbCmd);
void vboxVDMACommand(PVBOXVDMAHOST pVdma, PVBOXVDMACBUF_DR pCmd, uint32_t cbCmd);
int vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
int vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
# endif /* VBOX_WITH_VDMA */
+int vboxCmdVBVACmdSubmit(PVGASTATE pVGAState);
+int vboxCmdVBVACmdFlush(PVGASTATE pVGAState);
+void vboxCmdVBVACmdTimer(PVGASTATE pVGAState);
+int vboxCmdVBVACmdCtl(PVGASTATE pVGAState, VBOXCMDVBVA_CTL *pCtl, uint32_t cbCtl);
+
#endif /* VBOX_WITH_HGSMI */
+# ifdef VBOX_WITH_VMSVGA
+int vgaR3RegisterVRAMHandler(PVGASTATE pVGAState, uint64_t cbFrameBuffer);
+int vgaR3UnregisterVRAMHandler(PVGASTATE pVGAState);
+int vgaR3UpdateDisplay(PVGASTATE pVGAState, unsigned xStart, unsigned yStart, unsigned width, unsigned height);
+# endif
+
#ifndef VBOX
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
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