diff options
| author | Lorry Tar Creator <lorry-tar-importer@baserock.org> | 2014-03-26 19:21:20 +0000 |
|---|---|---|
| committer | <> | 2014-05-08 15:03:54 +0000 |
| commit | fb123f93f9f5ce42c8e5785d2f8e0edaf951740e (patch) | |
| tree | c2103d76aec5f1f10892cd1d3a38e24f665ae5db /src/VBox/VMM/testcase | |
| parent | 58ed4748338f9466599adfc8a9171280ed99e23f (diff) | |
| download | VirtualBox-master.tar.gz | |
Imported from /home/lorry/working-area/delta_VirtualBox/VirtualBox-4.3.10.tar.bz2.HEADVirtualBox-4.3.10master
Diffstat (limited to 'src/VBox/VMM/testcase')
46 files changed, 6084 insertions, 467 deletions
diff --git a/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py b/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py new file mode 100755 index 00000000..6d506d19 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py @@ -0,0 +1,2239 @@ +#!/usr/bin/env python +# -*- coding: utf-8 -*- +# $Id: InstructionTestGen.py $ + +""" +Instruction Test Generator. +""" + +from __future__ import print_function; + +__copyright__ = \ +""" +Copyright (C) 2012-2013 Oracle Corporation + +This file is part of VirtualBox Open Source Edition (OSE), as +available from http://www.virtualbox.org. This file is free software; +you can redistribute it and/or modify it under the terms of the GNU +General Public License (GPL) as published by the Free Software +Foundation, in version 2 as it comes in the "COPYING" file of the +VirtualBox OSE distribution. VirtualBox OSE is distributed in the +hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +""" +__version__ = "$Revision: 90928 $"; + + +# pylint: disable=C0103,R0913 + + +# Standard python imports. +import io; +import os; +from optparse import OptionParser +import random; +import sys; + + +## @name Exit codes +## @{ +RTEXITCODE_SUCCESS = 0; +RTEXITCODE_SYNTAX = 2; +## @} + +## @name Various C macros we're used to. +## @{ +UINT8_MAX = 0xff +UINT16_MAX = 0xffff +UINT32_MAX = 0xffffffff +UINT64_MAX = 0xffffffffffffffff +def RT_BIT_32(iBit): # pylint: disable=C0103 + """ 32-bit one bit mask. """ + return 1 << iBit; +def RT_BIT_64(iBit): # pylint: disable=C0103 + """ 64-bit one bit mask. """ + return 1 << iBit; +## @} + + +## @name ModR/M +## @{ +X86_MODRM_RM_MASK = 0x07; +X86_MODRM_REG_MASK = 0x38; +X86_MODRM_REG_SMASK = 0x07; +X86_MODRM_REG_SHIFT = 3; +X86_MODRM_MOD_MASK = 0xc0; +X86_MODRM_MOD_SMASK = 0x03; +X86_MODRM_MOD_SHIFT = 6; +## @} + +## @name SIB +## @{ +X86_SIB_BASE_MASK = 0x07; +X86_SIB_INDEX_MASK = 0x38; +X86_SIB_INDEX_SMASK = 0x07; +X86_SIB_INDEX_SHIFT = 3; +X86_SIB_SCALE_MASK = 0xc0; +X86_SIB_SCALE_SMASK = 0x03; +X86_SIB_SCALE_SHIFT = 6; +## @} + +## @name Prefixes +## @ +X86_OP_PRF_CS = 0x2e; +X86_OP_PRF_SS = 0x36; +X86_OP_PRF_DS = 0x3e; +X86_OP_PRF_ES = 0x26; +X86_OP_PRF_FS = 0x64; +X86_OP_PRF_GS = 0x65; +X86_OP_PRF_SIZE_OP = 0x66; +X86_OP_PRF_SIZE_ADDR = 0x67; +X86_OP_PRF_LOCK = 0xf0; +X86_OP_PRF_REPZ = 0xf2; +X86_OP_PRF_REPNZ = 0xf3; +X86_OP_REX_B = 0x41; +X86_OP_REX_X = 0x42; +X86_OP_REX_R = 0x44; +X86_OP_REX_W = 0x48; +## @} + + +## @name General registers +## @ +X86_GREG_xAX = 0 +X86_GREG_xCX = 1 +X86_GREG_xDX = 2 +X86_GREG_xBX = 3 +X86_GREG_xSP = 4 +X86_GREG_xBP = 5 +X86_GREG_xSI = 6 +X86_GREG_xDI = 7 +X86_GREG_x8 = 8 +X86_GREG_x9 = 9 +X86_GREG_x10 = 10 +X86_GREG_x11 = 11 +X86_GREG_x12 = 12 +X86_GREG_x13 = 13 +X86_GREG_x14 = 14 +X86_GREG_x15 = 15 +## @} + + +## @name Register names. +## @{ +g_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15'); +g_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15'); +g_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi', + 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d'); +g_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi', + 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d'); +g_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di', + 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w'); +g_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di', + 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w'); +g_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ch', 'dh', 'bh'); +g_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil', + 'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b', + 'ah', 'ch', 'dh', 'bh'); +## @} + +## @name EFLAGS/RFLAGS/EFLAGS +## @{ +X86_EFL_CF = RT_BIT_32(0); +X86_EFL_CF_BIT = 0; +X86_EFL_1 = RT_BIT_32(1); +X86_EFL_PF = RT_BIT_32(2); +X86_EFL_AF = RT_BIT_32(4); +X86_EFL_AF_BIT = 4; +X86_EFL_ZF = RT_BIT_32(6); +X86_EFL_ZF_BIT = 6; +X86_EFL_SF = RT_BIT_32(7); +X86_EFL_SF_BIT = 7; +X86_EFL_TF = RT_BIT_32(8); +X86_EFL_IF = RT_BIT_32(9); +X86_EFL_DF = RT_BIT_32(10); +X86_EFL_OF = RT_BIT_32(11); +X86_EFL_OF_BIT = 11; +X86_EFL_IOPL = (RT_BIT_32(12) | RT_BIT_32(13)); +X86_EFL_NT = RT_BIT_32(14); +X86_EFL_RF = RT_BIT_32(16); +X86_EFL_VM = RT_BIT_32(17); +X86_EFL_AC = RT_BIT_32(18); +X86_EFL_VIF = RT_BIT_32(19); +X86_EFL_VIP = RT_BIT_32(20); +X86_EFL_ID = RT_BIT_32(21); +X86_EFL_LIVE_MASK = 0x003f7fd5; +X86_EFL_RA1_MASK = RT_BIT_32(1); +X86_EFL_IOPL_SHIFT = 12; +X86_EFL_STATUS_BITS = ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF ); +## @} + +## @name Random +## @{ +g_iMyRandSeed = int((os.urandom(4)).encode('hex'), 16); +#g_iMyRandSeed = 286523426; +#g_iMyRandSeed = 1994382324; +g_oMyRand = random.Random(g_iMyRandSeed); +#g_oMyRand = random.SystemRandom(); + +def randU8(): + """ Unsigned 8-bit random number. """ + return g_oMyRand.getrandbits(8); + +def randU16(): + """ Unsigned 16-bit random number. """ + return g_oMyRand.getrandbits(16); + +def randU32(): + """ Unsigned 32-bit random number. """ + return g_oMyRand.getrandbits(32); + +def randU64(): + """ Unsigned 64-bit random number. """ + return g_oMyRand.getrandbits(64); + +def randUxx(cBits): + """ Unsigned 8-, 16-, 32-, or 64-bit random number. """ + return g_oMyRand.getrandbits(cBits); + +def randSxx(cBits): + """ Signed 8-, 16-, 32-, or 64-bit random number. """ + uVal = randUxx(cBits); + iRet = uVal & ((1 << (cBits - 1)) - 1); + if iRet != uVal: + iRet = -iRet; + return iRet; + +def randUxxList(cBits, cElements): + """ List of unsigned 8-, 16-, 32-, or 64-bit random numbers. """ + return [randUxx(cBits) for _ in range(cElements)]; +## @} + + + + +## @name Instruction Emitter Helpers +## @{ + +def calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0): + """ + Calculates a rex prefix if neccessary given the two registers + and optional rex size prefixes. + Returns an empty array if not necessary. + """ + bRex = bOtherRexPrefixes; + if iReg >= 8: + bRex |= X86_OP_REX_R; + if iRm >= 8: + bRex |= X86_OP_REX_B; + if bRex == 0: + return []; + return [bRex,]; + +def calcModRmForTwoRegs(iReg, iRm): + """ + Calculate the RM byte for two registers. + Returns an array with one byte in it. + """ + bRm = (0x3 << X86_MODRM_MOD_SHIFT) \ + | ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \ + | (iRm & X86_MODRM_RM_MASK); + return [bRm,]; + +## @} + + +## @name Misc +## @{ + +def convU32ToSigned(u32): + """ Converts a 32-bit unsigned value to 32-bit signed. """ + if u32 < 0x80000000: + return u32; + return u32 - UINT32_MAX - 1; + +def rotateLeftUxx(cBits, uVal, cShift): + """ Rotate a xx-bit wide unsigned number to the left. """ + assert cShift < cBits; + + if cBits == 16: + uMask = UINT16_MAX; + elif cBits == 32: + uMask = UINT32_MAX; + elif cBits == 64: + uMask = UINT64_MAX; + else: + assert cBits == 8; + uMask = UINT8_MAX; + + uVal &= uMask; + uRet = (uVal << cShift) & uMask; + uRet |= (uVal >> (cBits - cShift)); + return uRet; + +def rotateRightUxx(cBits, uVal, cShift): + """ Rotate a xx-bit wide unsigned number to the right. """ + assert cShift < cBits; + + if cBits == 16: + uMask = UINT16_MAX; + elif cBits == 32: + uMask = UINT32_MAX; + elif cBits == 64: + uMask = UINT64_MAX; + else: + assert cBits == 8; + uMask = UINT8_MAX; + + uVal &= uMask; + uRet = (uVal >> cShift); + uRet |= (uVal << (cBits - cShift)) & uMask; + return uRet; + +def gregName(iReg, cBits, fRexByteRegs = True): + """ Gets the name of a general register by index and width. """ + if cBits == 64: + return g_asGRegs64[iReg]; + if cBits == 32: + return g_asGRegs32[iReg]; + if cBits == 16: + return g_asGRegs16[iReg]; + assert cBits == 8; + if fRexByteRegs: + return g_asGRegs8Rex[iReg]; + return g_asGRegs8[iReg]; + +## @} + + +class TargetEnv(object): + """ + Target Runtime Environment. + """ + + ## @name CPU Modes + ## @{ + ksCpuMode_Real = 'real'; + ksCpuMode_Protect = 'prot'; + ksCpuMode_Paged = 'paged'; + ksCpuMode_Long = 'long'; + ksCpuMode_V86 = 'v86'; + ## @} + + ## @name Instruction set. + ## @{ + ksInstrSet_16 = '16'; + ksInstrSet_32 = '32'; + ksInstrSet_64 = '64'; + ## @} + + def __init__(self, sName, + sInstrSet = ksInstrSet_32, + sCpuMode = ksCpuMode_Paged, + iRing = 3, + ): + self.sName = sName; + self.sInstrSet = sInstrSet; + self.sCpuMode = sCpuMode; + self.iRing = iRing; + self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32; + self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp; + + def isUsingIprt(self): + """ Whether it's an IPRT environment or not. """ + return self.sName.startswith('iprt'); + + def is64Bit(self): + """ Whether it's a 64-bit environment or not. """ + return self.sInstrSet == self.ksInstrSet_64; + + def getDefOpBits(self): + """ Get the default operand size as a bit count. """ + if self.sInstrSet == self.ksInstrSet_16: + return 16; + return 32; + + def getDefOpBytes(self): + """ Get the default operand size as a byte count. """ + return self.getDefOpBits() / 8; + + def getMaxOpBits(self): + """ Get the max operand size as a bit count. """ + if self.sInstrSet == self.ksInstrSet_64: + return 64; + return 32; + + def getMaxOpBytes(self): + """ Get the max operand size as a byte count. """ + return self.getMaxOpBits() / 8; + + def getDefAddrBits(self): + """ Get the default address size as a bit count. """ + if self.sInstrSet == self.ksInstrSet_16: + return 16; + if self.sInstrSet == self.ksInstrSet_32: + return 32; + return 64; + + def getDefAddrBytes(self): + """ Get the default address size as a byte count. """ + return self.getDefAddrBits() / 8; + + def getGRegCount(self, cbEffBytes = 4): + """ Get the number of general registers. """ + if self.sInstrSet == self.ksInstrSet_64: + if cbEffBytes == 1: + return 16 + 4; + return 16; + return 8; + + def randGRegNoSp(self, cbEffBytes = 4): + """ Returns a random general register number, excluding the SP register. """ + iReg = randU16() % self.getGRegCount(cbEffBytes); + while iReg == X86_GREG_xSP: + iReg = randU16() % self.getGRegCount(cbEffBytes); + return iReg; + + def randGRegNoSpList(self, cItems, cbEffBytes = 4): + """ List of randGRegNoSp values. """ + aiRegs = []; + for _ in range(cItems): + aiRegs.append(self.randGRegNoSp(cbEffBytes)); + return aiRegs; + + def getAddrModes(self): + """ Gets a list of addressing mode (16, 32, or/and 64). """ + if self.sInstrSet == self.ksInstrSet_16: + return [16, 32]; + if self.sInstrSet == self.ksInstrSet_32: + return [32, 16]; + return [64, 32]; + + def is8BitHighGReg(self, cbEffOp, iGReg): + """ Checks if the given register is a high 8-bit general register (AH, CH, DH or BH). """ + assert cbEffOp in [1, 2, 4, 8]; + if cbEffOp == 1: + if iGReg >= 16: + return True; + if iGReg >= 4 and not self.is64Bit(): + return True; + return False; + + def gregNameBits(self, iReg, cBits): + """ Gets the name of the given register for the specified width (bits). """ + return gregName(iReg, cBits, self.is64Bit()); + + def gregNameBytes(self, iReg, cbWidth): + """ Gets the name of the given register for the specified with (in bytes). """ + return gregName(iReg, cbWidth * 8, self.is64Bit()); + + + + +## Target environments. +g_dTargetEnvs = { + 'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3), + 'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3), + 'bs2-r0-64': TargetEnv('bs2-r0-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 0), + 'bs2-r0-64-big': TargetEnv('bs2-r0-64-big', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 0), + 'bs2-r0-32-big': TargetEnv('bs2-r0-32-big', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 0), +}; + + +class InstrTestBase(object): + """ + Base class for testing one instruction. + """ + + def __init__(self, sName, sInstr = None): + self.sName = sName; + self.sInstr = sInstr if sInstr else sName.split()[0]; + + def isApplicable(self, oGen): + """ + Tests if the instruction test is applicable to the selected environment. + """ + _ = oGen; + return True; + + def generateTest(self, oGen, sTestFnName): + """ + Emits the test assembly code. + """ + oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName)); + return True; + + def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False): + """ Generate a list of inputs. """ + if fLong: + # + # Try do extremes as well as different ranges of random numbers. + # + auRet = [0, 1, ]; + if cbMaxOp >= 1: + auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ]; + if cbMaxOp >= 2: + auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ]; + if cbMaxOp >= 4: + auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ]; + if cbMaxOp >= 8: + auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ]; + + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, cValues); + cWanted = 16; + elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium: + for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, cValues); + cWanted = 64; + else: + for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, cValues); + cWanted = 168; + if len(auRet) < cWanted: + auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet)); + else: + # + # Short list, just do some random numbers. + # + auRet = []; + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + auRet += randUxxList(cbMaxOp, 1); + elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium: + auRet += randUxxList(cbMaxOp, 2); + else: + auRet = []; + for cBits in (8, 16, 32, 64): + if cBits < cbMaxOp * 8: + auRet += randUxxList(cBits, 1); + return auRet; + + +class InstrTest_MemOrGreg_2_Greg(InstrTestBase): + """ + Instruction reading memory or general register and writing the result to a + general register. + """ + + def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None): + InstrTestBase.__init__(self, sName, sInstr); + self.fnCalcResult = fnCalcResult; + self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars); + self.fTestRegForm = True; + self.fTestMemForm = True; + + ## @name Test Instruction Writers + ## @{ + + def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen): + """ Writes the instruction with two general registers as operands. """ + oGen.write(' %s %s, %s\n' + % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),)); + return True; + + def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen): + """ Writes the instruction with two general registers as operands. """ + oGen.write(' '); + if iOp2 == 13 and iMod == 0 and cAddrBits == 64: + oGen.write('altrexb '); # Alternative encoding for rip relative addressing. + oGen.write('%s %s, [' % (self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp),)); + if (iOp2 == 5 or iOp2 == 13) and iMod == 0: + oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,)) + if oGen.oTarget.is64Bit(): + oGen.write(' wrt rip'); + else: + if iMod == 1: + oGen.write('byte %d + ' % (offDisp,)); + elif iMod == 2: + oGen.write('dword %d + ' % (offDisp,)); + else: + assert iMod == 0; + + if cAddrBits == 64: + oGen.write(g_asGRegs64[iOp2]); + elif cAddrBits == 32: + oGen.write(g_asGRegs32[iOp2]); + elif cAddrBits == 16: + assert False; ## @todo implement 16-bit addressing. + else: + assert False, str(cAddrBits); + + oGen.write(']\n'); + return True; + + def writeInstrGregSibLabel(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes the instruction taking a register and a label (base only w/o reg), SIB form. """ + assert offDisp is None; assert iBaseReg in [5, 13]; assert iIndexReg == 4; assert cAddrBits != 16; + if cAddrBits == 64: + # Note! Cannot test this in 64-bit mode in any sensible way because the disp is 32-bit + # and we cannot (yet) make assumtions about where we're loaded. + ## @todo Enable testing this in environments where we can make assumptions (boot sector). + oGen.write(' %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP]\n' + % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), cbEffOp * 8,)); + else: + oGen.write(' altsibx%u %s %s, [VBINSTST_NAME(g_u%sData) xWrtRIP] ; iOp1=%s cbEffOp=%s\n' + % ( iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), cbEffOp * 8, iOp1, cbEffOp)); + return True; + + def writeInstrGregSibScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes the instruction taking a register and disp+scaled register (no base reg), SIB form. """ + assert iBaseReg in [5, 13]; assert iIndexReg != 4; assert cAddrBits != 16; + # Note! Using altsibxN to force scaled encoding. This is only really a + # necessity for iScale=1, but doesn't hurt for the rest. + oGen.write(' altsibx%u %s %s, [%s * %#x' + % (iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBits(iIndexReg, cAddrBits), iScale,)); + if offDisp is not None: + oGen.write(' + %#x' % (offDisp,)); + oGen.write(']\n'); + _ = iBaseReg; + return True; + + def writeInstrGregSibBase(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes the instruction taking a register and base only (with reg), SIB form. """ + oGen.write(' altsibx%u %s %s, [%s' + % (iScale, self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBits(iBaseReg, cAddrBits),)); + if offDisp is not None: + oGen.write(' + %#x' % (offDisp,)); + oGen.write(']\n'); + _ = iIndexReg; + return True; + + def writeInstrGregSibBaseAndScaledReg(self, cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen): + """ Writes tinstruction taking a register and full featured SIB form address. """ + # Note! From the looks of things, yasm will encode the following instructions the same way: + # mov eax, [rsi*1 + rbx] + # mov eax, [rbx + rsi*1] + # So, when there are two registers involved, the '*1' selects + # which is index and which is base. + oGen.write(' %s %s, [%s + %s * %u' + % ( self.sInstr, oGen.gregNameBytes(iOp1, cbEffOp), + oGen.gregNameBits(iBaseReg, cAddrBits), oGen.gregNameBits(iIndexReg, cAddrBits), iScale,)); + if offDisp is not None: + oGen.write(' + %#x' % (offDisp,)); + oGen.write(']\n'); + return True; + + ## @} + + + ## @name Memory setups + ## @{ + + def generateMemSetupReadByLabel(self, oGen, cbEffOp, uInput): + """ Sets up memory for a memory read. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,)); + return True; + + def generateMemSetupReadByReg(self, oGen, cAddrBits, cbEffOp, iReg1, uInput, offDisp = None): + """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iReg1, offDisp = offDisp),)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iReg1],)); + return True; + + def generateMemSetupReadByScaledReg(self, oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp = None): + """ Sets up memory for a memory read indirectly addressed thru one register and optional displacement. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, offDisp = offDisp, iIndexReg = iIndexReg, iScale = iScale),)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],)); + return True; + + def generateMemSetupReadByBaseAndScaledReg(self, oGen, cAddrBits, cbEffOp, iBaseReg, iIndexReg, iScale, uInput, offDisp): + """ Sets up memory for a memory read indirectly addressed thru two registers with optional displacement. """ + oGen.pushConst(uInput); + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iBaseReg = iBaseReg, offDisp = offDisp, + iIndexReg = iIndexReg, iScale = iScale),)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iIndexReg],)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iBaseReg],)); + return True; + + def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None): + """ Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """ + oGen.pushConst(uInput); + assert offDisp is None or iMod != 0; + if (iOp2 != 5 and iOp2 != 13) or iMod != 0: + oGen.write(' call VBINSTST_NAME(%s)\n' + % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),)); + else: + oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); + return True; + + ## @} + + def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult): + """ Generate one standard instr greg,greg test. """ + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uInput,)); + if iOp1X != iOp2X: + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],)); + self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1X, iOp2X if iOp1X != iOp2X else None),)); + _ = cbMaxOp; + return True; + + def generateOneStdTestGregGreg8BitHighPain(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput): + """ High 8-bit registers are a real pain! """ + assert oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) or oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2); + # Figure out the register indexes of the max op sized regs involved. + iOp1X = iOp1 & 3; + iOp2X = iOp2 & 3; + oGen.write(' ; iOp1=%u iOp1X=%u iOp2=%u iOp2X=%u\n' % (iOp1, iOp1X, iOp2, iOp2X,)); + + # Calculate unshifted result. + if iOp1X != iOp2X: + uCur = oGen.auRegValues[iOp1X]; + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1): + uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8); + else: + uCur = uInput; + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) != oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2): + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1): + uCur = rotateRightUxx(cbMaxOp * 8, uCur, 8); + else: + uCur = rotateLeftUxx(cbMaxOp * 8, uCur, 8); + uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen); + + + # Rotate the input and/or result to match their max-op-sized registers. + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2): + uInput = rotateLeftUxx(cbMaxOp * 8, uInput, 8); + if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1): + uResult = rotateLeftUxx(cbMaxOp * 8, uResult, 8); + + # Hand it over to an overridable worker method. + return self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1X, iOp2, iOp2X, uInput, uResult); + + + def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult): + """ Generate mode 0, 1 and 2 test for the R/M=iOp2. """ + if cAddrBits == 16: + _ = cbMaxOp; + else: + iMod = 0; # No disp, except for i=5. + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput); + self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),)); + + if iOp2 != 5 and iOp2 != 13: + iMod = 1; + for offDisp in oGen.getDispForMod(iMod): + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp); + self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),)); + + iMod = 2; + for offDisp in oGen.getDispForMod(iMod): + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp); + self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),)); + + return True; + + def generateOneStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, # pylint: disable=R0913 + iBaseReg, iIndexReg, iScale, uInput, uResult): + """ Generate one SIB variations. """ + for offDisp in oGen.getDispForMod(iMod, cbEffOp): + if ((iBaseReg == 5 or iBaseReg == 13) and iMod == 0): + if iIndexReg == 4: + if cAddrBits == 64: + continue; # skipping. + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupReadByLabel(oGen, cbEffOp, uInput); + self.writeInstrGregSibLabel(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1); + else: + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + self.generateMemSetupReadByScaledReg(oGen, cAddrBits, cbEffOp, iIndexReg, iScale, uInput, offDisp); + self.writeInstrGregSibScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1, iIndexReg); + else: + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + if iIndexReg == 4: + self.generateMemSetupReadByReg(oGen, cAddrBits, cbEffOp, iBaseReg, uInput, offDisp); + self.writeInstrGregSibBase(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1, iBaseReg); + else: + if iIndexReg == iBaseReg and iScale == 1 and offDisp is not None and (offDisp & 1): + if offDisp < 0: offDisp += 1; + else: offDisp -= 1; + self.generateMemSetupReadByBaseAndScaledReg(oGen, cAddrBits, cbEffOp, iBaseReg, + iIndexReg, iScale, uInput, offDisp); + self.writeInstrGregSibBaseAndScaledReg(cbEffOp, iOp1, cAddrBits, iBaseReg, iIndexReg, iScale, offDisp, oGen); + sChecker = oGen.needGRegChecker(iOp1, iBaseReg, iIndexReg); + oGen.pushConst(uResult); + oGen.write(' call VBINSTST_NAME(%s)\n' % (sChecker,)); + _ = cbMaxOp; + return True; + + def generateStdTestGregMemSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, auInputs): + """ Generate all SIB variations for the given iOp1 (reg) value. """ + assert cAddrBits in [32, 64]; + i = oGen.cSibBasePerRun; + while i > 0: + oGen.iSibBaseReg = (oGen.iSibBaseReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8); + if oGen.iSibBaseReg == X86_GREG_xSP: # no RSP testing atm. + continue; + + j = oGen.getSibIndexPerRun(); + while j > 0: + oGen.iSibIndexReg = (oGen.iSibIndexReg + 1) % oGen.oTarget.getGRegCount(cAddrBits / 8); + if oGen.iSibIndexReg == iOp1 and oGen.iSibIndexReg != 4 and cAddrBits != cbMaxOp: + continue; # Don't know the high bit of the address ending up the result - skip it for now. + + for iMod in [0, 1, 2]: + if oGen.iSibBaseReg == iOp1 \ + and ((oGen.iSibBaseReg != 5 and oGen.iSibBaseReg != 13) or iMod != 0) \ + and cAddrBits != cbMaxOp: + continue; # Don't know the high bit of the address ending up the result - skip it for now. + + for _ in oGen.oSibScaleRange: + oGen.iSibScale *= 2; + if oGen.iSibScale > 8: + oGen.iSibScale = 1; + + for uInput in auInputs: + oGen.newSubTest(); + uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen); + self.generateOneStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iMod, + oGen.iSibBaseReg, oGen.iSibIndexReg, oGen.iSibScale, + uInput, uResult); + j -= 1; + i -= 1; + + return True; + + + def generateStandardTests(self, oGen): + """ Generate standard tests. """ + + # Parameters. + cbDefOp = oGen.oTarget.getDefOpBytes(); + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen); + auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True); + iLongOp1 = oGen.oTarget.randGRegNoSp(); + iLongOp2 = oGen.oTarget.randGRegNoSp(); + + # Register tests + if self.fTestRegForm: + for cbEffOp in self.acbOpVars: + if cbEffOp > cbMaxOp: + continue; + oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp)); + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + oOp2Range = [iLongOp2,]; + oGen.write('; cbEffOp=%u\n' % (cbEffOp,)); + + for iOp1 in range(oGen.oTarget.getGRegCount(cbEffOp)): + if iOp1 == X86_GREG_xSP: + continue; # Cannot test xSP atm. + for iOp2 in oOp2Range: + if (iOp2 >= 16 and iOp1 in range(4, 16)) \ + or (iOp1 >= 16 and iOp2 in range(4, 16)): + continue; # Any REX encoding turns AH,CH,DH,BH regs into SPL,BPL,SIL,DIL. + if iOp2 == X86_GREG_xSP: + continue; # Cannot test xSP atm. + + oGen.write('; iOp2=%u cbEffOp=%u\n' % (iOp2, cbEffOp)); + for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs): + oGen.newSubTest(); + if not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp1) and not oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2): + uCur = oGen.auRegValues[iOp1 & 15] if iOp1 != iOp2 else uInput; + uResult = self.fnCalcResult(cbEffOp, uInput, uCur, oGen); + self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp1 & 15, iOp2, iOp2 & 15, + uInput, uResult); + else: + self.generateOneStdTestGregGreg8BitHighPain(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput); + + # Memory test. + if self.fTestMemForm: + for cAddrBits in oGen.oTarget.getAddrModes(): + for cbEffOp in self.acbOpVars: + if cbEffOp > cbMaxOp: + continue; + + for _ in oGen.getModRegRange(cbEffOp): + oGen.iModReg = (oGen.iModReg + 1) % oGen.oTarget.getGRegCount(cbEffOp); + if oGen.iModReg == X86_GREG_xSP: + continue; # Cannot test xSP atm. + if oGen.iModReg > 15: + continue; ## TODO AH,CH,DH,BH + + auInputs = auLongInputs if oGen.iModReg == iLongOp1 else auShortInputs; + for _ in oGen.oModRmRange: + oGen.iModRm = (oGen.iModRm + 1) % oGen.oTarget.getGRegCount(cAddrBits * 8); + if oGen.iModRm != 4 or cAddrBits == 16: + for uInput in auInputs: + oGen.newSubTest(); + if oGen.iModReg == oGen.iModRm and oGen.iModRm != 5 \ + and oGen.iModRm != 13 and cbEffOp != cbMaxOp: + continue; # Don't know the high bit of the address ending up the result - skip it for now. + uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[oGen.iModReg & 15], oGen); + self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp, + oGen.iModReg, oGen.iModRm, uInput, uResult); + else: + # SIB - currently only short list of inputs or things may get seriously out of hand. + self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, oGen.iModReg, auShortInputs); + return True; + + def generateTest(self, oGen, sTestFnName): + oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,)); + + self.generateStandardTests(oGen); + + oGen.write(' ret\n'); + oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,)); + return True; + + + +class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg): + """ + Tests MOV Gv,Ev. + """ + def __init__(self): + InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov); + + @staticmethod + def calc_mov(cbEffOp, uInput, uCur, oGen): + """ Calculates the result of a mov instruction.""" + if cbEffOp == 8: + return uInput & UINT64_MAX; + if cbEffOp == 4: + return uInput & UINT32_MAX; + if cbEffOp == 2: + return (uCur & 0xffffffffffff0000) | (uInput & UINT16_MAX); + assert cbEffOp == 1; _ = oGen; + return (uCur & 0xffffffffffffff00) | (uInput & UINT8_MAX); + + +class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg): + """ + Tests MOVSXD Gv,Ev. + """ + def __init__(self): + InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]); + self.fTestMemForm = False; # drop this... + + def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen): + """ Writes the instruction with two general registers as operands. """ + if cbEffOp == 8: + oGen.write(' movsxd %s, %s\n' + % ( oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp / 2),)); + else: + oGen.write(' oddmovsxd %s, %s\n' + % ( oGen.gregNameBytes(iOp1, cbEffOp), oGen.gregNameBytes(iOp2, cbEffOp),)); + return True; + + def isApplicable(self, oGen): + return oGen.oTarget.is64Bit(); + + @staticmethod + def calc_movsxd(cbEffOp, uInput, uCur, oGen): + """ + Calculates the result of a movxsd instruction. + Returns the result value (cbMaxOp sized). + """ + _ = oGen; + if cbEffOp == 8 and (uInput & RT_BIT_32(31)): + return (UINT32_MAX << 32) | (uInput & UINT32_MAX); + if cbEffOp == 2: + return (uCur & 0xffffffffffff0000) | (uInput & 0xffff); + return uInput & UINT32_MAX; + + +class InstrTest_DivIDiv(InstrTestBase): + """ + Tests IDIV and DIV instructions. + """ + + def __init__(self, fIsIDiv): + if not fIsIDiv: + InstrTestBase.__init__(self, 'div Gv,Ev', 'div'); + else: + InstrTestBase.__init__(self, 'idiv Gv,Ev', 'idiv'); + self.fIsIDiv = fIsIDiv; + + def generateInputEdgeCases(self, cbEffOp, fLong, fXcpt): + """ Generate edge case inputs for cbEffOp. Returns a list of pairs, dividen + divisor. """ + # Test params. + uStep = 1 << (cbEffOp * 8); + if self.fIsIDiv: + uStep /= 2; + + # edge tests + auRet = []; + + uDivisor = 1 if fLong else 3; + uDividend = uStep * uDivisor - 1; + for i in range(5 if fLong else 3): + auRet.append([uDividend + fXcpt, uDivisor]); + if self.fIsIDiv: + auRet.append([-uDividend - fXcpt, -uDivisor]); + auRet.append([-(uDividend + uDivisor + fXcpt), uDivisor]); + auRet.append([ (uDividend + uDivisor + fXcpt), -uDivisor]); + if i <= 3 and fLong: + auRet.append([uDividend - 1 + fXcpt*3, uDivisor]); + if self.fIsIDiv: + auRet.append([-(uDividend - 1 + fXcpt*3), -uDivisor]); + uDivisor += 1; + uDividend += uStep; + + uDivisor = uStep - 1; + uDividend = uStep * uDivisor - 1; + for _ in range(3 if fLong else 1): + auRet.append([uDividend + fXcpt, uDivisor]); + if self.fIsIDiv: + auRet.append([-uDividend - fXcpt, -uDivisor]); + uDivisor -= 1; + uDividend -= uStep; + + if self.fIsIDiv: + uDivisor = -uStep; + for _ in range(3 if fLong else 1): + auRet.append([uDivisor * (-uStep - 1) - (not fXcpt), uDivisor]); + uDivisor += 1 + uDivisor = uStep - 1; + for _ in range(3 if fLong else 1): + auRet.append([-(uDivisor * (uStep + 1) - (not fXcpt)), uDivisor]); + uDivisor -= 1 + + return auRet; + + def generateInputsNoXcpt(self, cbEffOp, fLong = False): + """ Generate inputs for cbEffOp. Returns a list of pairs, dividen + divisor. """ + # Test params. + uStep = 1 << (cbEffOp * 8); + if self.fIsIDiv: + uStep /= 2; + + # edge tests + auRet = self.generateInputEdgeCases(cbEffOp, fLong, False) + + # random tests. + if self.fIsIDiv: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randSxx(cbEffOp * 8); + if uDivisor == 0 or uDivisor >= uStep or uDivisor < -uStep: + continue; + uDividend = randSxx(cbEffOp * 16); + uResult = uDividend / uDivisor; + if uResult >= uStep or uResult <= -uStep: # exclude difficulties + continue; + break; + auRet.append([uDividend, uDivisor]); + else: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randUxx(cbEffOp * 8); + if uDivisor == 0 or uDivisor >= uStep: + continue; + uDividend = randUxx(cbEffOp * 16); + uResult = uDividend / uDivisor; + if uResult >= uStep: + continue; + break; + auRet.append([uDividend, uDivisor]); + + return auRet; + + def generateOneStdTestGreg(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV rDX:rAX,<GREG>' test. """ + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fEffOp = ((1 << (cbEffOp *8) ) - 1); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + fTopOp = fMaxOp - fEffOp; + fFullOp1 = ((1 << (cbEffOp*16)) - 1); + + uAX = iDividend & fFullOp1; # full with unsigned + uDX = uAX >> (cbEffOp*8); + uAX &= fEffOp; + uOp2Val = iDivisor & fEffOp; + + iQuotient = iDividend / iDivisor; + iReminder = iDividend % iDivisor; + if iReminder != 0 and iQuotient < 0: # python has different rounding rules for negative division. + iQuotient += 1; + iReminder -= iDivisor; + uAXResult = iQuotient & fEffOp; + uDXResult = iReminder & fEffOp; + + if cbEffOp < cbMaxOp: + uAX |= randUxx(cbMaxOp * 8) & fTopOp; + uDX |= randUxx(cbMaxOp * 8) & fTopOp; + uOp2Val |= randUxx(cbMaxOp * 8) & fTopOp; + if cbEffOp < 4: + uAXResult |= uAX & fTopOp; + uDXResult |= uDX & fTopOp; + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + ' ; iQuotient=%#x (%d) iReminder=%#x (%d)\n' + % ( iDividend & fFullOp1, iDividend, iDivisor & fEffOp, iDivisor, + iQuotient & fEffOp, iQuotient, iReminder & fEffOp, iReminder, )); + + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX], uDX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uOp2Val,)); + + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); + oGen.pushConst(uDXResult); + oGen.pushConst(uAXResult); + + oGen.write(' %-4s %s\n' % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, X86_GREG_xDX, iOp2),)); + return True; + + def generateOneStdTestGreg8Bit(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV AX,<GREG>' test (8-bit). """ + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + iOp2X = (iOp2 & 3) if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2) else iOp2; + assert iOp2X != X86_GREG_xAX; + + uAX = iDividend & UINT16_MAX; # full with unsigned + uOp2Val = iDivisor & UINT8_MAX; + + iQuotient = iDividend / iDivisor; + iReminder = iDividend % iDivisor; + if iReminder != 0 and iQuotient < 0: # python has different rounding rules for negative division. + iQuotient += 1; + iReminder -= iDivisor; + uAXResult = (iQuotient & UINT8_MAX) | ((iReminder & UINT8_MAX) << 8); + + uAX |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT16_MAX); + uAXResult |= uAX & (fMaxOp - UINT16_MAX); + uOp2Val |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT8_MAX); + if iOp2X != iOp2: + uOp2Val = rotateLeftUxx(cbMaxOp * 8, uOp2Val, 8); + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + ' ; iQuotient=%#x (%d) iReminder=%#x (%d)\n' + % ( iDividend & UINT16_MAX, iDividend, iDivisor & UINT8_MAX, iDivisor, + iQuotient & UINT8_MAX, iQuotient, iReminder & UINT8_MAX, iReminder, )); + + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uOp2Val,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],)); + oGen.pushConst(uAXResult); + + oGen.write(' %-4s %s\n' % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, iOp2X),)); + return; + + + def generateStandardTests(self, oGen): + """ Generates test that causes no exceptions. """ + + # Parameters. + iLongOp2 = oGen.oTarget.randGRegNoSp(); + + # Register tests + if True: + for cbEffOp in ( 8, 4, 2, 1 ): + if cbEffOp > oGen.oTarget.getMaxOpBytes(): + continue; + oGen.write('; cbEffOp=%u\n' % (cbEffOp,)); + oOp2Range = range(oGen.oTarget.getGRegCount(cbEffOp)); + if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + oOp2Range = [iLongOp2,]; + for iOp2 in oOp2Range: + if iOp2 == X86_GREG_xSP: + continue; # Cannot test xSP atm. + if iOp2 == X86_GREG_xAX or (cbEffOp > 1 and iOp2 == X86_GREG_xDX): + continue; # Will overflow or be too complicated to get right. + if cbEffOp == 1 and iOp2 == (16 if oGen.oTarget.is64Bit() else 4): + continue; # Avoid dividing by AH, same reasons as above. + + for iDividend, iDivisor in self.generateInputsNoXcpt(cbEffOp, iOp2 == iLongOp2): + oGen.newSubTest(); + if cbEffOp > 1: + self.generateOneStdTestGreg(oGen, cbEffOp, iOp2, iDividend, iDivisor); + else: + self.generateOneStdTestGreg8Bit(oGen, cbEffOp, iOp2, iDividend, iDivisor); + + ## Memory test. + #if False: + # for cAddrBits in oGen.oTarget.getAddrModes(): + # for cbEffOp in self.acbOpVars: + # if cbEffOp > cbMaxOp: + # continue; + # + # auInputs = auLongInputs if oGen.iModReg == iLongOp1 else auShortInputs; + # for _ in oGen.oModRmRange: + # oGen.iModRm = (oGen.iModRm + 1) % oGen.oTarget.getGRegCount(cAddrBits * 8); + # if oGen.iModRm != 4 or cAddrBits == 16: + # for uInput in auInputs: + # oGen.newSubTest(); + # if oGen.iModReg == oGen.iModRm and oGen.iModRm != 5 and oGen.iModRm != 13 and cbEffOp != cbMaxOp: + # continue; # Don't know the high bit of the address ending up the result - skip it for now. + # uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[oGen.iModReg & 15], oGen); + # self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp, + # oGen.iModReg, oGen.iModRm, uInput, uResult); + # else: + # # SIB - currently only short list of inputs or things may get seriously out of hand. + # self.generateStdTestGregMemSib(oGen, cAddrBits, cbEffOp, cbMaxOp, oGen.iModReg, auShortInputs); + # + return True; + + def generateInputsXcpt(self, cbEffOp, fLong = False): + """ + Generate inputs for cbEffOp that will overflow or underflow. + Returns a list of pairs, dividen + divisor. + """ + # Test params. + uStep = 1 << (cbEffOp * 8); + if self.fIsIDiv: + uStep /= 2; + + # edge tests + auRet = self.generateInputEdgeCases(cbEffOp, fLong, True); + auRet.extend([[0, 0], [1, 0], [ uStep * uStep / 2 - 1, 0]]); + + # random tests. + if self.fIsIDiv: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randSxx(cbEffOp * 8); + uDividend = randSxx(cbEffOp * 16); + if uDivisor >= uStep or uDivisor < -uStep: + continue; + if uDivisor != 0: + uResult = uDividend / uDivisor; + if (uResult <= uStep and uResult >= 0) or (uResult >= -uStep and uResult < 0): + continue; # exclude difficulties + break; + auRet.append([uDividend, uDivisor]); + else: + for _ in range(6 if fLong else 2): + while True: + uDivisor = randUxx(cbEffOp * 8); + uDividend = randUxx(cbEffOp * 16); + if uDivisor >= uStep: + continue; + if uDivisor != 0: + uResult = uDividend / uDivisor; + if uResult < uStep: + continue; + break; + auRet.append([uDividend, uDivisor]); + + return auRet; + + def generateOneDivideErrorTestGreg(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV rDX:rAX,<GREG>' test that causes #DE. """ + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fEffOp = ((1 << (cbEffOp *8) ) - 1); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + fTopOp = fMaxOp - fEffOp; + fFullOp1 = ((1 << (cbEffOp*16)) - 1); + + uAX = iDividend & fFullOp1; # full with unsigned + uDX = uAX >> (cbEffOp*8); + uAX &= fEffOp; + uOp2Val = iDivisor & fEffOp; + + if cbEffOp < cbMaxOp: + uAX |= randUxx(cbMaxOp * 8) & fTopOp; + uDX |= randUxx(cbMaxOp * 8) & fTopOp; + uOp2Val |= randUxx(cbMaxOp * 8) & fTopOp; + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + % ( iDividend & fFullOp1, iDividend, iDivisor & fEffOp, iDivisor,)); + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX], uDX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uOp2Val,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[X86_GREG_xDX],)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX],)); + oGen.write(' VBINSTST_TRAP_INSTR X86_XCPT_DE, 0, %-4s %s\n' + % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, X86_GREG_xDX, iOp2),)); + return True; + + def generateOneDivideErrorTestGreg8Bit(self, oGen, cbEffOp, iOp2, iDividend, iDivisor): + """ Generate code of one '[I]DIV AX,<GREG>' test that causes #DE (8-bit). """ + if not oGen.oTarget.is64Bit() and iOp2 == 4: # Avoid AH. + iOp2 = 5; + + cbMaxOp = oGen.oTarget.getMaxOpBytes(); + fMaxOp = UINT64_MAX if cbMaxOp == 8 else UINT32_MAX; assert cbMaxOp in [8, 4]; + iOp2X = (iOp2 & 3) if oGen.oTarget.is8BitHighGReg(cbEffOp, iOp2) else iOp2; + assert iOp2X != X86_GREG_xAX; + + uAX = iDividend & UINT16_MAX; # full with unsigned + uOp2Val = iDivisor & UINT8_MAX; + + uAX |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT16_MAX); + uOp2Val |= randUxx(cbMaxOp * 8) & (fMaxOp - UINT8_MAX); + if iOp2X != iOp2: + uOp2Val = rotateLeftUxx(cbMaxOp * 8, uOp2Val, 8); + oGen.write(' ; iDividend=%#x (%d) iDivisor=%#x (%d)\n' + % ( iDividend & UINT16_MAX, iDividend, iDivisor & UINT8_MAX, iDivisor,)); + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[X86_GREG_xAX], uAX,)); + oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2X], uOp2Val,)); + oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2X],)); + oGen.write(' push sAX\n'); + oGen.write(' VBINSTST_TRAP_INSTR X86_XCPT_DE, 0, %-4s %s\n' + % (self.sInstr, oGen.gregNameBytes(iOp2, cbEffOp),)); + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(X86_GREG_xAX, iOp2X),)); + return; + + def generateDivideErrorTests(self, oGen): + """ Generate divide error tests (raises X86_XCPT_DE). """ + oGen.write('%ifdef VBINSTST_CAN_DO_TRAPS\n'); + + # We do one register variation here, assuming the standard test has got them covered. + # Register tests + if True: + iOp2 = oGen.oTarget.randGRegNoSp(); + while iOp2 == X86_GREG_xAX or iOp2 == X86_GREG_xDX: + iOp2 = oGen.oTarget.randGRegNoSp(); + + for cbEffOp in ( 8, 4, 2, 1 ): + if cbEffOp > oGen.oTarget.getMaxOpBytes(): + continue; + oGen.write('; cbEffOp=%u iOp2=%u\n' % (cbEffOp, iOp2,)); + + for iDividend, iDivisor in self.generateInputsXcpt(cbEffOp, fLong = not oGen.isTiny()): + oGen.newSubTest(); + if cbEffOp > 1: + self.generateOneDivideErrorTestGreg(oGen, cbEffOp, iOp2, iDividend, iDivisor); + else: + self.generateOneDivideErrorTestGreg8Bit(oGen, cbEffOp, iOp2, iDividend, iDivisor); + + oGen.write('%endif ; VBINSTST_CAN_DO_TRAPS\n'); + return True; + + + def generateTest(self, oGen, sTestFnName): + oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,)); + #oGen.write(' int3\n'); + + self.generateStandardTests(oGen); + self.generateDivideErrorTests(oGen); + + #oGen.write(' int3\n'); + oGen.write(' ret\n'); + oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,)); + return True; + + + +class InstrTest_DaaDas(InstrTestBase): + """ Tests the DAA and DAS instructions. """ + + def __init__(self, fIsDas): + InstrTestBase.__init__(self, 'das' if fIsDas else 'daa'); + self.fIsDas = fIsDas; + + def isApplicable(self, oGen): + return not oGen.oTarget.is64Bit(); + + def generateTest(self, oGen, sTestFnName): + if self.fIsDas: from itgTableDas import g_aItgDasResults as aItgResults; + else: from itgTableDaa import g_aItgDaaResults as aItgResults; + cMax = len(aItgResults); + if oGen.isTiny(): + cMax = 64; + + oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,)); + oGen.write(' xor ebx, ebx\n'); + oGen.write('.das_loop:\n'); + # Save the loop variable so we can load known values. + oGen.write(' push ebx\n'); + oGen.newSubTestEx('ebx'); + + # Push the results. + oGen.write(' movzx eax, byte [.abAlResults + ebx]\n'); + oGen.write(' or eax, %#x\n' % (oGen.au32Regs[X86_GREG_xAX] & ~0xff,)); + oGen.write(' push eax\n'); + oGen.write(' movzx eax, byte [.aFlagsResults + ebx]\n'); + oGen.write(' push eax\n'); + # Calc and push the inputs. + oGen.write(' mov eax, ebx\n'); + oGen.write(' shr eax, 2\n'); + oGen.write(' and eax, 0ffh\n'); + oGen.write(' or eax, %#x\n' % (oGen.au32Regs[X86_GREG_xAX] & ~0xff,)); + oGen.write(' push eax\n'); + + oGen.write(' pushfd\n') + oGen.write(' and dword [xSP], ~(X86_EFL_CF | X86_EFL_AF)\n'); + oGen.write(' mov al, bl\n'); + oGen.write(' and al, 2\n'); + oGen.write(' shl al, X86_EFL_AF_BIT - 1\n'); + oGen.write(' or [xSP], al\n'); + oGen.write(' mov al, bl\n'); + oGen.write(' and al, X86_EFL_CF\n'); + oGen.write(' or [xSP], al\n'); + + # Load register values and do the test. + oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n'); + oGen.write(' popfd\n'); + oGen.write(' pop eax\n'); + if self.fIsDas: + oGen.write(' das\n'); + else: + oGen.write(' daa\n'); + + # Verify the results. + fFlagsToCheck = X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_ZF; + oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needFlagsGRegChecker(fFlagsToCheck, X86_GREG_xAX),)); + + # Restore the loop variable and advance. + oGen.write(' pop ebx\n'); + oGen.write(' inc ebx\n'); + oGen.write(' cmp ebx, %#x\n' % (cMax,)); + oGen.write(' jb .das_loop\n'); + + oGen.write(' ret\n'); + + oGen.write('.abAlResults:\n'); + for i in range(cMax): + oGen.write(' db %#x\n' % (aItgResults[i][0],)); + + oGen.write('.aFlagsResults:\n'); + for i in range(cMax): + oGen.write(' db %#x\n' % (aItgResults[i][1],)); + + oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,)); + return True; + + +## +# Instruction Tests. +# +g_aoInstructionTests = [ + InstrTest_Mov_Gv_Ev(), + InstrTest_MovSxD_Gv_Ev(), + InstrTest_DivIDiv(fIsIDiv = False), + InstrTest_DivIDiv(fIsIDiv = True), + InstrTest_DaaDas(fIsDas = False), + InstrTest_DaaDas(fIsDas = True), +]; + + + + + +class InstructionTestGen(object): # pylint: disable=R0902 + """ + Instruction Test Generator. + """ + + ## @name Test size + ## @{ + ksTestSize_Large = 'large'; + ksTestSize_Medium = 'medium'; + ksTestSize_Tiny = 'tiny'; + ## @} + kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny ); + + ## The prefix for the checker functions. + ksCheckerPrefix = 'Common_Check_' + + + def __init__(self, oOptions): + self.oOptions = oOptions; + self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv]; + + # Calculate the number of output files. + self.cFiles = 1; + if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile: + self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile; + if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests): + self.cFiles += 1; + + # Fix the known register values. + self.au64Regs = randUxxList(64, 16); + self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)]; + self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)]; + self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs; + + # Declare state variables used while generating. + self.oFile = sys.stderr; + self.iFile = -1; + self.sFile = ''; + self._dCheckFns = dict(); + self._dMemSetupFns = dict(); + self._d64BitConsts = dict(); + + # State variables used while generating test convenientely placed here (lazy bird)... + self.iModReg = 0; + self.iModRm = 0; + self.iSibBaseReg = 0; + self.iSibIndexReg = 0; + self.iSibScale = 1; + if self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny: + self._oModRegRange = range(2); + self._oModRegRange8 = range(2); + self.oModRmRange = range(2); + self.cSibBasePerRun = 1; + self._cSibIndexPerRun = 2; + self.oSibScaleRange = range(1); + elif self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium: + self._oModRegRange = range( 5 if self.oTarget.is64Bit() else 4); + self._oModRegRange8 = range( 6 if self.oTarget.is64Bit() else 4); + self.oModRmRange = range(5); + self.cSibBasePerRun = 5; + self._cSibIndexPerRun = 4 + self.oSibScaleRange = range(2); + else: + self._oModRegRange = range(16 if self.oTarget.is64Bit() else 8); + self._oModRegRange8 = range(20 if self.oTarget.is64Bit() else 8); + self.oModRmRange = range(16 if self.oTarget.is64Bit() else 8); + self.cSibBasePerRun = 8; + self._cSibIndexPerRun = 9; + self.oSibScaleRange = range(4); + self.iSibIndexRange = 0; + + + # + # Methods used by instruction tests. + # + + def write(self, sText): + """ Writes to the current output file. """ + return self.oFile.write(unicode(sText)); + + def writeln(self, sText): + """ Writes a line to the current output file. """ + self.write(sText); + return self.write('\n'); + + def writeInstrBytes(self, abInstr): + """ + Emits an instruction given as a sequence of bytes values. + """ + self.write(' db %#04x' % (abInstr[0],)); + for i in range(1, len(abInstr)): + self.write(', %#04x' % (abInstr[i],)); + return self.write('\n'); + + def newSubTest(self): + """ + Indicates that a new subtest has started. + """ + self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n'); + return True; + + def newSubTestEx(self, sIndicator): + """ + Indicates that a new subtest has started. + """ + self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], %s\n' % (sIndicator, )); + return True; + + def needGRegChecker(self, iReg1, iReg2 = None, iReg3 = None): + """ + Records the need for a given register checker function, returning its label. + """ + if iReg2 is not None: + if iReg3 is not None: + sName = '%s_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2], self.oTarget.asGRegs[iReg3],); + else: + sName = '%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2],); + else: + sName = '%s' % (self.oTarget.asGRegs[iReg1],); + assert iReg3 is None; + + if sName in self._dCheckFns: + self._dCheckFns[sName] += 1; + else: + self._dCheckFns[sName] = 1; + + return self.ksCheckerPrefix + sName; + + def needFlagsGRegChecker(self, fFlagsToCheck, iReg1, iReg2 = None, iReg3 = None): + """ + Records the need for a given rFLAGS + register checker function, returning its label. + """ + sWorkerName = self.needGRegChecker(iReg1, iReg2, iReg3); + + sName = 'eflags_%#x_%s' % (fFlagsToCheck, sWorkerName[len(self.ksCheckerPrefix):]); + if sName in self._dCheckFns: + self._dCheckFns[sName] += 1; + else: + self._dCheckFns[sName] = 1; + + return self.ksCheckerPrefix + sName; + + def needGRegMemSetup(self, cAddrBits, cbEffOp, iBaseReg = None, offDisp = None, iIndexReg = None, iScale = 1): + """ + Records the need for a given register checker function, returning its label. + """ + assert cAddrBits in [64, 32, 16]; + assert cbEffOp in [8, 4, 2, 1]; + assert iScale in [1, 2, 4, 8]; + + sName = '%ubit_U%u' % (cAddrBits, cbEffOp * 8,); + if iBaseReg is not None: + sName += '_%s' % (gregName(iBaseReg, cAddrBits),); + sName += '_x%u' % (iScale,); + if iIndexReg is not None: + sName += '_%s' % (gregName(iIndexReg, cAddrBits),); + if offDisp is not None: + sName += '_%#010x' % (offDisp & UINT32_MAX, ); + if sName in self._dMemSetupFns: + self._dMemSetupFns[sName] += 1; + else: + self._dMemSetupFns[sName] = 1; + return 'Common_MemSetup_' + sName; + + def need64BitConstant(self, uVal): + """ + Records the need for a 64-bit constant, returning its label. + These constants are pooled to attempt reduce the size of the whole thing. + """ + assert uVal >= 0 and uVal <= UINT64_MAX; + if uVal in self._d64BitConsts: + self._d64BitConsts[uVal] += 1; + else: + self._d64BitConsts[uVal] = 1; + return 'g_u64Const_0x%016x' % (uVal, ); + + def pushConst(self, uResult): + """ + Emits a push constant value, taking care of high values on 64-bit hosts. + """ + if self.oTarget.is64Bit() and uResult >= 0x80000000: + self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),)); + else: + self.write(' push dword 0x%x\n' % (uResult,)); + return True; + + def getDispForMod(self, iMod, cbAlignment = 1): + """ + Get a set of address dispositions for a given addressing mode. + The alignment restriction is for SIB scaling. + """ + assert cbAlignment in [1, 2, 4, 8]; + if iMod == 0: + aoffDisp = [ None, ]; + elif iMod == 1: + aoffDisp = [ 127 & ~(cbAlignment - 1), -128 ]; + elif iMod == 2: + aoffDisp = [ 2147483647 & ~(cbAlignment - 1), -2147483648 ]; + else: assert False; + return aoffDisp; + + def getModRegRange(self, cbEffOp): + """ + The Mod R/M register range varies with the effective operand size, for + 8-bit registers we have 4 more. + """ + if cbEffOp == 1: + return self._oModRegRange8; + return self._oModRegRange; + + def getSibIndexPerRun(self): + """ + We vary the SIB index test range a little to try cover more operand + combinations and avoid repeating the same ones. + """ + self.iSibIndexRange += 1; + self.iSibIndexRange %= 3; + if self.iSibIndexRange == 0: + return self._cSibIndexPerRun - 1; + return self._cSibIndexPerRun; + + def isTiny(self): + """ Checks if we're in tiny mode.""" + return self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny; + + def isMedium(self): + """ Checks if we're in medium mode.""" + return self.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium; + + + # + # Forwarding calls for oTarget to shorted typing and lessen the attacks + # on the right margin. + # + + def gregNameBits(self, iReg, cBitsWide): + """ Target: Get the name of a general register for the given size (in bits). """ + return self.oTarget.gregNameBits(iReg, cBitsWide); + + def gregNameBytes(self, iReg, cbWide): + """ Target: Get the name of a general register for the given size (in bytes). """ + return self.oTarget.gregNameBytes(iReg, cbWide); + + def is64Bit(self): + """ Target: Is the target 64-bit? """ + return self.oTarget.is64Bit(); + + + # + # Internal machinery. + # + + def _randInitIndexes(self): + """ + Initializes the Mod R/M and SIB state index with random numbers prior + to generating a test. + + Note! As with all other randomness and variations we do, we cannot + test all combinations for each and every instruction so we try + get coverage over time. + """ + self.iModReg = randU8(); + self.iModRm = randU8(); + self.iSibBaseReg = randU8(); + self.iSibIndexReg = randU8(); + self.iSibScale = 1 << (randU8() & 3); + self.iSibIndexRange = randU8(); + return True; + + def _calcTestFunctionName(self, oInstrTest, iInstrTest): + """ + Calc a test function name for the given instruction test. + """ + sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName); + return sName.replace(',', '_').replace(' ', '_').replace('%', '_'); + + def _generateFileHeader(self, ): + """ + Writes the file header. + Raises exception on trouble. + """ + self.write('; $Id: InstructionTestGen.py $\n' + ';; @file %s\n' + '; Autogenerate by %s %s. DO NOT EDIT\n' + ';\n' + '\n' + ';\n' + '; Headers\n' + ';\n' + '%%include "env-%s.mac"\n' + % ( os.path.basename(self.sFile), + os.path.basename(__file__), __version__[11:-1], + self.oTarget.sName, + ) ); + # Target environment specific init stuff. + + # + # Global variables. + # + self.write('\n\n' + ';\n' + '; Globals\n' + ';\n'); + self.write('VBINSTST_BEGINDATA\n' + 'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n' + ' dq 0\n' + 'VBINSTST_GLOBALNAME_EX g_pvLow32Mem4K, data hidden\n' + ' dq 0\n' + 'VBINSTST_GLOBALNAME_EX g_pvMem4K, data hidden\n' + ' dq 0\n' + 'VBINSTST_GLOBALNAME_EX g_uVBInsTstSubTestIndicator, data hidden\n' + ' dd 0\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + 'VBINSTST_TRAP_RECS_BEGIN\n' + '%endif\n' + 'VBINSTST_BEGINCODE\n' + ); + self.write('%ifdef RT_ARCH_AMD64\n'); + for i in range(len(g_asGRegs64)): + self.write('g_u64KnownValue_%s: dq 0x%x\n' % (g_asGRegs64[i], self.au64Regs[i])); + self.write('%endif\n\n') + + # + # Common functions. + # + + # Loading common values. + self.write('\n\n' + 'VBINSTST_BEGINPROC Common_LoadKnownValues\n' + '%ifdef RT_ARCH_AMD64\n'); + for i in range(len(g_asGRegs64NoSp)): + if g_asGRegs64NoSp[i]: + self.write(' mov %s, 0x%x\n' % (g_asGRegs64NoSp[i], self.au64Regs[i],)); + self.write('%else\n'); + for i in range(8): + if g_asGRegs32NoSp[i]: + self.write(' mov %s, 0x%x\n' % (g_asGRegs32NoSp[i], self.au32Regs[i],)); + self.write('%endif\n' + ' ret\n' + 'VBINSTST_ENDPROC Common_LoadKnownValues\n' + '\n'); + + self.write('VBINSTST_BEGINPROC Common_CheckKnownValues\n' + '%ifdef RT_ARCH_AMD64\n'); + for i in range(len(g_asGRegs64NoSp)): + if g_asGRegs64NoSp[i]: + self.write(' cmp %s, [g_u64KnownValue_%s wrt rip]\n' + ' je .ok_%u\n' + ' push %u ; register number\n' + ' push %s ; actual\n' + ' push qword [g_u64KnownValue_%s wrt rip] ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n' + '.ok_%u:\n' + % ( g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i, i, g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i,)); + self.write('%else\n'); + for i in range(8): + if g_asGRegs32NoSp[i]: + self.write(' cmp %s, 0x%x\n' + ' je .ok_%u\n' + ' push %u ; register number\n' + ' push %s ; actual\n' + ' push dword 0x%x ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n' + '.ok_%u:\n' + % ( g_asGRegs32NoSp[i], self.au32Regs[i], i, i, g_asGRegs32NoSp[i], self.au32Regs[i], i,)); + self.write('%endif\n' + ' ret\n' + 'VBINSTST_ENDPROC Common_CheckKnownValues\n' + '\n'); + + return True; + + def _generateMemSetupFunctions(self): # pylint: disable=R0915 + """ + Generates the memory setup functions. + """ + cDefAddrBits = self.oTarget.getDefAddrBits(); + for sName in self._dMemSetupFns: + # Unpack it. + asParams = sName.split('_'); + cAddrBits = int(asParams[0][:-3]); assert asParams[0][-3:] == 'bit'; + cEffOpBits = int(asParams[1][1:]); assert asParams[1][0] == 'U'; + if cAddrBits == 64: asAddrGRegs = g_asGRegs64; + elif cAddrBits == 32: asAddrGRegs = g_asGRegs32; + else: asAddrGRegs = g_asGRegs16; + + i = 2; + iBaseReg = None; + sBaseReg = None; + if i < len(asParams) and asParams[i] in asAddrGRegs: + sBaseReg = asParams[i]; + iBaseReg = asAddrGRegs.index(sBaseReg); + i += 1 + + assert i < len(asParams); assert asParams[i][0] == 'x'; + iScale = iScale = int(asParams[i][1:]); assert iScale in [1, 2, 4, 8], '%u %s' % (iScale, sName); + i += 1; + + sIndexReg = None; + iIndexReg = None; + if i < len(asParams) and asParams[i] in asAddrGRegs: + sIndexReg = asParams[i]; + iIndexReg = asAddrGRegs.index(sIndexReg); + i += 1; + + u32Disp = None; + if i < len(asParams) and len(asParams[i]) == 10: + u32Disp = long(asParams[i], 16); + i += 1; + + assert i == len(asParams), 'i=%d len=%d len[i]=%d (%s)' % (i, len(asParams), len(asParams[i]), asParams[i],); + assert iScale == 1 or iIndexReg is not None; + + # Find a temporary register. + iTmpReg1 = X86_GREG_xCX; + while iTmpReg1 in [iBaseReg, iIndexReg]: + iTmpReg1 += 1; + + # Prologue. + self.write('\n\n' + '; cAddrBits=%s cEffOpBits=%s iBaseReg=%s u32Disp=%s iIndexReg=%s iScale=%s\n' + 'VBINSTST_BEGINPROC Common_MemSetup_%s\n' + ' MY_PUSH_FLAGS\n' + ' push %s\n' + % ( cAddrBits, cEffOpBits, iBaseReg, u32Disp, iIndexReg, iScale, + sName, self.oTarget.asGRegs[iTmpReg1], )); + + # Figure out what to use. + if cEffOpBits == 64: + sTmpReg1 = g_asGRegs64[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u64Data)'; + elif cEffOpBits == 32: + sTmpReg1 = g_asGRegs32[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u32Data)'; + elif cEffOpBits == 16: + sTmpReg1 = g_asGRegs16[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u16Data)'; + else: + assert cEffOpBits == 8; assert iTmpReg1 < 4; + sTmpReg1 = g_asGRegs8Rex[iTmpReg1]; + sDataVar = 'VBINSTST_NAME(g_u8Data)'; + + # Special case: reg + reg * [2,4,8] + if iBaseReg == iIndexReg and iBaseReg is not None and iScale != 1: + iTmpReg2 = X86_GREG_xBP; + while iTmpReg2 in [iBaseReg, iIndexReg, iTmpReg1]: + iTmpReg2 += 1; + sTmpReg2 = self.gregNameBits(iTmpReg2, cAddrBits); + self.write(' push sAX\n' + ' push %s\n' + ' push sDX\n' + % (self.oTarget.asGRegs[iTmpReg2],)); + if cAddrBits == 16: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sTmpReg2,)); + else: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sTmpReg2,)); + self.write(' add %s, 0x200\n' % (sTmpReg2,)); + self.write(' mov %s, %s\n' % (self.gregNameBits(X86_GREG_xAX, cAddrBits), sTmpReg2,)); + if u32Disp is not None: + self.write(' sub %s, %d\n' + % ( self.gregNameBits(X86_GREG_xAX, cAddrBits), convU32ToSigned(u32Disp), )); + self.write(' xor edx, edx\n' + '%if xCB == 2\n' + ' push 0\n' + '%endif\n'); + self.write(' push %u\n' % (iScale + 1,)); + self.write(' div %s [xSP]\n' % ('qword' if cAddrBits == 64 else 'dword',)); + self.write(' sub %s, %s\n' % (sTmpReg2, self.gregNameBits(X86_GREG_xDX, cAddrBits),)); + self.write(' pop sDX\n' + ' pop sDX\n'); # sTmpReg2 is eff address; sAX is sIndexReg value. + # Note! sTmpReg1 can be xDX and that's no problem now. + self.write(' mov %s, [xSP + sCB*3 + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,)); + self.write(' mov [%s], %s\n' % (sTmpReg2, sTmpReg1,)); # Value in place. + self.write(' pop %s\n' % (self.oTarget.asGRegs[iTmpReg2],)); + if iBaseReg == X86_GREG_xAX: + self.write(' pop %s\n' % (self.oTarget.asGRegs[iTmpReg1],)); + else: + self.write(' mov %s, %s\n' % (sBaseReg, self.gregNameBits(X86_GREG_xAX, cAddrBits),)); + self.write(' pop sAX\n'); + + else: + # Load the value and mem address, storing the value there. + # Note! ASSUMES that the scale and disposition works fine together. + sAddrReg = sBaseReg if sBaseReg is not None else sIndexReg; + self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,)); + if cAddrBits >= cDefAddrBits: + self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,)); + self.write(' lea %s, [%s xWrtRIP]\n' % (sAddrReg, sDataVar,)); + else: + if cAddrBits == 16: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sAddrReg,)); + else: + self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sAddrReg,)); + self.write(' add %s, %s\n' % (sAddrReg, (randU16() << cEffOpBits) & 0xfff, )); + self.write(' mov [%s], %s\n' % (sAddrReg, sTmpReg1, )); + + # Adjust for disposition and scaling. + if u32Disp is not None: + self.write(' sub %s, %d\n' % ( sAddrReg, convU32ToSigned(u32Disp), )); + if iIndexReg is not None: + if iBaseReg == iIndexReg: + assert iScale == 1; + assert u32Disp is None or (u32Disp & 1) == 0; + self.write(' shr %s, 1\n' % (sIndexReg,)); + elif sBaseReg is not None: + uIdxRegVal = randUxx(cAddrBits); + if cAddrBits == 64: + self.write(' mov %s, %u\n' + ' sub %s, %s\n' + ' mov %s, %u\n' + % ( sIndexReg, (uIdxRegVal * iScale) & UINT64_MAX, + sBaseReg, sIndexReg, + sIndexReg, uIdxRegVal, )); + else: + assert cAddrBits == 32; + self.write(' mov %s, %u\n' + ' sub %s, %#06x\n' + % ( sIndexReg, uIdxRegVal, sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, )); + elif iScale == 2: + assert u32Disp is None or (u32Disp & 1) == 0; + self.write(' shr %s, 1\n' % (sIndexReg,)); + elif iScale == 4: + assert u32Disp is None or (u32Disp & 3) == 0; + self.write(' shr %s, 2\n' % (sIndexReg,)); + elif iScale == 8: + assert u32Disp is None or (u32Disp & 7) == 0; + self.write(' shr %s, 3\n' % (sIndexReg,)); + else: + assert iScale == 1; + + # Set upper bits that's supposed to be unused. + if cDefAddrBits > cAddrBits or cAddrBits == 16: + if cDefAddrBits == 64: + assert cAddrBits == 32; + if iBaseReg is not None: + self.write(' mov %s, %#018x\n' + ' or %s, %s\n' + % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000, + g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],)); + if iIndexReg is not None and iIndexReg != iBaseReg: + self.write(' mov %s, %#018x\n' + ' or %s, %s\n' + % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000, + g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],)); + else: + assert cDefAddrBits == 32; assert cAddrBits == 16; assert iIndexReg is None; + if iBaseReg is not None: + self.write(' or %s, %#010x\n' + % ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, )); + + # Epilogue. + self.write(' pop %s\n' + ' MY_POP_FLAGS\n' + ' ret sCB\n' + 'VBINSTST_ENDPROC Common_MemSetup_%s\n' + % ( self.oTarget.asGRegs[iTmpReg1], sName,)); + + + def _generateFileFooter(self): + """ + Generates file footer. + """ + + # Terminate the trap records. + self.write('\n\n' + ';\n' + '; Terminate the trap records\n' + ';\n' + 'VBINSTST_BEGINDATA\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + 'VBINSTST_TRAP_RECS_END\n' + '%endif\n' + 'VBINSTST_BEGINCODE\n'); + + # Register checking functions. + for sName in self._dCheckFns: + asRegs = sName.split('_'); + sPushSize = 'dword'; + + # Do we check eflags first. + if asRegs[0] == 'eflags': + asRegs.pop(0); + sFlagsToCheck = asRegs.pop(0); + self.write('\n\n' + '; Check flags and then defers to the register-only checker\n' + '; To save space, the callee cleans up the stack.' + '; Ref count: %u\n' + 'VBINSTST_BEGINPROC %s%s\n' + ' MY_PUSH_FLAGS\n' + ' push sAX\n' + ' mov sAX, [xSP + sCB]\n' + ' and sAX, %s\n' + ' cmp sAX, [xSP + xCB + sCB*2]\n' + ' je .equal\n' + % ( self._dCheckFns[sName], self.ksCheckerPrefix, sName, + sFlagsToCheck,)); + self.write(' push dword 0xef ; register number\n' + ' push sAX ; actual\n' + ' mov sAX, [xSP + xCB + sCB*4]\n' + ' push sAX ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n'); + self.write('.equal:\n' + ' mov xAX, [xSP + sCB*2]\n' # Remove the expected eflags value from the stack frame. + ' mov [xSP + sCB*2 + xCB + sCB - xCB], xAX\n' + ' pop sAX\n' + ' MY_POP_FLAGS\n' + ' lea xSP, [xSP + sCB]\n' + ' jmp VBINSTST_NAME(Common_Check_%s)\n' + 'VBINSTST_ENDPROC %s%s\n' + % ( '_'.join(asRegs), + self.ksCheckerPrefix, sName,) ); + else: + # Prologue + self.write('\n\n' + '; Checks 1 or more register values, expected values pushed on the stack.\n' + '; To save space, the callee cleans up the stack.' + '; Ref count: %u\n' + 'VBINSTST_BEGINPROC %s%s\n' + ' MY_PUSH_FLAGS\n' + % ( self._dCheckFns[sName], self.ksCheckerPrefix, sName, ) ); + + # Register checks. + for i in range(len(asRegs)): + sReg = asRegs[i]; + iReg = self.oTarget.asGRegs.index(sReg); + if i == asRegs.index(sReg): # Only check once, i.e. input = output reg. + self.write(' cmp %s, [xSP + MY_PUSH_FLAGS_SIZE + xCB + sCB * %u]\n' + ' je .equal%u\n' + ' push %s %u ; register number\n' + ' push %s ; actual\n' + ' mov %s, [xSP + sCB*2 + MY_PUSH_FLAGS_SIZE + xCB + sCB * %u]\n' + ' push %s ; expected\n' + ' call VBINSTST_NAME(Common_BadValue)\n' + '.equal%u:\n' + % ( sReg, i, i, sPushSize, iReg, sReg, sReg, i, sReg, i, ) ); + + + # Restore known register values and check the other registers. + for sReg in asRegs: + if self.oTarget.is64Bit(): + self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg, sReg,)); + else: + iReg = self.oTarget.asGRegs.index(sReg) + self.write(' mov %s, 0x%x\n' % (sReg, self.au32Regs[iReg],)); + self.write(' MY_POP_FLAGS\n' + ' call VBINSTST_NAME(Common_CheckKnownValues)\n' + ' ret sCB*%u\n' + 'VBINSTST_ENDPROC %s%s\n' + % (len(asRegs), self.ksCheckerPrefix, sName,)); + + # memory setup functions + self._generateMemSetupFunctions(); + + # 64-bit constants. + if len(self._d64BitConsts) > 0: + self.write('\n\n' + ';\n' + '; 64-bit constants\n' + ';\n'); + for uVal in self._d64BitConsts: + self.write('g_u64Const_0x%016x: dq 0x%016x ; Ref count: %d\n' % (uVal, uVal, self._d64BitConsts[uVal], ) ); + + return True; + + def _generateTests(self): + """ + Generate the test cases. + """ + for self.iFile in range(self.cFiles): + if self.cFiles == 1: + self.sFile = '%s.asm' % (self.oOptions.sOutputBase,) + else: + self.sFile = '%s-%u.asm' % (self.oOptions.sOutputBase, self.iFile) + self.oFile = sys.stdout; + if self.oOptions.sOutputBase != '-': + self.oFile = io.open(self.sFile, 'w', buffering = 65536, encoding = 'utf-8'); + + self._generateFileHeader(); + + # Calc the range. + iInstrTestStart = self.iFile * self.oOptions.cInstrPerFile; + iInstrTestEnd = iInstrTestStart + self.oOptions.cInstrPerFile; + if iInstrTestEnd > len(g_aoInstructionTests): + iInstrTestEnd = len(g_aoInstructionTests); + + # Generate the instruction tests. + for iInstrTest in range(iInstrTestStart, iInstrTestEnd): + oInstrTest = g_aoInstructionTests[iInstrTest]; + if oInstrTest.isApplicable(self): + self.write('\n' + '\n' + ';\n' + '; %s\n' + ';\n' + % (oInstrTest.sName,)); + self._randInitIndexes(); + oInstrTest.generateTest(self, self._calcTestFunctionName(oInstrTest, iInstrTest)); + + # Generate the main function. + self.write('\n\n' + 'VBINSTST_BEGINPROC TestInstrMain\n' + ' MY_PUSH_ALL\n' + ' sub xSP, 40h\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + ' VBINSTST_TRAP_RECS_INSTALL\n' + '%endif\n' + '\n'); + + for iInstrTest in range(iInstrTestStart, iInstrTestEnd): + oInstrTest = g_aoInstructionTests[iInstrTest]; + if oInstrTest.isApplicable(self): + self.write('%%ifdef ASM_CALL64_GCC\n' + ' lea rdi, [.szInstr%03u wrt rip]\n' + '%%elifdef ASM_CALL64_MSC\n' + ' lea rcx, [.szInstr%03u wrt rip]\n' + '%%else\n' + ' mov xAX, .szInstr%03u\n' + ' mov [xSP], xAX\n' + '%%endif\n' + ' VBINSTST_CALL_FN_SUB_TEST\n' + ' call VBINSTST_NAME(%s)\n' + % ( iInstrTest, iInstrTest, iInstrTest, self._calcTestFunctionName(oInstrTest, iInstrTest))); + + self.write('\n' + '%ifdef VBINSTST_CAN_DO_TRAPS\n' + ' VBINSTST_TRAP_RECS_UNINSTALL\n' + '%endif\n' + ' add xSP, 40h\n' + ' MY_POP_ALL\n' + ' ret\n\n'); + for iInstrTest in range(iInstrTestStart, iInstrTestEnd): + self.write('.szInstr%03u: db \'%s\', 0\n' % (iInstrTest, g_aoInstructionTests[iInstrTest].sName,)); + self.write('VBINSTST_ENDPROC TestInstrMain\n\n'); + + self._generateFileFooter(); + if self.oOptions.sOutputBase != '-': + self.oFile.close(); + self.oFile = None; + self.sFile = ''; + + return RTEXITCODE_SUCCESS; + + def _runMakefileMode(self): + """ + Generate a list of output files on standard output. + """ + if self.cFiles == 1: + print('%s.asm' % (self.oOptions.sOutputBase,)); + else: + print(' '.join('%s-%s.asm' % (self.oOptions.sOutputBase, i) for i in range(self.cFiles))); + return RTEXITCODE_SUCCESS; + + def run(self): + """ + Generates the tests or whatever is required. + """ + if self.oOptions.fMakefileMode: + return self._runMakefileMode(); + sys.stderr.write('InstructionTestGen.py: Seed = %s\n' % (g_iMyRandSeed,)); + return self._generateTests(); + + @staticmethod + def main(): + """ + Main function a la C/C++. Returns exit code. + """ + + # + # Parse the command line. + # + oParser = OptionParser(version = __version__[11:-1].strip()); + oParser.add_option('--makefile-mode', dest = 'fMakefileMode', action = 'store_true', default = False, + help = 'Special mode for use to output a list of output files for the benefit of ' + 'the make program (kmk).'); + oParser.add_option('--split', dest = 'cInstrPerFile', metavar = '<instr-per-file>', type = 'int', default = 9999999, + help = 'Number of instruction to test per output file.'); + oParser.add_option('--output-base', dest = 'sOutputBase', metavar = '<file>', default = None, + help = 'The output file base name, no suffix please. Required.'); + oParser.add_option('--target', dest = 'sTargetEnv', metavar = '<target>', + default = 'iprt-r3-32', + choices = g_dTargetEnvs.keys(), + help = 'The target environment. Choices: %s' + % (', '.join(sorted(g_dTargetEnvs.keys())),)); + oParser.add_option('--test-size', dest = 'sTestSize', default = InstructionTestGen.ksTestSize_Medium, + choices = InstructionTestGen.kasTestSizes, + help = 'Selects the test size.'); + + (oOptions, asArgs) = oParser.parse_args(); + if len(asArgs) > 0: + oParser.print_help(); + return RTEXITCODE_SYNTAX + if oOptions.sOutputBase is None: + print('syntax error: Missing required option --output-base.', file = sys.stderr); + return RTEXITCODE_SYNTAX + + # + # Instantiate the program class and run it. + # + oProgram = InstructionTestGen(oOptions); + return oProgram.run(); + + +if __name__ == '__main__': + sys.exit(InstructionTestGen.main()); + diff --git a/src/VBox/VMM/testcase/Instructions/Makefile.kmk b/src/VBox/VMM/testcase/Instructions/Makefile.kmk new file mode 100644 index 00000000..f5298580 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/Makefile.kmk @@ -0,0 +1,69 @@ +# $Id: Makefile.kmk $ +## @file +# Sub-Makefile for the X86 and AMD64 Instruction Tests. +# + +# +# Copyright (C) 2006-2013 Oracle Corporation +# +# This file is part of VirtualBox Open Source Edition (OSE), as +# available from http://www.virtualbox.org. This file is free software; +# you can redistribute it and/or modify it under the terms of the GNU +# General Public License (GPL) as published by the Free Software +# Foundation, in version 2 as it comes in the "COPYING" file of the +# VirtualBox OSE distribution. VirtualBox OSE is distributed in the +# hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +# + +SUB_DEPTH = ../../../../.. +include $(KBUILD_PATH)/subheader.kmk + +# +# Python linting (can't live without pylint!). +# +ifdef VBOX_WITH_PYLINT + TESTING += +endif +BLDDIRS += $(PATH_TARGET)/pylint + +define def_vbox_instructions_py_check +$(eval name:=$(basename $(notdir $(py)))) + +pylint:: $(name)-py-phony.o +$(name).o: $(name)-py-phony.o +$(PATH_TARGET)/pylint/$(name).o $(name)-py-phony.o:: $(py) | $(PATH_TARGET)/pylint/ +ifdef VBOX_WITH_PYLINT + $(QUIET2)$(call MSG_L1,Subjecting $(py) to pylint...) + $(QUIET)$(REDIRECT_EXT) -E LC_ALL=C -E PYTHONPATH="$(dir $(py))" -C $(dir $(py)) \ + -- $$(VBOX_PYLINT) $$(VBOX_PYLINT_FLAGS) $$($(py)_VBOX_PYLINT_FLAGS) ./$(notdir $(py)) +endif + $(QUIET)$(APPEND) -t "$(PATH_TARGET)/pylint/$(name).o" + +TESTING += $(name)-py-phony.o +endef # def_vbox_instructions_py_check + + +$(foreach py, $(addprefix $(PATH_SUB_CURRENT)/, InstructionTestGen.py ) , $(eval $(def_vbox_instructions_py_check))) + + + +# +# Ring-3 test program based on IPRT. +# +PROGRAMS += tstVBInsTstR3 +tstVBInsTstR3_TEMPLATE = VBOXR3TSTEXE +tstVBInsTstR3_INCS = . +tstVBInsTstR3_SOURCES = \ + tstVBInsTstR3.cpp \ + $(tstVBInsTstR3_0_OUTDIR)/tstVBInsTstR3A.asm +tstVBInsTstR3_CLEAN = \ + $(tstVBInsTstR3_0_OUTDIR)/tstVBInsTstR3A.asm + +$$(tstVBInsTstR3_0_OUTDIR)/tstVBInsTstR3A.asm: $(PATH_SUB_CURRENT)/InstructionTestGen.py + $(VBOX_BLD_PYTHON) $(PATH_SUB_CURRENT)/InstructionTestGen.py \ + --target iprt-r3-$(if-expr $(intersects $(KBUILD_TARGET_ARCH), $(KBUILD_ARCHES_64)),64,32) \ + --output-base $(basename $@) + + +include $(FILE_KBUILD_SUB_FOOTER) + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac new file mode 100644 index 00000000..812ad752 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-32-big.mac @@ -0,0 +1,35 @@ +; $Id: env-bs2-r0-32-big.mac $ +;; @file +; Instruction Test Environment - Big Boot Sector Type 2, Ring-0, 64-Bit. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%undef RT_ARCH_AMD64 +%undef RT_ARCH_X86 +%undef RT_ARCH_X86_32 +%undef RT_ARCH_X86_16 +%undef ASM_CALL64_MSC +%undef ASM_CALL64_GCC +%undef ASM_CALL64_BS2 +%undef ARCH_BITS +%undef xWrtRIP + +%define ARCH_BITS 32 +%define RT_ARCH_X86 +%define ASM_CALL32_BS2 +%define xWrtRIP +%define RTCCPTR_PRE dword + +%include "env-bs2-r0-big.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac new file mode 100644 index 00000000..4c126d30 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64-big.mac @@ -0,0 +1,35 @@ +; $Id: env-bs2-r0-64-big.mac $ +;; @file +; Instruction Test Environment - Big Boot Sector Type 2, Ring-0, 64-Bit. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%undef RT_ARCH_AMD64 +%undef RT_ARCH_X86 +%undef RT_ARCH_X86_32 +%undef RT_ARCH_X86_16 +%undef ASM_CALL64_MSC +%undef ASM_CALL64_GCC +%undef ASM_CALL64_BS2 +%undef ARCH_BITS +%undef xWrtRIP + +%define ARCH_BITS 64 +%define RT_ARCH_AMD64 +%define ASM_CALL64_BS2 +%define xWrtRIP wrt rip +%define RTCCPTR_PRE qword + +%include "env-bs2-r0-big.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac new file mode 100644 index 00000000..da41ba8d --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-64.mac @@ -0,0 +1,35 @@ +; $Id: env-bs2-r0-64.mac $ +;; @file +; Instruction Test Environment - Boot Sector Type 2, Ring-0, 64-Bit. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%undef RT_ARCH_AMD64 +%undef RT_ARCH_X86 +%undef RT_ARCH_X86_32 +%undef RT_ARCH_X86_16 +%undef ASM_CALL64_MSC +%undef ASM_CALL64_GCC +%undef ASM_CALL64_BS2 +%undef ARCH_BITS +%undef xWrtRIP + +%define ARCH_BITS 64 +%define RT_ARCH_AMD64 +%define ASM_CALL64_BS2 +%define xWrtRIP wrt rip +%define RTCCPTR_PRE qword + +%include "env-bs2-r0.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac new file mode 100644 index 00000000..3c1d39da --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-big.mac @@ -0,0 +1,57 @@ +; $Id: env-bs2-r0-big.mac $ +;; @file +; Instruction Test Environment - Big Boot Sector Type 2, Ring-0. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_bs2_r0_big_mac +%define ___env_bs2_r0_big_mac + +; +; Include the BS2 API for BIG images. +; +%include "bootsector2-api.mac" + + +;; Call RTTestISub like function. +%define VBINSTST_CALL_FN_SUB_TEST call [TMPL_NM_CMN(g_pfnTestSub) xWrtRIP] + +;; Call RTTestIFailure like function with simple message. +%define VBINSTST_CALL_FN_FAILURE call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 1 arg. +%define VBINSTST_CALL_FN_FAILURE_1 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 2 args. +%define VBINSTST_CALL_FN_FAILURE_2 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 3 args. +%define VBINSTST_CALL_FN_FAILURE_3 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; Call RTTestIFailure like function with format message + 4 args. +%define VBINSTST_CALL_FN_FAILURE_4 call [TMPL_NM_CMN(g_pfnTestFailedF) xWrtRIP] + +;; The image base label (used by the trap macros). +%define VBINSTST_IMAGE_BASE_LABLE bs2_big_image_start + +;; Wrapper for calling TestInstallTrapRecs (used by the trap macros). +%define VBINSTST_CALL_TEST_INSTALL_TRAP_RECS call [TMPL_NM_CMN(g_pfnTestInstallTrapRecs) xWrtRIP] + +; +; Include the common bits (contains code using above macros) +; +%include "env-bs2-r0-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac new file mode 100644 index 00000000..1de2f1de --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0-common.mac @@ -0,0 +1,115 @@ +; $Id: env-bs2-r0-common.mac $ +;; @file +; Instruction Test Environment - Boot Sector Type 2, Ring-0. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_bs2_r0_common_mac +%define ___env_bs2_r0_common_mac + + +;; Same as BEGINPROC in asmdefs.mac. +%macro VBINSTST_BEGINPROC 1 +VBINSTST_GLOBALNAME_EX %1, function hidden +%endm + +;; Same as ENDPROC in asmdefs.mac. +%macro VBINSTST_ENDPROC 1, +VBINSTST_GLOBALNAME_EX %1 %+ _EndProc, function hidden +%endm + +;; Same as NAME in asmdefs.mac. +%define VBINSTST_NAME(a_Name) TMPL_NM(a_Name) + +;; Same as GLOBALNAME_EX in asmdefs.mac. +%macro VBINSTST_GLOBALNAME_EX 2, +VBINSTST_NAME(%1): +%endmacro + +;; Same as BEGINCODE in asmdefs.mac. +%macro VBINSTST_BEGINCODE 0, +BEGINCODE +%endmacro + +;; Same as BEGINDATA in asmdefs.mac. +%macro VBINSTST_BEGINDATA 0, +BEGINDATA +%endmacro + + +; +; Trap related macros. +; +%define VBINSTST_CAN_DO_TRAPS 1 + +%macro VBINSTST_TRAP_INSTR 3+, + section .traprecs + istruc BS2TRAPREC + at BS2TRAPREC.offWhere, dd (%%trapinstr - VBINSTST_IMAGE_BASE_LABLE) + at BS2TRAPREC.offResumeAddend, db (%%resume - %%trapinstr) + at BS2TRAPREC.u8TrapNo, db %1 + at BS2TRAPREC.u16ErrCd, dw %2 + iend + VBINSTST_BEGINCODE + %if %1 != X86_XCPT_BP + %%trapinstr: + %3 + %else + %3 + %%trapinstr: + %endif + call VBINSTST_NAME(Common_MissingTrap_ %+ %1) + %%resume: +%endmacro + +%macro VBINSTST_TRAP_RECS_BEGIN 0, + VBINSTST_BEGINDATA + section .traprecs progbits valign=8 vfollows=.data align=8 follows=.data + dq 0ffffffffeeeeeeeeh + dq 0ddddddddcccccccch +VBINSTST_GLOBALNAME_EX g_aTrapRecs, hidden + VBINSTST_BEGINCODE +%endmacro + +%macro VBINSTST_TRAP_RECS_END 0, + section .traprecs +VBINSTST_GLOBALNAME_EX g_aTrapRecsEnd, hidden + dq 0ddddddddcccccccch + dq 0ffffffffeeeeeeeeh + VBINSTST_BEGINCODE +%endmacro + +%macro VBINSTST_TRAP_RECS_INSTALL 0, + mov sAX, VBINSTST_NAME(g_aTrapRecs) + mov edx, VBINSTST_NAME(g_aTrapRecsEnd) - VBINSTST_NAME(g_aTrapRecs) + shr edx, BS2TRAPREC_SIZE_SHIFT + mov sCX, VBINSTST_IMAGE_BASE_LABLE + VBINSTST_CALL_TEST_INSTALL_TRAP_RECS +%endmacro + +%macro VBINSTST_TRAP_RECS_UNINSTALL 0, + xor sAX, sAX + xor edx, edx + xor sCX, sCX + VBINSTST_CALL_TEST_INSTALL_TRAP_RECS +%endmacro + + +; +; Include the common bits (contains code using above macros) +; +%include "env-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac b/src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac new file mode 100644 index 00000000..2e32a81f --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-bs2-r0.mac @@ -0,0 +1,53 @@ +; $Id: env-bs2-r0.mac $ +;; @file +; Instruction Test Environment - Boot Sector Type 2, Ring-0. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_bs2_r0_mac +%define ___env_bs2_r0_mac + + +;; Call RTTestISub like function. +%define VBINSTST_CALL_FN_SUB_TEST call TMPL_NM_CMN(TestSub) + +;; Call RTTestIFailure like function with simple message. +%define VBINSTST_CALL_FN_FAILURE call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 1 arg. +%define VBINSTST_CALL_FN_FAILURE_1 call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 2 args. +%define VBINSTST_CALL_FN_FAILURE_2 call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 3 args. +%define VBINSTST_CALL_FN_FAILURE_3 call TMPL_NM_CMN(TestFailedF) + +;; Call RTTestIFailure like function with format message + 4 args. +%define VBINSTST_CALL_FN_FAILURE_4 call TMPL_NM_CMN(TestFailedF) + +;; The image base label (used by the trap macros). +%define VBINSTST_IMAGE_BASE_LABLE start + +;; Wrapper for calling TestInstallTrapRecs (used by the trap macros). +%define VBINSTST_CALL_TEST_INSTALL_TRAP_RECS call TMPL_NM_CMN(TestInstallTrapRecs) + + +; +; Include the common bits (contains code using above macros) +; +%include "env-bs2-r0-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-common.mac b/src/VBox/VMM/testcase/Instructions/env-common.mac new file mode 100644 index 00000000..ff8aeb7c --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-common.mac @@ -0,0 +1,346 @@ +; $Id: env-common.mac $ +;; @file +; Instruction Test Environment - Common Bits. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_common_mac +%define ___env_common_mac + +%include "iprt/x86.mac" + +;******************************************************************************* +;* Defined Constants And Macros * +;******************************************************************************* +%ifdef RT_ARCH_AMD64 + %define MY_PUSH_FLAGS pushfq + %define MY_POP_FLAGS popfq + %define MY_PUSH_FLAGS_SIZE 8 + + %macro MY_PUSH_ALL 0 + push rbp + mov rbp, rsp + push rax + push rbx + push rcx + push rdx + push rsi + push rdi + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + pushfq + %endm + %macro MY_POP_ALL 0 + popfq + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 + pop rdi + pop rsi + pop rdx + pop rcx + pop rbx + pop rax + pop rbp + %endm + +%else + %define MY_PUSH_FLAGS pushfd + %define MY_POP_FLAGS popfd + %define MY_PUSH_FLAGS_SIZE 4 + + %macro MY_PUSH_ALL 0 + push eBP + mov xBP, xSP + push eax + push ebx + push ecx + push edx + push esi + push edi + pushfd + %endm + %macro MY_POP_ALL 0 + popfd + pop edi + pop esi + pop edx + pop ecx + pop ebx + pop eax + pop ebp + %endm +%endif + + + +;******************************************************************************* +;* Internal Functions * +;******************************************************************************* + +VBINSTST_BEGINCODE + +;; +; Report bad register value. +; +; Primary purpose is save all registers and convert from our stack-based to +; the correct calling convention for the environment. +; +; This function will clean up the stack upon return (to save space in the caller). +; +; @param uExpected +; @param uActual +; @param uRegisterNo +; +VBINSTST_BEGINPROC Common_BadValue + MY_PUSH_ALL + mov xAX, xSP ; 16-byte align the stack and reserve space for arguments and stuff. + sub xSP, 40h + and xSP, ~15 + mov [xSP + 38h], xAX + +%ifdef ASM_CALL64_GCC + mov r8d, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + mov rcx, [rbp + 10h] ; expected + mov rdx, [rbp + 18h] ; actual + mov rsi, [rbp + 20h] ; reg# + lea rdi, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_4 + +%elifdef ASM_CALL64_MSC + mov r10d, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + mov [rsp + 20h], r10 + mov r9, [rbp + 10h] ; expected + mov r8, [rbp + 18h] ; actual + mov rdx, [rbp + 20h] ; reg# + lea rcx, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_4 + +%elifdef ASM_CALL64_BS2 + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP] + mov sCX, [xBP + xCB + xCB] ; expected + mov sAX, [xBP + xCB + xCB + sCB*1] ; actual + mov sDX, [xBP + xCB + xCB + sCB*2] ; reg# + lea sSI, [.szFmt xWrtRIP] + mov qword [xSP + xCB + 3*sCB], sBX + mov qword [xSP + xCB + 2*sCB], sCX + mov qword [xSP + xCB + 1*sCB], sAX + mov qword [xSP + xCB], sDX + mov [xSP], sSI + VBINSTST_CALL_FN_FAILURE_4 + +%else + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator)] + mov sCX, [xBP + xCB + xCB] ; expected + mov sAX, [xBP + xCB + xCB + sCB*1] ; actual + mov sDX, [xBP + xCB + xCB + sCB*2] ; reg# + mov [xSP + xCB + 3*sCB], sBX + mov [xSP + xCB + 2*sCB], sCX + mov [xSP + xCB + 1*sCB], sAX + mov [xSP + xCB], sDX + mov [xSP], RTCCPTR_PRE .szFmt + VBINSTST_CALL_FN_FAILURE_4 +%endif + + mov xSP, [xSP + 38h] + MY_POP_ALL + ret 3*sCB +%if ARCH_BITS == 64 +.szFmt: db 'Bad register 0x%RX32 value 0x%RX64, expected 0x%RX64 (line %RU64)', 13, 0 +%else +.szFmt: db 'Bad register 0x%RX32 value 0x%RX32, expected 0x%RX32 (line %RU32)', 13, 0 +%endif +VBINSTST_ENDPROC Common_BadValue + + +%ifdef VBINSTST_CAN_DO_TRAPS + +;; +; Report a missing TRAP. +; +; Primary purpose is save all registers and convert from our stack-based to +; the correct calling convention for the environment. +; +; This function will clean up the stack upon return (to save space in the caller). +; +; @param uExpected +; +VBINSTST_BEGINPROC Common_MissingTrap + MY_PUSH_ALL + mov xAX, xSP ; 16-byte align the stack and reserve space for arguments and stuff. + sub xSP, 40h + and xSP, ~15 + mov [xSP + 38h], xAX + + %ifdef ASM_CALL64_GCC + mov rdx, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + movzx rsi, byte [rbp + 10h] ; expected + lea rdi, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_2 + + %elifdef ASM_CALL64_MSC + mov r8d, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) wrt rip] + movzx rdx, byte [rbp + 10h] ; expected + lea rcx, [.szFmt wrt rip] + VBINSTST_CALL_FN_FAILURE_2 + + %elifdef ASM_CALL64_BS2 + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP] + mov sDX, [xBP + xCB + xCB] ; expected + lea sSI, [.szFmt xWrtRIP] + mov qword [xSP + xCB + 1*sCB], sBX + mov qword [xSP + xCB], sDX + mov [xSP], sSI + VBINSTST_CALL_FN_FAILURE_2 + + %else + mov sBX, [VBINSTST_NAME(g_uVBInsTstSubTestIndicator)] + mov sDX, [xBP + xCB + xCB] ; expected + mov [xSP + xCB + 1*sCB], sBX + mov [xSP + xCB], sDX + mov [xSP], RTCCPTR_PRE .szFmt + VBINSTST_CALL_FN_FAILURE_2 + %endif + + mov xSP, [xSP + 38h] + MY_POP_ALL + ret 1*sCB + %if ARCH_BITS == 64 +.szFmt: db 'Missing trap %RX8 (line %RU64)', 13, 0 + %else +.szFmt: db 'Missing trap %RX8 (line %RU32)', 13, 0 + %endif +VBINSTST_ENDPROC Common_MissingTrap + + %macro Common_MissingTrapTemplate 1 + VBINSTST_BEGINPROC Common_MissingTrap_%1 + push %1 + call VBINSTST_NAME(Common_MissingTrap) + ret + VBINSTST_ENDPROC Common_MissingTrap_%1 + %endmacro + Common_MissingTrapTemplate X86_XCPT_DE + Common_MissingTrapTemplate X86_XCPT_DB + Common_MissingTrapTemplate X86_XCPT_NMI + Common_MissingTrapTemplate X86_XCPT_BP + Common_MissingTrapTemplate X86_XCPT_OF + Common_MissingTrapTemplate X86_XCPT_BR + Common_MissingTrapTemplate X86_XCPT_UD + Common_MissingTrapTemplate X86_XCPT_NM + ;Common_MissingTrapTemplate X86_XCPT_DF + ;Common_MissingTrapTemplate X86_XCPT_CO_SEG_OVERRUN + Common_MissingTrapTemplate X86_XCPT_TS + Common_MissingTrapTemplate X86_XCPT_NP + Common_MissingTrapTemplate X86_XCPT_SS + Common_MissingTrapTemplate X86_XCPT_GP + Common_MissingTrapTemplate X86_XCPT_PF + Common_MissingTrapTemplate X86_XCPT_MF + Common_MissingTrapTemplate X86_XCPT_AC + ;Common_MissingTrapTemplate X86_XCPT_MC + Common_MissingTrapTemplate X86_XCPT_XF + +%endif ; VBINSTST_CAN_DO_TRAPS + + +; +; Global data variables used by Common_SetupMemReadUxx. +; For address calculation reasons, these must be qword aligned. +; +VBINSTST_BEGINDATA + align 64 + dd 09d8af498h, 09ab3e5f8h +VBINSTST_GLOBALNAME_EX g_u64Data, data hidden + dq 0 + dd 07d7af797h, 096b36562h +VBINSTST_GLOBALNAME_EX g_u32Data, data hidden + dd 0 + dd 012305987h +VBINSTST_GLOBALNAME_EX g_u16Data, data hidden + dw 0 + dw 05865h + dw 03863h + dw 02679h +VBINSTST_GLOBALNAME_EX g_u8Data, data hidden + db 0 + db 90h + dw 0865ah + dd 058daffe2h + +VBINSTST_BEGINCODE + +;; +; Sets up g_u8Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU8 + push sAX + mov ax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u8Data) xWrtRIP], ax + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU8 + +;; +; Sets up g_u16Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU16 + push sAX + mov ax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u16Data) xWrtRIP], ax + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU16 + +;; +; Sets up g_u32Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU32 + push sAX + mov eax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u32Data) xWrtRIP], eax + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU32 + +;; +; Sets up g_u64Data. +; @param uValue +VBINSTST_BEGINPROC Common_SetupMemReadU64 + push sAX +%ifdef RT_ARCH_AMD64 + mov rax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u64Data) xWrtRIP], rax +%else + mov eax, [xSP + sCB + xCB] + mov [VBINSTST_NAME(g_u64Data) xWrtRIP], eax + mov eax, [xSP + sCB + xCB + 4] + mov [VBINSTST_NAME(g_u64Data) + 4 xWrtRIP], eax +%endif + pop sAX + ret sCB +VBINSTST_ENDPROC Common_SetupMemReadU64 + + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac new file mode 100644 index 00000000..b5225a40 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-32.mac @@ -0,0 +1,19 @@ +; $Id: env-iprt-r3-32.mac $ +;; @file +; Instruction Test Environment - IPRT, Ring-3, 32-Bit. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%include "env-iprt-r3.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac new file mode 100644 index 00000000..b172ecea --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-iprt-r3-64.mac @@ -0,0 +1,19 @@ +; $Id: env-iprt-r3-64.mac $ +;; @file +; Instruction Test Environment - IPRT, Ring-3, 64-Bit. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%include "env-iprt-r3.mac" + diff --git a/src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac b/src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac new file mode 100644 index 00000000..c64e45c1 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/env-iprt-r3.mac @@ -0,0 +1,99 @@ +; $Id: env-iprt-r3.mac $ +;; @file +; Instruction Test Environment - IPRT, Ring-3, 32-bit and 64-bit. +; + +; +; Copyright (C) 2006-2013 Oracle Corporation +; +; This file is part of VirtualBox Open Source Edition (OSE), as +; available from http://www.virtualbox.org. This file is free software; +; you can redistribute it and/or modify it under the terms of the GNU +; General Public License (GPL) as published by the Free Software +; Foundation, in version 2 as it comes in the "COPYING" file of the +; VirtualBox OSE distribution. VirtualBox OSE is distributed in the +; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +; + +%ifndef ___env_iprt_r3_mac +%define ___env_iprt_r3_mac + +;******************************************************************************* +;* Header Files * +;******************************************************************************* +%include "iprt/asmdefs.mac" + + +;******************************************************************************* +;* Defined Constants And Macros * +;******************************************************************************* +%define sAX xAX +%define sBX xBX +%define sCX xCX +%define sDX xDX +%define sSP xSP +%define sBP xBP +%define sSI xSI +%define sDI xDI +%define sCB xCB + + +;; Same as BEGINPROC in asmdefs.mac. +%macro VBINSTST_BEGINPROC 1 +BEGINPROC %1 +%endm + +;; Same as ENDPROC in asmdefs.mac. +%macro VBINSTST_ENDPROC 1 +ENDPROC %1 +%endm + +;; Same as NAME in asmdefs.mac. +%define VBINSTST_NAME(a_Name) NAME(a_Name) + +;; Same as GLOBALNAME_EX in asmdefs.mac. +%define VBINSTST_GLOBALNAME_EX GLOBALNAME_EX + +;; Same as BEGINCODE in asmdefs.mac. +%define VBINSTST_BEGINCODE BEGINCODE + +;; Same as BEGINDATA in asmdefs.mac. +%define VBINSTST_BEGINDATA BEGINDATA + + +;; Call RTTestISub like function. +%define VBINSTST_CALL_FN_SUB_TEST call IMP2(RTTestISub) +EXTERN_IMP2 RTTestISub + +;; Call RTTestIFailure like function with simple message. +%define VBINSTST_CALL_FN_FAILURE call NAME(VBInsTstFailure) +extern NAME(VBInsTstFailure) + +;; Call RTTestIFailure like function with format message + 1 arg. +%define VBINSTST_CALL_FN_FAILURE_1 call NAME(VBInsTstFailure1) +extern NAME(VBInsTstFailure1) + +;; Call RTTestIFailure like function with format message + 2 args. +%define VBINSTST_CALL_FN_FAILURE_2 call NAME(VBInsTstFailure2) +extern NAME(VBInsTstFailure2) + +;; Call RTTestIFailure like function with format message + 3 args. +%define VBINSTST_CALL_FN_FAILURE_3 call NAME(VBInsTstFailure3) +extern NAME(VBInsTstFailure3) + +;; Call RTTestIFailure like function with format message + 4 args. +%define VBINSTST_CALL_FN_FAILURE_4 call NAME(VBInsTstFailure4) +extern NAME(VBInsTstFailure4) + + +;; Cannot do traps yet. +%undef VBINSTST_CAN_DO_TRAPS + + +; +; Include the common bits (contains code using above macros) +; +%include "env-common.mac" + +%endif + diff --git a/src/VBox/VMM/testcase/Instructions/itgTableDaa.py b/src/VBox/VMM/testcase/Instructions/itgTableDaa.py new file mode 100644 index 00000000..04c6319c --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/itgTableDaa.py @@ -0,0 +1,1105 @@ +# -*- coding: utf-8 -*- +# $Id: itgTableDaa.py $ + +""" +DAA (instruction) result table. +""" + + +__copyright__ = \ +""" +Copyright (C) 2012-2013 Oracle Corporation + +This file is part of VirtualBox Open Source Edition (OSE), as +available from http://www.virtualbox.org. This file is free software; +you can redistribute it and/or modify it under the terms of the GNU +General Public License (GPL) as published by the Free Software +Foundation, in version 2 as it comes in the "COPYING" file of the +VirtualBox OSE distribution. VirtualBox OSE is distributed in the +hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +""" +__version__ = "$Revision: 90928 $"; + + +## The 32-bit GCC (C99) program that produced the table below. +g_sItgCProgramDaa = \ +""" +#include <stdio.h> + +int main() +{ + for (unsigned uInputAL = 0; uInputAL < 256; uInputAL++) + for (unsigned fAux = 0; fAux < 2; fAux++) + for (unsigned fCarry = 0; fCarry < 2; fCarry++) + { + unsigned uInputEFlags = fCarry | (fAux << 4); + unsigned uResultAL; + unsigned uResultEFlags; + __asm__ __volatile__("pushl %1\\n" + "popfl\\n" + "daa\\n" + "pushf\\n" + "pop %1\\n" + : "=a" (uResultAL), + "=r" (uResultEFlags) + : "0" (uInputAL), + "1" (uInputEFlags) + : "memory" + ); + printf(" ( 0x%02x, 0x%02x ), # AL=0x%02x, AF=%u CF=%u\\n", + uResultAL, uResultEFlags & 0xd5, uInputAL, fAux, fCarry); + /* 0xd5 = CF, PF, AF, ZF, SF */ + } + return 0; +} +"""; + + +# +# Compile and run the above program if requested to do so. +# +if __name__ == '__main__': + import sys; + if len(sys.argv) > 1 and sys.argv[1] == 'gen': + import subprocess; + oProc = subprocess.Popen(['gcc', '-x', 'c', '-std=gnu99', '-m32', '-o', './itgTableDaa', '-'], stdin = subprocess.PIPE); + oProc.communicate(g_sItgCProgramDaa); + oProc.wait(); + oProc = subprocess.Popen(['./itgTableDaa',]).wait(); + sys.exit(0); + + + +## +# The DAA results. +# +# The index / input relation is: index = (AL << 2) | (CF << 1) | AF +# +g_aItgDaaResults = \ +[ + ( 0x00, 0x44 ), # AL=0x00, AF=0 CF=0 + ( 0x60, 0x05 ), # AL=0x00, AF=0 CF=1 + ( 0x06, 0x14 ), # AL=0x00, AF=1 CF=0 + ( 0x66, 0x15 ), # AL=0x00, AF=1 CF=1 + ( 0x01, 0x00 ), # AL=0x01, AF=0 CF=0 + ( 0x61, 0x01 ), # AL=0x01, AF=0 CF=1 + ( 0x07, 0x10 ), # AL=0x01, AF=1 CF=0 + ( 0x67, 0x11 ), # AL=0x01, AF=1 CF=1 + ( 0x02, 0x00 ), # AL=0x02, AF=0 CF=0 + ( 0x62, 0x01 ), # AL=0x02, AF=0 CF=1 + ( 0x08, 0x10 ), # AL=0x02, AF=1 CF=0 + ( 0x68, 0x11 ), # AL=0x02, AF=1 CF=1 + ( 0x03, 0x04 ), # AL=0x03, AF=0 CF=0 + ( 0x63, 0x05 ), # AL=0x03, AF=0 CF=1 + ( 0x09, 0x14 ), # AL=0x03, AF=1 CF=0 + ( 0x69, 0x15 ), # AL=0x03, AF=1 CF=1 + ( 0x04, 0x00 ), # AL=0x04, AF=0 CF=0 + ( 0x64, 0x01 ), # AL=0x04, AF=0 CF=1 + ( 0x0a, 0x14 ), # AL=0x04, AF=1 CF=0 + ( 0x6a, 0x15 ), # AL=0x04, AF=1 CF=1 + ( 0x05, 0x04 ), # AL=0x05, AF=0 CF=0 + ( 0x65, 0x05 ), # AL=0x05, AF=0 CF=1 + ( 0x0b, 0x10 ), # AL=0x05, AF=1 CF=0 + ( 0x6b, 0x11 ), # AL=0x05, AF=1 CF=1 + ( 0x06, 0x04 ), # AL=0x06, AF=0 CF=0 + ( 0x66, 0x05 ), # AL=0x06, AF=0 CF=1 + ( 0x0c, 0x14 ), # AL=0x06, AF=1 CF=0 + ( 0x6c, 0x15 ), # AL=0x06, AF=1 CF=1 + ( 0x07, 0x00 ), # AL=0x07, AF=0 CF=0 + ( 0x67, 0x01 ), # AL=0x07, AF=0 CF=1 + ( 0x0d, 0x10 ), # AL=0x07, AF=1 CF=0 + ( 0x6d, 0x11 ), # AL=0x07, AF=1 CF=1 + ( 0x08, 0x00 ), # AL=0x08, AF=0 CF=0 + ( 0x68, 0x01 ), # AL=0x08, AF=0 CF=1 + ( 0x0e, 0x10 ), # AL=0x08, AF=1 CF=0 + ( 0x6e, 0x11 ), # AL=0x08, AF=1 CF=1 + ( 0x09, 0x04 ), # AL=0x09, AF=0 CF=0 + ( 0x69, 0x05 ), # AL=0x09, AF=0 CF=1 + ( 0x0f, 0x14 ), # AL=0x09, AF=1 CF=0 + ( 0x6f, 0x15 ), # AL=0x09, AF=1 CF=1 + ( 0x10, 0x10 ), # AL=0x0a, AF=0 CF=0 + ( 0x70, 0x11 ), # AL=0x0a, AF=0 CF=1 + ( 0x10, 0x10 ), # AL=0x0a, AF=1 CF=0 + ( 0x70, 0x11 ), # AL=0x0a, AF=1 CF=1 + ( 0x11, 0x14 ), # AL=0x0b, AF=0 CF=0 + ( 0x71, 0x15 ), # AL=0x0b, AF=0 CF=1 + ( 0x11, 0x14 ), # AL=0x0b, AF=1 CF=0 + ( 0x71, 0x15 ), # AL=0x0b, AF=1 CF=1 + ( 0x12, 0x14 ), # AL=0x0c, AF=0 CF=0 + ( 0x72, 0x15 ), # AL=0x0c, AF=0 CF=1 + ( 0x12, 0x14 ), # AL=0x0c, AF=1 CF=0 + ( 0x72, 0x15 ), # AL=0x0c, AF=1 CF=1 + ( 0x13, 0x10 ), # AL=0x0d, AF=0 CF=0 + ( 0x73, 0x11 ), # AL=0x0d, AF=0 CF=1 + ( 0x13, 0x10 ), # AL=0x0d, AF=1 CF=0 + ( 0x73, 0x11 ), # AL=0x0d, AF=1 CF=1 + ( 0x14, 0x14 ), # AL=0x0e, AF=0 CF=0 + ( 0x74, 0x15 ), # AL=0x0e, AF=0 CF=1 + ( 0x14, 0x14 ), # AL=0x0e, AF=1 CF=0 + ( 0x74, 0x15 ), # AL=0x0e, AF=1 CF=1 + ( 0x15, 0x10 ), # AL=0x0f, AF=0 CF=0 + ( 0x75, 0x11 ), # AL=0x0f, AF=0 CF=1 + ( 0x15, 0x10 ), # AL=0x0f, AF=1 CF=0 + ( 0x75, 0x11 ), # AL=0x0f, AF=1 CF=1 + ( 0x10, 0x00 ), # AL=0x10, AF=0 CF=0 + ( 0x70, 0x01 ), # AL=0x10, AF=0 CF=1 + ( 0x16, 0x10 ), # AL=0x10, AF=1 CF=0 + ( 0x76, 0x11 ), # AL=0x10, AF=1 CF=1 + ( 0x11, 0x04 ), # AL=0x11, AF=0 CF=0 + ( 0x71, 0x05 ), # AL=0x11, AF=0 CF=1 + ( 0x17, 0x14 ), # AL=0x11, AF=1 CF=0 + ( 0x77, 0x15 ), # AL=0x11, AF=1 CF=1 + ( 0x12, 0x04 ), # AL=0x12, AF=0 CF=0 + ( 0x72, 0x05 ), # AL=0x12, AF=0 CF=1 + ( 0x18, 0x14 ), # AL=0x12, AF=1 CF=0 + ( 0x78, 0x15 ), # AL=0x12, AF=1 CF=1 + ( 0x13, 0x00 ), # AL=0x13, AF=0 CF=0 + ( 0x73, 0x01 ), # AL=0x13, AF=0 CF=1 + ( 0x19, 0x10 ), # AL=0x13, AF=1 CF=0 + ( 0x79, 0x11 ), # AL=0x13, AF=1 CF=1 + ( 0x14, 0x04 ), # AL=0x14, AF=0 CF=0 + ( 0x74, 0x05 ), # AL=0x14, AF=0 CF=1 + ( 0x1a, 0x10 ), # AL=0x14, AF=1 CF=0 + ( 0x7a, 0x11 ), # AL=0x14, AF=1 CF=1 + ( 0x15, 0x00 ), # AL=0x15, AF=0 CF=0 + ( 0x75, 0x01 ), # AL=0x15, AF=0 CF=1 + ( 0x1b, 0x14 ), # AL=0x15, AF=1 CF=0 + ( 0x7b, 0x15 ), # AL=0x15, AF=1 CF=1 + ( 0x16, 0x00 ), # AL=0x16, AF=0 CF=0 + ( 0x76, 0x01 ), # AL=0x16, AF=0 CF=1 + ( 0x1c, 0x10 ), # AL=0x16, AF=1 CF=0 + ( 0x7c, 0x11 ), # AL=0x16, AF=1 CF=1 + ( 0x17, 0x04 ), # AL=0x17, AF=0 CF=0 + ( 0x77, 0x05 ), # AL=0x17, AF=0 CF=1 + ( 0x1d, 0x14 ), # AL=0x17, AF=1 CF=0 + ( 0x7d, 0x15 ), # AL=0x17, AF=1 CF=1 + ( 0x18, 0x04 ), # AL=0x18, AF=0 CF=0 + ( 0x78, 0x05 ), # AL=0x18, AF=0 CF=1 + ( 0x1e, 0x14 ), # AL=0x18, AF=1 CF=0 + ( 0x7e, 0x15 ), # AL=0x18, AF=1 CF=1 + ( 0x19, 0x00 ), # AL=0x19, AF=0 CF=0 + ( 0x79, 0x01 ), # AL=0x19, AF=0 CF=1 + ( 0x1f, 0x10 ), # AL=0x19, AF=1 CF=0 + ( 0x7f, 0x11 ), # AL=0x19, AF=1 CF=1 + ( 0x20, 0x10 ), # AL=0x1a, AF=0 CF=0 + ( 0x80, 0x91 ), # AL=0x1a, AF=0 CF=1 + ( 0x20, 0x10 ), # AL=0x1a, AF=1 CF=0 + ( 0x80, 0x91 ), # AL=0x1a, AF=1 CF=1 + ( 0x21, 0x14 ), # AL=0x1b, AF=0 CF=0 + ( 0x81, 0x95 ), # AL=0x1b, AF=0 CF=1 + ( 0x21, 0x14 ), # AL=0x1b, AF=1 CF=0 + ( 0x81, 0x95 ), # AL=0x1b, AF=1 CF=1 + ( 0x22, 0x14 ), # AL=0x1c, AF=0 CF=0 + ( 0x82, 0x95 ), # AL=0x1c, AF=0 CF=1 + ( 0x22, 0x14 ), # AL=0x1c, AF=1 CF=0 + ( 0x82, 0x95 ), # AL=0x1c, AF=1 CF=1 + ( 0x23, 0x10 ), # AL=0x1d, AF=0 CF=0 + ( 0x83, 0x91 ), # AL=0x1d, AF=0 CF=1 + ( 0x23, 0x10 ), # AL=0x1d, AF=1 CF=0 + ( 0x83, 0x91 ), # AL=0x1d, AF=1 CF=1 + ( 0x24, 0x14 ), # AL=0x1e, AF=0 CF=0 + ( 0x84, 0x95 ), # AL=0x1e, AF=0 CF=1 + ( 0x24, 0x14 ), # AL=0x1e, AF=1 CF=0 + ( 0x84, 0x95 ), # AL=0x1e, AF=1 CF=1 + ( 0x25, 0x10 ), # AL=0x1f, AF=0 CF=0 + ( 0x85, 0x91 ), # AL=0x1f, AF=0 CF=1 + ( 0x25, 0x10 ), # AL=0x1f, AF=1 CF=0 + ( 0x85, 0x91 ), # AL=0x1f, AF=1 CF=1 + ( 0x20, 0x00 ), # AL=0x20, AF=0 CF=0 + ( 0x80, 0x81 ), # AL=0x20, AF=0 CF=1 + ( 0x26, 0x10 ), # AL=0x20, AF=1 CF=0 + ( 0x86, 0x91 ), # AL=0x20, AF=1 CF=1 + ( 0x21, 0x04 ), # AL=0x21, AF=0 CF=0 + ( 0x81, 0x85 ), # AL=0x21, AF=0 CF=1 + ( 0x27, 0x14 ), # AL=0x21, AF=1 CF=0 + ( 0x87, 0x95 ), # AL=0x21, AF=1 CF=1 + ( 0x22, 0x04 ), # AL=0x22, AF=0 CF=0 + ( 0x82, 0x85 ), # AL=0x22, AF=0 CF=1 + ( 0x28, 0x14 ), # AL=0x22, AF=1 CF=0 + ( 0x88, 0x95 ), # AL=0x22, AF=1 CF=1 + ( 0x23, 0x00 ), # AL=0x23, AF=0 CF=0 + ( 0x83, 0x81 ), # AL=0x23, AF=0 CF=1 + ( 0x29, 0x10 ), # AL=0x23, AF=1 CF=0 + ( 0x89, 0x91 ), # AL=0x23, AF=1 CF=1 + ( 0x24, 0x04 ), # AL=0x24, AF=0 CF=0 + ( 0x84, 0x85 ), # AL=0x24, AF=0 CF=1 + ( 0x2a, 0x10 ), # AL=0x24, AF=1 CF=0 + ( 0x8a, 0x91 ), # AL=0x24, AF=1 CF=1 + ( 0x25, 0x00 ), # AL=0x25, AF=0 CF=0 + ( 0x85, 0x81 ), # AL=0x25, AF=0 CF=1 + ( 0x2b, 0x14 ), # AL=0x25, AF=1 CF=0 + ( 0x8b, 0x95 ), # AL=0x25, AF=1 CF=1 + ( 0x26, 0x00 ), # AL=0x26, AF=0 CF=0 + ( 0x86, 0x81 ), # AL=0x26, AF=0 CF=1 + ( 0x2c, 0x10 ), # AL=0x26, AF=1 CF=0 + ( 0x8c, 0x91 ), # AL=0x26, AF=1 CF=1 + ( 0x27, 0x04 ), # AL=0x27, AF=0 CF=0 + ( 0x87, 0x85 ), # AL=0x27, AF=0 CF=1 + ( 0x2d, 0x14 ), # AL=0x27, AF=1 CF=0 + ( 0x8d, 0x95 ), # AL=0x27, AF=1 CF=1 + ( 0x28, 0x04 ), # AL=0x28, AF=0 CF=0 + ( 0x88, 0x85 ), # AL=0x28, AF=0 CF=1 + ( 0x2e, 0x14 ), # AL=0x28, AF=1 CF=0 + ( 0x8e, 0x95 ), # AL=0x28, AF=1 CF=1 + ( 0x29, 0x00 ), # AL=0x29, AF=0 CF=0 + ( 0x89, 0x81 ), # AL=0x29, AF=0 CF=1 + ( 0x2f, 0x10 ), # AL=0x29, AF=1 CF=0 + ( 0x8f, 0x91 ), # AL=0x29, AF=1 CF=1 + ( 0x30, 0x14 ), # AL=0x2a, AF=0 CF=0 + ( 0x90, 0x95 ), # AL=0x2a, AF=0 CF=1 + ( 0x30, 0x14 ), # AL=0x2a, AF=1 CF=0 + ( 0x90, 0x95 ), # AL=0x2a, AF=1 CF=1 + ( 0x31, 0x10 ), # AL=0x2b, AF=0 CF=0 + ( 0x91, 0x91 ), # AL=0x2b, AF=0 CF=1 + ( 0x31, 0x10 ), # AL=0x2b, AF=1 CF=0 + ( 0x91, 0x91 ), # AL=0x2b, AF=1 CF=1 + ( 0x32, 0x10 ), # AL=0x2c, AF=0 CF=0 + ( 0x92, 0x91 ), # AL=0x2c, AF=0 CF=1 + ( 0x32, 0x10 ), # AL=0x2c, AF=1 CF=0 + ( 0x92, 0x91 ), # AL=0x2c, AF=1 CF=1 + ( 0x33, 0x14 ), # AL=0x2d, AF=0 CF=0 + ( 0x93, 0x95 ), # AL=0x2d, AF=0 CF=1 + ( 0x33, 0x14 ), # AL=0x2d, AF=1 CF=0 + ( 0x93, 0x95 ), # AL=0x2d, AF=1 CF=1 + ( 0x34, 0x10 ), # AL=0x2e, AF=0 CF=0 + ( 0x94, 0x91 ), # AL=0x2e, AF=0 CF=1 + ( 0x34, 0x10 ), # AL=0x2e, AF=1 CF=0 + ( 0x94, 0x91 ), # AL=0x2e, AF=1 CF=1 + ( 0x35, 0x14 ), # AL=0x2f, AF=0 CF=0 + ( 0x95, 0x95 ), # AL=0x2f, AF=0 CF=1 + ( 0x35, 0x14 ), # AL=0x2f, AF=1 CF=0 + ( 0x95, 0x95 ), # AL=0x2f, AF=1 CF=1 + ( 0x30, 0x04 ), # AL=0x30, AF=0 CF=0 + ( 0x90, 0x85 ), # AL=0x30, AF=0 CF=1 + ( 0x36, 0x14 ), # AL=0x30, AF=1 CF=0 + ( 0x96, 0x95 ), # AL=0x30, AF=1 CF=1 + ( 0x31, 0x00 ), # AL=0x31, AF=0 CF=0 + ( 0x91, 0x81 ), # AL=0x31, AF=0 CF=1 + ( 0x37, 0x10 ), # AL=0x31, AF=1 CF=0 + ( 0x97, 0x91 ), # AL=0x31, AF=1 CF=1 + ( 0x32, 0x00 ), # AL=0x32, AF=0 CF=0 + ( 0x92, 0x81 ), # AL=0x32, AF=0 CF=1 + ( 0x38, 0x10 ), # AL=0x32, AF=1 CF=0 + ( 0x98, 0x91 ), # AL=0x32, AF=1 CF=1 + ( 0x33, 0x04 ), # AL=0x33, AF=0 CF=0 + ( 0x93, 0x85 ), # AL=0x33, AF=0 CF=1 + ( 0x39, 0x14 ), # AL=0x33, AF=1 CF=0 + ( 0x99, 0x95 ), # AL=0x33, AF=1 CF=1 + ( 0x34, 0x00 ), # AL=0x34, AF=0 CF=0 + ( 0x94, 0x81 ), # AL=0x34, AF=0 CF=1 + ( 0x3a, 0x14 ), # AL=0x34, AF=1 CF=0 + ( 0x9a, 0x95 ), # AL=0x34, AF=1 CF=1 + ( 0x35, 0x04 ), # AL=0x35, AF=0 CF=0 + ( 0x95, 0x85 ), # AL=0x35, AF=0 CF=1 + ( 0x3b, 0x10 ), # AL=0x35, AF=1 CF=0 + ( 0x9b, 0x91 ), # AL=0x35, AF=1 CF=1 + ( 0x36, 0x04 ), # AL=0x36, AF=0 CF=0 + ( 0x96, 0x85 ), # AL=0x36, AF=0 CF=1 + ( 0x3c, 0x14 ), # AL=0x36, AF=1 CF=0 + ( 0x9c, 0x95 ), # AL=0x36, AF=1 CF=1 + ( 0x37, 0x00 ), # AL=0x37, AF=0 CF=0 + ( 0x97, 0x81 ), # AL=0x37, AF=0 CF=1 + ( 0x3d, 0x10 ), # AL=0x37, AF=1 CF=0 + ( 0x9d, 0x91 ), # AL=0x37, AF=1 CF=1 + ( 0x38, 0x00 ), # AL=0x38, AF=0 CF=0 + ( 0x98, 0x81 ), # AL=0x38, AF=0 CF=1 + ( 0x3e, 0x10 ), # AL=0x38, AF=1 CF=0 + ( 0x9e, 0x91 ), # AL=0x38, AF=1 CF=1 + ( 0x39, 0x04 ), # AL=0x39, AF=0 CF=0 + ( 0x99, 0x85 ), # AL=0x39, AF=0 CF=1 + ( 0x3f, 0x14 ), # AL=0x39, AF=1 CF=0 + ( 0x9f, 0x95 ), # AL=0x39, AF=1 CF=1 + ( 0x40, 0x10 ), # AL=0x3a, AF=0 CF=0 + ( 0xa0, 0x95 ), # AL=0x3a, AF=0 CF=1 + ( 0x40, 0x10 ), # AL=0x3a, AF=1 CF=0 + ( 0xa0, 0x95 ), # AL=0x3a, AF=1 CF=1 + ( 0x41, 0x14 ), # AL=0x3b, AF=0 CF=0 + ( 0xa1, 0x91 ), # AL=0x3b, AF=0 CF=1 + ( 0x41, 0x14 ), # AL=0x3b, AF=1 CF=0 + ( 0xa1, 0x91 ), # AL=0x3b, AF=1 CF=1 + ( 0x42, 0x14 ), # AL=0x3c, AF=0 CF=0 + ( 0xa2, 0x91 ), # AL=0x3c, AF=0 CF=1 + ( 0x42, 0x14 ), # AL=0x3c, AF=1 CF=0 + ( 0xa2, 0x91 ), # AL=0x3c, AF=1 CF=1 + ( 0x43, 0x10 ), # AL=0x3d, AF=0 CF=0 + ( 0xa3, 0x95 ), # AL=0x3d, AF=0 CF=1 + ( 0x43, 0x10 ), # AL=0x3d, AF=1 CF=0 + ( 0xa3, 0x95 ), # AL=0x3d, AF=1 CF=1 + ( 0x44, 0x14 ), # AL=0x3e, AF=0 CF=0 + ( 0xa4, 0x91 ), # AL=0x3e, AF=0 CF=1 + ( 0x44, 0x14 ), # AL=0x3e, AF=1 CF=0 + ( 0xa4, 0x91 ), # AL=0x3e, AF=1 CF=1 + ( 0x45, 0x10 ), # AL=0x3f, AF=0 CF=0 + ( 0xa5, 0x95 ), # AL=0x3f, AF=0 CF=1 + ( 0x45, 0x10 ), # AL=0x3f, AF=1 CF=0 + ( 0xa5, 0x95 ), # AL=0x3f, AF=1 CF=1 + ( 0x40, 0x00 ), # AL=0x40, AF=0 CF=0 + ( 0xa0, 0x85 ), # AL=0x40, AF=0 CF=1 + ( 0x46, 0x10 ), # AL=0x40, AF=1 CF=0 + ( 0xa6, 0x95 ), # AL=0x40, AF=1 CF=1 + ( 0x41, 0x04 ), # AL=0x41, AF=0 CF=0 + ( 0xa1, 0x81 ), # AL=0x41, AF=0 CF=1 + ( 0x47, 0x14 ), # AL=0x41, AF=1 CF=0 + ( 0xa7, 0x91 ), # AL=0x41, AF=1 CF=1 + ( 0x42, 0x04 ), # AL=0x42, AF=0 CF=0 + ( 0xa2, 0x81 ), # AL=0x42, AF=0 CF=1 + ( 0x48, 0x14 ), # AL=0x42, AF=1 CF=0 + ( 0xa8, 0x91 ), # AL=0x42, AF=1 CF=1 + ( 0x43, 0x00 ), # AL=0x43, AF=0 CF=0 + ( 0xa3, 0x85 ), # AL=0x43, AF=0 CF=1 + ( 0x49, 0x10 ), # AL=0x43, AF=1 CF=0 + ( 0xa9, 0x95 ), # AL=0x43, AF=1 CF=1 + ( 0x44, 0x04 ), # AL=0x44, AF=0 CF=0 + ( 0xa4, 0x81 ), # AL=0x44, AF=0 CF=1 + ( 0x4a, 0x10 ), # AL=0x44, AF=1 CF=0 + ( 0xaa, 0x95 ), # AL=0x44, AF=1 CF=1 + ( 0x45, 0x00 ), # AL=0x45, AF=0 CF=0 + ( 0xa5, 0x85 ), # AL=0x45, AF=0 CF=1 + ( 0x4b, 0x14 ), # AL=0x45, AF=1 CF=0 + ( 0xab, 0x91 ), # AL=0x45, AF=1 CF=1 + ( 0x46, 0x00 ), # AL=0x46, AF=0 CF=0 + ( 0xa6, 0x85 ), # AL=0x46, AF=0 CF=1 + ( 0x4c, 0x10 ), # AL=0x46, AF=1 CF=0 + ( 0xac, 0x95 ), # AL=0x46, AF=1 CF=1 + ( 0x47, 0x04 ), # AL=0x47, AF=0 CF=0 + ( 0xa7, 0x81 ), # AL=0x47, AF=0 CF=1 + ( 0x4d, 0x14 ), # AL=0x47, AF=1 CF=0 + ( 0xad, 0x91 ), # AL=0x47, AF=1 CF=1 + ( 0x48, 0x04 ), # AL=0x48, AF=0 CF=0 + ( 0xa8, 0x81 ), # AL=0x48, AF=0 CF=1 + ( 0x4e, 0x14 ), # AL=0x48, AF=1 CF=0 + ( 0xae, 0x91 ), # AL=0x48, AF=1 CF=1 + ( 0x49, 0x00 ), # AL=0x49, AF=0 CF=0 + ( 0xa9, 0x85 ), # AL=0x49, AF=0 CF=1 + ( 0x4f, 0x10 ), # AL=0x49, AF=1 CF=0 + ( 0xaf, 0x95 ), # AL=0x49, AF=1 CF=1 + ( 0x50, 0x14 ), # AL=0x4a, AF=0 CF=0 + ( 0xb0, 0x91 ), # AL=0x4a, AF=0 CF=1 + ( 0x50, 0x14 ), # AL=0x4a, AF=1 CF=0 + ( 0xb0, 0x91 ), # AL=0x4a, AF=1 CF=1 + ( 0x51, 0x10 ), # AL=0x4b, AF=0 CF=0 + ( 0xb1, 0x95 ), # AL=0x4b, AF=0 CF=1 + ( 0x51, 0x10 ), # AL=0x4b, AF=1 CF=0 + ( 0xb1, 0x95 ), # AL=0x4b, AF=1 CF=1 + ( 0x52, 0x10 ), # AL=0x4c, AF=0 CF=0 + ( 0xb2, 0x95 ), # AL=0x4c, AF=0 CF=1 + ( 0x52, 0x10 ), # AL=0x4c, AF=1 CF=0 + ( 0xb2, 0x95 ), # AL=0x4c, AF=1 CF=1 + ( 0x53, 0x14 ), # AL=0x4d, AF=0 CF=0 + ( 0xb3, 0x91 ), # AL=0x4d, AF=0 CF=1 + ( 0x53, 0x14 ), # AL=0x4d, AF=1 CF=0 + ( 0xb3, 0x91 ), # AL=0x4d, AF=1 CF=1 + ( 0x54, 0x10 ), # AL=0x4e, AF=0 CF=0 + ( 0xb4, 0x95 ), # AL=0x4e, AF=0 CF=1 + ( 0x54, 0x10 ), # AL=0x4e, AF=1 CF=0 + ( 0xb4, 0x95 ), # AL=0x4e, AF=1 CF=1 + ( 0x55, 0x14 ), # AL=0x4f, AF=0 CF=0 + ( 0xb5, 0x91 ), # AL=0x4f, AF=0 CF=1 + ( 0x55, 0x14 ), # AL=0x4f, AF=1 CF=0 + ( 0xb5, 0x91 ), # AL=0x4f, AF=1 CF=1 + ( 0x50, 0x04 ), # AL=0x50, AF=0 CF=0 + ( 0xb0, 0x81 ), # AL=0x50, AF=0 CF=1 + ( 0x56, 0x14 ), # AL=0x50, AF=1 CF=0 + ( 0xb6, 0x91 ), # AL=0x50, AF=1 CF=1 + ( 0x51, 0x00 ), # AL=0x51, AF=0 CF=0 + ( 0xb1, 0x85 ), # AL=0x51, AF=0 CF=1 + ( 0x57, 0x10 ), # AL=0x51, AF=1 CF=0 + ( 0xb7, 0x95 ), # AL=0x51, AF=1 CF=1 + ( 0x52, 0x00 ), # AL=0x52, AF=0 CF=0 + ( 0xb2, 0x85 ), # AL=0x52, AF=0 CF=1 + ( 0x58, 0x10 ), # AL=0x52, AF=1 CF=0 + ( 0xb8, 0x95 ), # AL=0x52, AF=1 CF=1 + ( 0x53, 0x04 ), # AL=0x53, AF=0 CF=0 + ( 0xb3, 0x81 ), # AL=0x53, AF=0 CF=1 + ( 0x59, 0x14 ), # AL=0x53, AF=1 CF=0 + ( 0xb9, 0x91 ), # AL=0x53, AF=1 CF=1 + ( 0x54, 0x00 ), # AL=0x54, AF=0 CF=0 + ( 0xb4, 0x85 ), # AL=0x54, AF=0 CF=1 + ( 0x5a, 0x14 ), # AL=0x54, AF=1 CF=0 + ( 0xba, 0x91 ), # AL=0x54, AF=1 CF=1 + ( 0x55, 0x04 ), # AL=0x55, AF=0 CF=0 + ( 0xb5, 0x81 ), # AL=0x55, AF=0 CF=1 + ( 0x5b, 0x10 ), # AL=0x55, AF=1 CF=0 + ( 0xbb, 0x95 ), # AL=0x55, AF=1 CF=1 + ( 0x56, 0x04 ), # AL=0x56, AF=0 CF=0 + ( 0xb6, 0x81 ), # AL=0x56, AF=0 CF=1 + ( 0x5c, 0x14 ), # AL=0x56, AF=1 CF=0 + ( 0xbc, 0x91 ), # AL=0x56, AF=1 CF=1 + ( 0x57, 0x00 ), # AL=0x57, AF=0 CF=0 + ( 0xb7, 0x85 ), # AL=0x57, AF=0 CF=1 + ( 0x5d, 0x10 ), # AL=0x57, AF=1 CF=0 + ( 0xbd, 0x95 ), # AL=0x57, AF=1 CF=1 + ( 0x58, 0x00 ), # AL=0x58, AF=0 CF=0 + ( 0xb8, 0x85 ), # AL=0x58, AF=0 CF=1 + ( 0x5e, 0x10 ), # AL=0x58, AF=1 CF=0 + ( 0xbe, 0x95 ), # AL=0x58, AF=1 CF=1 + ( 0x59, 0x04 ), # AL=0x59, AF=0 CF=0 + ( 0xb9, 0x81 ), # AL=0x59, AF=0 CF=1 + ( 0x5f, 0x14 ), # AL=0x59, AF=1 CF=0 + ( 0xbf, 0x91 ), # AL=0x59, AF=1 CF=1 + ( 0x60, 0x14 ), # AL=0x5a, AF=0 CF=0 + ( 0xc0, 0x95 ), # AL=0x5a, AF=0 CF=1 + ( 0x60, 0x14 ), # AL=0x5a, AF=1 CF=0 + ( 0xc0, 0x95 ), # AL=0x5a, AF=1 CF=1 + ( 0x61, 0x10 ), # AL=0x5b, AF=0 CF=0 + ( 0xc1, 0x91 ), # AL=0x5b, AF=0 CF=1 + ( 0x61, 0x10 ), # AL=0x5b, AF=1 CF=0 + ( 0xc1, 0x91 ), # AL=0x5b, AF=1 CF=1 + ( 0x62, 0x10 ), # AL=0x5c, AF=0 CF=0 + ( 0xc2, 0x91 ), # AL=0x5c, AF=0 CF=1 + ( 0x62, 0x10 ), # AL=0x5c, AF=1 CF=0 + ( 0xc2, 0x91 ), # AL=0x5c, AF=1 CF=1 + ( 0x63, 0x14 ), # AL=0x5d, AF=0 CF=0 + ( 0xc3, 0x95 ), # AL=0x5d, AF=0 CF=1 + ( 0x63, 0x14 ), # AL=0x5d, AF=1 CF=0 + ( 0xc3, 0x95 ), # AL=0x5d, AF=1 CF=1 + ( 0x64, 0x10 ), # AL=0x5e, AF=0 CF=0 + ( 0xc4, 0x91 ), # AL=0x5e, AF=0 CF=1 + ( 0x64, 0x10 ), # AL=0x5e, AF=1 CF=0 + ( 0xc4, 0x91 ), # AL=0x5e, AF=1 CF=1 + ( 0x65, 0x14 ), # AL=0x5f, AF=0 CF=0 + ( 0xc5, 0x95 ), # AL=0x5f, AF=0 CF=1 + ( 0x65, 0x14 ), # AL=0x5f, AF=1 CF=0 + ( 0xc5, 0x95 ), # AL=0x5f, AF=1 CF=1 + ( 0x60, 0x04 ), # AL=0x60, AF=0 CF=0 + ( 0xc0, 0x85 ), # AL=0x60, AF=0 CF=1 + ( 0x66, 0x14 ), # AL=0x60, AF=1 CF=0 + ( 0xc6, 0x95 ), # AL=0x60, AF=1 CF=1 + ( 0x61, 0x00 ), # AL=0x61, AF=0 CF=0 + ( 0xc1, 0x81 ), # AL=0x61, AF=0 CF=1 + ( 0x67, 0x10 ), # AL=0x61, AF=1 CF=0 + ( 0xc7, 0x91 ), # AL=0x61, AF=1 CF=1 + ( 0x62, 0x00 ), # AL=0x62, AF=0 CF=0 + ( 0xc2, 0x81 ), # AL=0x62, AF=0 CF=1 + ( 0x68, 0x10 ), # AL=0x62, AF=1 CF=0 + ( 0xc8, 0x91 ), # AL=0x62, AF=1 CF=1 + ( 0x63, 0x04 ), # AL=0x63, AF=0 CF=0 + ( 0xc3, 0x85 ), # AL=0x63, AF=0 CF=1 + ( 0x69, 0x14 ), # AL=0x63, AF=1 CF=0 + ( 0xc9, 0x95 ), # AL=0x63, AF=1 CF=1 + ( 0x64, 0x00 ), # AL=0x64, AF=0 CF=0 + ( 0xc4, 0x81 ), # AL=0x64, AF=0 CF=1 + ( 0x6a, 0x14 ), # AL=0x64, AF=1 CF=0 + ( 0xca, 0x95 ), # AL=0x64, AF=1 CF=1 + ( 0x65, 0x04 ), # AL=0x65, AF=0 CF=0 + ( 0xc5, 0x85 ), # AL=0x65, AF=0 CF=1 + ( 0x6b, 0x10 ), # AL=0x65, AF=1 CF=0 + ( 0xcb, 0x91 ), # AL=0x65, AF=1 CF=1 + ( 0x66, 0x04 ), # AL=0x66, AF=0 CF=0 + ( 0xc6, 0x85 ), # AL=0x66, AF=0 CF=1 + ( 0x6c, 0x14 ), # AL=0x66, AF=1 CF=0 + ( 0xcc, 0x95 ), # AL=0x66, AF=1 CF=1 + ( 0x67, 0x00 ), # AL=0x67, AF=0 CF=0 + ( 0xc7, 0x81 ), # AL=0x67, AF=0 CF=1 + ( 0x6d, 0x10 ), # AL=0x67, AF=1 CF=0 + ( 0xcd, 0x91 ), # AL=0x67, AF=1 CF=1 + ( 0x68, 0x00 ), # AL=0x68, AF=0 CF=0 + ( 0xc8, 0x81 ), # AL=0x68, AF=0 CF=1 + ( 0x6e, 0x10 ), # AL=0x68, AF=1 CF=0 + ( 0xce, 0x91 ), # AL=0x68, AF=1 CF=1 + ( 0x69, 0x04 ), # AL=0x69, AF=0 CF=0 + ( 0xc9, 0x85 ), # AL=0x69, AF=0 CF=1 + ( 0x6f, 0x14 ), # AL=0x69, AF=1 CF=0 + ( 0xcf, 0x95 ), # AL=0x69, AF=1 CF=1 + ( 0x70, 0x10 ), # AL=0x6a, AF=0 CF=0 + ( 0xd0, 0x91 ), # AL=0x6a, AF=0 CF=1 + ( 0x70, 0x10 ), # AL=0x6a, AF=1 CF=0 + ( 0xd0, 0x91 ), # AL=0x6a, AF=1 CF=1 + ( 0x71, 0x14 ), # AL=0x6b, AF=0 CF=0 + ( 0xd1, 0x95 ), # AL=0x6b, AF=0 CF=1 + ( 0x71, 0x14 ), # AL=0x6b, AF=1 CF=0 + ( 0xd1, 0x95 ), # AL=0x6b, AF=1 CF=1 + ( 0x72, 0x14 ), # AL=0x6c, AF=0 CF=0 + ( 0xd2, 0x95 ), # AL=0x6c, AF=0 CF=1 + ( 0x72, 0x14 ), # AL=0x6c, AF=1 CF=0 + ( 0xd2, 0x95 ), # AL=0x6c, AF=1 CF=1 + ( 0x73, 0x10 ), # AL=0x6d, AF=0 CF=0 + ( 0xd3, 0x91 ), # AL=0x6d, AF=0 CF=1 + ( 0x73, 0x10 ), # AL=0x6d, AF=1 CF=0 + ( 0xd3, 0x91 ), # AL=0x6d, AF=1 CF=1 + ( 0x74, 0x14 ), # AL=0x6e, AF=0 CF=0 + ( 0xd4, 0x95 ), # AL=0x6e, AF=0 CF=1 + ( 0x74, 0x14 ), # AL=0x6e, AF=1 CF=0 + ( 0xd4, 0x95 ), # AL=0x6e, AF=1 CF=1 + ( 0x75, 0x10 ), # AL=0x6f, AF=0 CF=0 + ( 0xd5, 0x91 ), # AL=0x6f, AF=0 CF=1 + ( 0x75, 0x10 ), # AL=0x6f, AF=1 CF=0 + ( 0xd5, 0x91 ), # AL=0x6f, AF=1 CF=1 + ( 0x70, 0x00 ), # AL=0x70, AF=0 CF=0 + ( 0xd0, 0x81 ), # AL=0x70, AF=0 CF=1 + ( 0x76, 0x10 ), # AL=0x70, AF=1 CF=0 + ( 0xd6, 0x91 ), # AL=0x70, AF=1 CF=1 + ( 0x71, 0x04 ), # AL=0x71, AF=0 CF=0 + ( 0xd1, 0x85 ), # AL=0x71, AF=0 CF=1 + ( 0x77, 0x14 ), # AL=0x71, AF=1 CF=0 + ( 0xd7, 0x95 ), # AL=0x71, AF=1 CF=1 + ( 0x72, 0x04 ), # AL=0x72, AF=0 CF=0 + ( 0xd2, 0x85 ), # AL=0x72, AF=0 CF=1 + ( 0x78, 0x14 ), # AL=0x72, AF=1 CF=0 + ( 0xd8, 0x95 ), # AL=0x72, AF=1 CF=1 + ( 0x73, 0x00 ), # AL=0x73, AF=0 CF=0 + ( 0xd3, 0x81 ), # AL=0x73, AF=0 CF=1 + ( 0x79, 0x10 ), # AL=0x73, AF=1 CF=0 + ( 0xd9, 0x91 ), # AL=0x73, AF=1 CF=1 + ( 0x74, 0x04 ), # AL=0x74, AF=0 CF=0 + ( 0xd4, 0x85 ), # AL=0x74, AF=0 CF=1 + ( 0x7a, 0x10 ), # AL=0x74, AF=1 CF=0 + ( 0xda, 0x91 ), # AL=0x74, AF=1 CF=1 + ( 0x75, 0x00 ), # AL=0x75, AF=0 CF=0 + ( 0xd5, 0x81 ), # AL=0x75, AF=0 CF=1 + ( 0x7b, 0x14 ), # AL=0x75, AF=1 CF=0 + ( 0xdb, 0x95 ), # AL=0x75, AF=1 CF=1 + ( 0x76, 0x00 ), # AL=0x76, AF=0 CF=0 + ( 0xd6, 0x81 ), # AL=0x76, AF=0 CF=1 + ( 0x7c, 0x10 ), # AL=0x76, AF=1 CF=0 + ( 0xdc, 0x91 ), # AL=0x76, AF=1 CF=1 + ( 0x77, 0x04 ), # AL=0x77, AF=0 CF=0 + ( 0xd7, 0x85 ), # AL=0x77, AF=0 CF=1 + ( 0x7d, 0x14 ), # AL=0x77, AF=1 CF=0 + ( 0xdd, 0x95 ), # AL=0x77, AF=1 CF=1 + ( 0x78, 0x04 ), # AL=0x78, AF=0 CF=0 + ( 0xd8, 0x85 ), # AL=0x78, AF=0 CF=1 + ( 0x7e, 0x14 ), # AL=0x78, AF=1 CF=0 + ( 0xde, 0x95 ), # AL=0x78, AF=1 CF=1 + ( 0x79, 0x00 ), # AL=0x79, AF=0 CF=0 + ( 0xd9, 0x81 ), # AL=0x79, AF=0 CF=1 + ( 0x7f, 0x10 ), # AL=0x79, AF=1 CF=0 + ( 0xdf, 0x91 ), # AL=0x79, AF=1 CF=1 + ( 0x80, 0x90 ), # AL=0x7a, AF=0 CF=0 + ( 0xe0, 0x91 ), # AL=0x7a, AF=0 CF=1 + ( 0x80, 0x90 ), # AL=0x7a, AF=1 CF=0 + ( 0xe0, 0x91 ), # AL=0x7a, AF=1 CF=1 + ( 0x81, 0x94 ), # AL=0x7b, AF=0 CF=0 + ( 0xe1, 0x95 ), # AL=0x7b, AF=0 CF=1 + ( 0x81, 0x94 ), # AL=0x7b, AF=1 CF=0 + ( 0xe1, 0x95 ), # AL=0x7b, AF=1 CF=1 + ( 0x82, 0x94 ), # AL=0x7c, AF=0 CF=0 + ( 0xe2, 0x95 ), # AL=0x7c, AF=0 CF=1 + ( 0x82, 0x94 ), # AL=0x7c, AF=1 CF=0 + ( 0xe2, 0x95 ), # AL=0x7c, AF=1 CF=1 + ( 0x83, 0x90 ), # AL=0x7d, AF=0 CF=0 + ( 0xe3, 0x91 ), # AL=0x7d, AF=0 CF=1 + ( 0x83, 0x90 ), # AL=0x7d, AF=1 CF=0 + ( 0xe3, 0x91 ), # AL=0x7d, AF=1 CF=1 + ( 0x84, 0x94 ), # AL=0x7e, AF=0 CF=0 + ( 0xe4, 0x95 ), # AL=0x7e, AF=0 CF=1 + ( 0x84, 0x94 ), # AL=0x7e, AF=1 CF=0 + ( 0xe4, 0x95 ), # AL=0x7e, AF=1 CF=1 + ( 0x85, 0x90 ), # AL=0x7f, AF=0 CF=0 + ( 0xe5, 0x91 ), # AL=0x7f, AF=0 CF=1 + ( 0x85, 0x90 ), # AL=0x7f, AF=1 CF=0 + ( 0xe5, 0x91 ), # AL=0x7f, AF=1 CF=1 + ( 0x80, 0x80 ), # AL=0x80, AF=0 CF=0 + ( 0xe0, 0x81 ), # AL=0x80, AF=0 CF=1 + ( 0x86, 0x90 ), # AL=0x80, AF=1 CF=0 + ( 0xe6, 0x91 ), # AL=0x80, AF=1 CF=1 + ( 0x81, 0x84 ), # AL=0x81, AF=0 CF=0 + ( 0xe1, 0x85 ), # AL=0x81, AF=0 CF=1 + ( 0x87, 0x94 ), # AL=0x81, AF=1 CF=0 + ( 0xe7, 0x95 ), # AL=0x81, AF=1 CF=1 + ( 0x82, 0x84 ), # AL=0x82, AF=0 CF=0 + ( 0xe2, 0x85 ), # AL=0x82, AF=0 CF=1 + ( 0x88, 0x94 ), # AL=0x82, AF=1 CF=0 + ( 0xe8, 0x95 ), # AL=0x82, AF=1 CF=1 + ( 0x83, 0x80 ), # AL=0x83, AF=0 CF=0 + ( 0xe3, 0x81 ), # AL=0x83, AF=0 CF=1 + ( 0x89, 0x90 ), # AL=0x83, AF=1 CF=0 + ( 0xe9, 0x91 ), # AL=0x83, AF=1 CF=1 + ( 0x84, 0x84 ), # AL=0x84, AF=0 CF=0 + ( 0xe4, 0x85 ), # AL=0x84, AF=0 CF=1 + ( 0x8a, 0x90 ), # AL=0x84, AF=1 CF=0 + ( 0xea, 0x91 ), # AL=0x84, AF=1 CF=1 + ( 0x85, 0x80 ), # AL=0x85, AF=0 CF=0 + ( 0xe5, 0x81 ), # AL=0x85, AF=0 CF=1 + ( 0x8b, 0x94 ), # AL=0x85, AF=1 CF=0 + ( 0xeb, 0x95 ), # AL=0x85, AF=1 CF=1 + ( 0x86, 0x80 ), # AL=0x86, AF=0 CF=0 + ( 0xe6, 0x81 ), # AL=0x86, AF=0 CF=1 + ( 0x8c, 0x90 ), # AL=0x86, AF=1 CF=0 + ( 0xec, 0x91 ), # AL=0x86, AF=1 CF=1 + ( 0x87, 0x84 ), # AL=0x87, AF=0 CF=0 + ( 0xe7, 0x85 ), # AL=0x87, AF=0 CF=1 + ( 0x8d, 0x94 ), # AL=0x87, AF=1 CF=0 + ( 0xed, 0x95 ), # AL=0x87, AF=1 CF=1 + ( 0x88, 0x84 ), # AL=0x88, AF=0 CF=0 + ( 0xe8, 0x85 ), # AL=0x88, AF=0 CF=1 + ( 0x8e, 0x94 ), # AL=0x88, AF=1 CF=0 + ( 0xee, 0x95 ), # AL=0x88, AF=1 CF=1 + ( 0x89, 0x80 ), # AL=0x89, AF=0 CF=0 + ( 0xe9, 0x81 ), # AL=0x89, AF=0 CF=1 + ( 0x8f, 0x90 ), # AL=0x89, AF=1 CF=0 + ( 0xef, 0x91 ), # AL=0x89, AF=1 CF=1 + ( 0x90, 0x94 ), # AL=0x8a, AF=0 CF=0 + ( 0xf0, 0x95 ), # AL=0x8a, AF=0 CF=1 + ( 0x90, 0x94 ), # AL=0x8a, AF=1 CF=0 + ( 0xf0, 0x95 ), # AL=0x8a, AF=1 CF=1 + ( 0x91, 0x90 ), # AL=0x8b, AF=0 CF=0 + ( 0xf1, 0x91 ), # AL=0x8b, AF=0 CF=1 + ( 0x91, 0x90 ), # AL=0x8b, AF=1 CF=0 + ( 0xf1, 0x91 ), # AL=0x8b, AF=1 CF=1 + ( 0x92, 0x90 ), # AL=0x8c, AF=0 CF=0 + ( 0xf2, 0x91 ), # AL=0x8c, AF=0 CF=1 + ( 0x92, 0x90 ), # AL=0x8c, AF=1 CF=0 + ( 0xf2, 0x91 ), # AL=0x8c, AF=1 CF=1 + ( 0x93, 0x94 ), # AL=0x8d, AF=0 CF=0 + ( 0xf3, 0x95 ), # AL=0x8d, AF=0 CF=1 + ( 0x93, 0x94 ), # AL=0x8d, AF=1 CF=0 + ( 0xf3, 0x95 ), # AL=0x8d, AF=1 CF=1 + ( 0x94, 0x90 ), # AL=0x8e, AF=0 CF=0 + ( 0xf4, 0x91 ), # AL=0x8e, AF=0 CF=1 + ( 0x94, 0x90 ), # AL=0x8e, AF=1 CF=0 + ( 0xf4, 0x91 ), # AL=0x8e, AF=1 CF=1 + ( 0x95, 0x94 ), # AL=0x8f, AF=0 CF=0 + ( 0xf5, 0x95 ), # AL=0x8f, AF=0 CF=1 + ( 0x95, 0x94 ), # AL=0x8f, AF=1 CF=0 + ( 0xf5, 0x95 ), # AL=0x8f, AF=1 CF=1 + ( 0x90, 0x84 ), # AL=0x90, AF=0 CF=0 + ( 0xf0, 0x85 ), # AL=0x90, AF=0 CF=1 + ( 0x96, 0x94 ), # AL=0x90, AF=1 CF=0 + ( 0xf6, 0x95 ), # AL=0x90, AF=1 CF=1 + ( 0x91, 0x80 ), # AL=0x91, AF=0 CF=0 + ( 0xf1, 0x81 ), # AL=0x91, AF=0 CF=1 + ( 0x97, 0x90 ), # AL=0x91, AF=1 CF=0 + ( 0xf7, 0x91 ), # AL=0x91, AF=1 CF=1 + ( 0x92, 0x80 ), # AL=0x92, AF=0 CF=0 + ( 0xf2, 0x81 ), # AL=0x92, AF=0 CF=1 + ( 0x98, 0x90 ), # AL=0x92, AF=1 CF=0 + ( 0xf8, 0x91 ), # AL=0x92, AF=1 CF=1 + ( 0x93, 0x84 ), # AL=0x93, AF=0 CF=0 + ( 0xf3, 0x85 ), # AL=0x93, AF=0 CF=1 + ( 0x99, 0x94 ), # AL=0x93, AF=1 CF=0 + ( 0xf9, 0x95 ), # AL=0x93, AF=1 CF=1 + ( 0x94, 0x80 ), # AL=0x94, AF=0 CF=0 + ( 0xf4, 0x81 ), # AL=0x94, AF=0 CF=1 + ( 0x9a, 0x94 ), # AL=0x94, AF=1 CF=0 + ( 0xfa, 0x95 ), # AL=0x94, AF=1 CF=1 + ( 0x95, 0x84 ), # AL=0x95, AF=0 CF=0 + ( 0xf5, 0x85 ), # AL=0x95, AF=0 CF=1 + ( 0x9b, 0x90 ), # AL=0x95, AF=1 CF=0 + ( 0xfb, 0x91 ), # AL=0x95, AF=1 CF=1 + ( 0x96, 0x84 ), # AL=0x96, AF=0 CF=0 + ( 0xf6, 0x85 ), # AL=0x96, AF=0 CF=1 + ( 0x9c, 0x94 ), # AL=0x96, AF=1 CF=0 + ( 0xfc, 0x95 ), # AL=0x96, AF=1 CF=1 + ( 0x97, 0x80 ), # AL=0x97, AF=0 CF=0 + ( 0xf7, 0x81 ), # AL=0x97, AF=0 CF=1 + ( 0x9d, 0x90 ), # AL=0x97, AF=1 CF=0 + ( 0xfd, 0x91 ), # AL=0x97, AF=1 CF=1 + ( 0x98, 0x80 ), # AL=0x98, AF=0 CF=0 + ( 0xf8, 0x81 ), # AL=0x98, AF=0 CF=1 + ( 0x9e, 0x90 ), # AL=0x98, AF=1 CF=0 + ( 0xfe, 0x91 ), # AL=0x98, AF=1 CF=1 + ( 0x99, 0x84 ), # AL=0x99, AF=0 CF=0 + ( 0xf9, 0x85 ), # AL=0x99, AF=0 CF=1 + ( 0x9f, 0x94 ), # AL=0x99, AF=1 CF=0 + ( 0xff, 0x95 ), # AL=0x99, AF=1 CF=1 + ( 0x00, 0x55 ), # AL=0x9a, AF=0 CF=0 + ( 0x00, 0x55 ), # AL=0x9a, AF=0 CF=1 + ( 0x00, 0x55 ), # AL=0x9a, AF=1 CF=0 + ( 0x00, 0x55 ), # AL=0x9a, AF=1 CF=1 + ( 0x01, 0x11 ), # AL=0x9b, AF=0 CF=0 + ( 0x01, 0x11 ), # AL=0x9b, AF=0 CF=1 + ( 0x01, 0x11 ), # AL=0x9b, AF=1 CF=0 + ( 0x01, 0x11 ), # AL=0x9b, AF=1 CF=1 + ( 0x02, 0x11 ), # AL=0x9c, AF=0 CF=0 + ( 0x02, 0x11 ), # AL=0x9c, AF=0 CF=1 + ( 0x02, 0x11 ), # AL=0x9c, AF=1 CF=0 + ( 0x02, 0x11 ), # AL=0x9c, AF=1 CF=1 + ( 0x03, 0x15 ), # AL=0x9d, AF=0 CF=0 + ( 0x03, 0x15 ), # AL=0x9d, AF=0 CF=1 + ( 0x03, 0x15 ), # AL=0x9d, AF=1 CF=0 + ( 0x03, 0x15 ), # AL=0x9d, AF=1 CF=1 + ( 0x04, 0x11 ), # AL=0x9e, AF=0 CF=0 + ( 0x04, 0x11 ), # AL=0x9e, AF=0 CF=1 + ( 0x04, 0x11 ), # AL=0x9e, AF=1 CF=0 + ( 0x04, 0x11 ), # AL=0x9e, AF=1 CF=1 + ( 0x05, 0x15 ), # AL=0x9f, AF=0 CF=0 + ( 0x05, 0x15 ), # AL=0x9f, AF=0 CF=1 + ( 0x05, 0x15 ), # AL=0x9f, AF=1 CF=0 + ( 0x05, 0x15 ), # AL=0x9f, AF=1 CF=1 + ( 0x00, 0x45 ), # AL=0xa0, AF=0 CF=0 + ( 0x00, 0x45 ), # AL=0xa0, AF=0 CF=1 + ( 0x06, 0x15 ), # AL=0xa0, AF=1 CF=0 + ( 0x06, 0x15 ), # AL=0xa0, AF=1 CF=1 + ( 0x01, 0x01 ), # AL=0xa1, AF=0 CF=0 + ( 0x01, 0x01 ), # AL=0xa1, AF=0 CF=1 + ( 0x07, 0x11 ), # AL=0xa1, AF=1 CF=0 + ( 0x07, 0x11 ), # AL=0xa1, AF=1 CF=1 + ( 0x02, 0x01 ), # AL=0xa2, AF=0 CF=0 + ( 0x02, 0x01 ), # AL=0xa2, AF=0 CF=1 + ( 0x08, 0x11 ), # AL=0xa2, AF=1 CF=0 + ( 0x08, 0x11 ), # AL=0xa2, AF=1 CF=1 + ( 0x03, 0x05 ), # AL=0xa3, AF=0 CF=0 + ( 0x03, 0x05 ), # AL=0xa3, AF=0 CF=1 + ( 0x09, 0x15 ), # AL=0xa3, AF=1 CF=0 + ( 0x09, 0x15 ), # AL=0xa3, AF=1 CF=1 + ( 0x04, 0x01 ), # AL=0xa4, AF=0 CF=0 + ( 0x04, 0x01 ), # AL=0xa4, AF=0 CF=1 + ( 0x0a, 0x15 ), # AL=0xa4, AF=1 CF=0 + ( 0x0a, 0x15 ), # AL=0xa4, AF=1 CF=1 + ( 0x05, 0x05 ), # AL=0xa5, AF=0 CF=0 + ( 0x05, 0x05 ), # AL=0xa5, AF=0 CF=1 + ( 0x0b, 0x11 ), # AL=0xa5, AF=1 CF=0 + ( 0x0b, 0x11 ), # AL=0xa5, AF=1 CF=1 + ( 0x06, 0x05 ), # AL=0xa6, AF=0 CF=0 + ( 0x06, 0x05 ), # AL=0xa6, AF=0 CF=1 + ( 0x0c, 0x15 ), # AL=0xa6, AF=1 CF=0 + ( 0x0c, 0x15 ), # AL=0xa6, AF=1 CF=1 + ( 0x07, 0x01 ), # AL=0xa7, AF=0 CF=0 + ( 0x07, 0x01 ), # AL=0xa7, AF=0 CF=1 + ( 0x0d, 0x11 ), # AL=0xa7, AF=1 CF=0 + ( 0x0d, 0x11 ), # AL=0xa7, AF=1 CF=1 + ( 0x08, 0x01 ), # AL=0xa8, AF=0 CF=0 + ( 0x08, 0x01 ), # AL=0xa8, AF=0 CF=1 + ( 0x0e, 0x11 ), # AL=0xa8, AF=1 CF=0 + ( 0x0e, 0x11 ), # AL=0xa8, AF=1 CF=1 + ( 0x09, 0x05 ), # AL=0xa9, AF=0 CF=0 + ( 0x09, 0x05 ), # AL=0xa9, AF=0 CF=1 + ( 0x0f, 0x15 ), # AL=0xa9, AF=1 CF=0 + ( 0x0f, 0x15 ), # AL=0xa9, AF=1 CF=1 + ( 0x10, 0x11 ), # AL=0xaa, AF=0 CF=0 + ( 0x10, 0x11 ), # AL=0xaa, AF=0 CF=1 + ( 0x10, 0x11 ), # AL=0xaa, AF=1 CF=0 + ( 0x10, 0x11 ), # AL=0xaa, AF=1 CF=1 + ( 0x11, 0x15 ), # AL=0xab, AF=0 CF=0 + ( 0x11, 0x15 ), # AL=0xab, AF=0 CF=1 + ( 0x11, 0x15 ), # AL=0xab, AF=1 CF=0 + ( 0x11, 0x15 ), # AL=0xab, AF=1 CF=1 + ( 0x12, 0x15 ), # AL=0xac, AF=0 CF=0 + ( 0x12, 0x15 ), # AL=0xac, AF=0 CF=1 + ( 0x12, 0x15 ), # AL=0xac, AF=1 CF=0 + ( 0x12, 0x15 ), # AL=0xac, AF=1 CF=1 + ( 0x13, 0x11 ), # AL=0xad, AF=0 CF=0 + ( 0x13, 0x11 ), # AL=0xad, AF=0 CF=1 + ( 0x13, 0x11 ), # AL=0xad, AF=1 CF=0 + ( 0x13, 0x11 ), # AL=0xad, AF=1 CF=1 + ( 0x14, 0x15 ), # AL=0xae, AF=0 CF=0 + ( 0x14, 0x15 ), # AL=0xae, AF=0 CF=1 + ( 0x14, 0x15 ), # AL=0xae, AF=1 CF=0 + ( 0x14, 0x15 ), # AL=0xae, AF=1 CF=1 + ( 0x15, 0x11 ), # AL=0xaf, AF=0 CF=0 + ( 0x15, 0x11 ), # AL=0xaf, AF=0 CF=1 + ( 0x15, 0x11 ), # AL=0xaf, AF=1 CF=0 + ( 0x15, 0x11 ), # AL=0xaf, AF=1 CF=1 + ( 0x10, 0x01 ), # AL=0xb0, AF=0 CF=0 + ( 0x10, 0x01 ), # AL=0xb0, AF=0 CF=1 + ( 0x16, 0x11 ), # AL=0xb0, AF=1 CF=0 + ( 0x16, 0x11 ), # AL=0xb0, AF=1 CF=1 + ( 0x11, 0x05 ), # AL=0xb1, AF=0 CF=0 + ( 0x11, 0x05 ), # AL=0xb1, AF=0 CF=1 + ( 0x17, 0x15 ), # AL=0xb1, AF=1 CF=0 + ( 0x17, 0x15 ), # AL=0xb1, AF=1 CF=1 + ( 0x12, 0x05 ), # AL=0xb2, AF=0 CF=0 + ( 0x12, 0x05 ), # AL=0xb2, AF=0 CF=1 + ( 0x18, 0x15 ), # AL=0xb2, AF=1 CF=0 + ( 0x18, 0x15 ), # AL=0xb2, AF=1 CF=1 + ( 0x13, 0x01 ), # AL=0xb3, AF=0 CF=0 + ( 0x13, 0x01 ), # AL=0xb3, AF=0 CF=1 + ( 0x19, 0x11 ), # AL=0xb3, AF=1 CF=0 + ( 0x19, 0x11 ), # AL=0xb3, AF=1 CF=1 + ( 0x14, 0x05 ), # AL=0xb4, AF=0 CF=0 + ( 0x14, 0x05 ), # AL=0xb4, AF=0 CF=1 + ( 0x1a, 0x11 ), # AL=0xb4, AF=1 CF=0 + ( 0x1a, 0x11 ), # AL=0xb4, AF=1 CF=1 + ( 0x15, 0x01 ), # AL=0xb5, AF=0 CF=0 + ( 0x15, 0x01 ), # AL=0xb5, AF=0 CF=1 + ( 0x1b, 0x15 ), # AL=0xb5, AF=1 CF=0 + ( 0x1b, 0x15 ), # AL=0xb5, AF=1 CF=1 + ( 0x16, 0x01 ), # AL=0xb6, AF=0 CF=0 + ( 0x16, 0x01 ), # AL=0xb6, AF=0 CF=1 + ( 0x1c, 0x11 ), # AL=0xb6, AF=1 CF=0 + ( 0x1c, 0x11 ), # AL=0xb6, AF=1 CF=1 + ( 0x17, 0x05 ), # AL=0xb7, AF=0 CF=0 + ( 0x17, 0x05 ), # AL=0xb7, AF=0 CF=1 + ( 0x1d, 0x15 ), # AL=0xb7, AF=1 CF=0 + ( 0x1d, 0x15 ), # AL=0xb7, AF=1 CF=1 + ( 0x18, 0x05 ), # AL=0xb8, AF=0 CF=0 + ( 0x18, 0x05 ), # AL=0xb8, AF=0 CF=1 + ( 0x1e, 0x15 ), # AL=0xb8, AF=1 CF=0 + ( 0x1e, 0x15 ), # AL=0xb8, AF=1 CF=1 + ( 0x19, 0x01 ), # AL=0xb9, AF=0 CF=0 + ( 0x19, 0x01 ), # AL=0xb9, AF=0 CF=1 + ( 0x1f, 0x11 ), # AL=0xb9, AF=1 CF=0 + ( 0x1f, 0x11 ), # AL=0xb9, AF=1 CF=1 + ( 0x20, 0x11 ), # AL=0xba, AF=0 CF=0 + ( 0x20, 0x11 ), # AL=0xba, AF=0 CF=1 + ( 0x20, 0x11 ), # AL=0xba, AF=1 CF=0 + ( 0x20, 0x11 ), # AL=0xba, AF=1 CF=1 + ( 0x21, 0x15 ), # AL=0xbb, AF=0 CF=0 + ( 0x21, 0x15 ), # AL=0xbb, AF=0 CF=1 + ( 0x21, 0x15 ), # AL=0xbb, AF=1 CF=0 + ( 0x21, 0x15 ), # AL=0xbb, AF=1 CF=1 + ( 0x22, 0x15 ), # AL=0xbc, AF=0 CF=0 + ( 0x22, 0x15 ), # AL=0xbc, AF=0 CF=1 + ( 0x22, 0x15 ), # AL=0xbc, AF=1 CF=0 + ( 0x22, 0x15 ), # AL=0xbc, AF=1 CF=1 + ( 0x23, 0x11 ), # AL=0xbd, AF=0 CF=0 + ( 0x23, 0x11 ), # AL=0xbd, AF=0 CF=1 + ( 0x23, 0x11 ), # AL=0xbd, AF=1 CF=0 + ( 0x23, 0x11 ), # AL=0xbd, AF=1 CF=1 + ( 0x24, 0x15 ), # AL=0xbe, AF=0 CF=0 + ( 0x24, 0x15 ), # AL=0xbe, AF=0 CF=1 + ( 0x24, 0x15 ), # AL=0xbe, AF=1 CF=0 + ( 0x24, 0x15 ), # AL=0xbe, AF=1 CF=1 + ( 0x25, 0x11 ), # AL=0xbf, AF=0 CF=0 + ( 0x25, 0x11 ), # AL=0xbf, AF=0 CF=1 + ( 0x25, 0x11 ), # AL=0xbf, AF=1 CF=0 + ( 0x25, 0x11 ), # AL=0xbf, AF=1 CF=1 + ( 0x20, 0x01 ), # AL=0xc0, AF=0 CF=0 + ( 0x20, 0x01 ), # AL=0xc0, AF=0 CF=1 + ( 0x26, 0x11 ), # AL=0xc0, AF=1 CF=0 + ( 0x26, 0x11 ), # AL=0xc0, AF=1 CF=1 + ( 0x21, 0x05 ), # AL=0xc1, AF=0 CF=0 + ( 0x21, 0x05 ), # AL=0xc1, AF=0 CF=1 + ( 0x27, 0x15 ), # AL=0xc1, AF=1 CF=0 + ( 0x27, 0x15 ), # AL=0xc1, AF=1 CF=1 + ( 0x22, 0x05 ), # AL=0xc2, AF=0 CF=0 + ( 0x22, 0x05 ), # AL=0xc2, AF=0 CF=1 + ( 0x28, 0x15 ), # AL=0xc2, AF=1 CF=0 + ( 0x28, 0x15 ), # AL=0xc2, AF=1 CF=1 + ( 0x23, 0x01 ), # AL=0xc3, AF=0 CF=0 + ( 0x23, 0x01 ), # AL=0xc3, AF=0 CF=1 + ( 0x29, 0x11 ), # AL=0xc3, AF=1 CF=0 + ( 0x29, 0x11 ), # AL=0xc3, AF=1 CF=1 + ( 0x24, 0x05 ), # AL=0xc4, AF=0 CF=0 + ( 0x24, 0x05 ), # AL=0xc4, AF=0 CF=1 + ( 0x2a, 0x11 ), # AL=0xc4, AF=1 CF=0 + ( 0x2a, 0x11 ), # AL=0xc4, AF=1 CF=1 + ( 0x25, 0x01 ), # AL=0xc5, AF=0 CF=0 + ( 0x25, 0x01 ), # AL=0xc5, AF=0 CF=1 + ( 0x2b, 0x15 ), # AL=0xc5, AF=1 CF=0 + ( 0x2b, 0x15 ), # AL=0xc5, AF=1 CF=1 + ( 0x26, 0x01 ), # AL=0xc6, AF=0 CF=0 + ( 0x26, 0x01 ), # AL=0xc6, AF=0 CF=1 + ( 0x2c, 0x11 ), # AL=0xc6, AF=1 CF=0 + ( 0x2c, 0x11 ), # AL=0xc6, AF=1 CF=1 + ( 0x27, 0x05 ), # AL=0xc7, AF=0 CF=0 + ( 0x27, 0x05 ), # AL=0xc7, AF=0 CF=1 + ( 0x2d, 0x15 ), # AL=0xc7, AF=1 CF=0 + ( 0x2d, 0x15 ), # AL=0xc7, AF=1 CF=1 + ( 0x28, 0x05 ), # AL=0xc8, AF=0 CF=0 + ( 0x28, 0x05 ), # AL=0xc8, AF=0 CF=1 + ( 0x2e, 0x15 ), # AL=0xc8, AF=1 CF=0 + ( 0x2e, 0x15 ), # AL=0xc8, AF=1 CF=1 + ( 0x29, 0x01 ), # AL=0xc9, AF=0 CF=0 + ( 0x29, 0x01 ), # AL=0xc9, AF=0 CF=1 + ( 0x2f, 0x11 ), # AL=0xc9, AF=1 CF=0 + ( 0x2f, 0x11 ), # AL=0xc9, AF=1 CF=1 + ( 0x30, 0x15 ), # AL=0xca, AF=0 CF=0 + ( 0x30, 0x15 ), # AL=0xca, AF=0 CF=1 + ( 0x30, 0x15 ), # AL=0xca, AF=1 CF=0 + ( 0x30, 0x15 ), # AL=0xca, AF=1 CF=1 + ( 0x31, 0x11 ), # AL=0xcb, AF=0 CF=0 + ( 0x31, 0x11 ), # AL=0xcb, AF=0 CF=1 + ( 0x31, 0x11 ), # AL=0xcb, AF=1 CF=0 + ( 0x31, 0x11 ), # AL=0xcb, AF=1 CF=1 + ( 0x32, 0x11 ), # AL=0xcc, AF=0 CF=0 + ( 0x32, 0x11 ), # AL=0xcc, AF=0 CF=1 + ( 0x32, 0x11 ), # AL=0xcc, AF=1 CF=0 + ( 0x32, 0x11 ), # AL=0xcc, AF=1 CF=1 + ( 0x33, 0x15 ), # AL=0xcd, AF=0 CF=0 + ( 0x33, 0x15 ), # AL=0xcd, AF=0 CF=1 + ( 0x33, 0x15 ), # AL=0xcd, AF=1 CF=0 + ( 0x33, 0x15 ), # AL=0xcd, AF=1 CF=1 + ( 0x34, 0x11 ), # AL=0xce, AF=0 CF=0 + ( 0x34, 0x11 ), # AL=0xce, AF=0 CF=1 + ( 0x34, 0x11 ), # AL=0xce, AF=1 CF=0 + ( 0x34, 0x11 ), # AL=0xce, AF=1 CF=1 + ( 0x35, 0x15 ), # AL=0xcf, AF=0 CF=0 + ( 0x35, 0x15 ), # AL=0xcf, AF=0 CF=1 + ( 0x35, 0x15 ), # AL=0xcf, AF=1 CF=0 + ( 0x35, 0x15 ), # AL=0xcf, AF=1 CF=1 + ( 0x30, 0x05 ), # AL=0xd0, AF=0 CF=0 + ( 0x30, 0x05 ), # AL=0xd0, AF=0 CF=1 + ( 0x36, 0x15 ), # AL=0xd0, AF=1 CF=0 + ( 0x36, 0x15 ), # AL=0xd0, AF=1 CF=1 + ( 0x31, 0x01 ), # AL=0xd1, AF=0 CF=0 + ( 0x31, 0x01 ), # AL=0xd1, AF=0 CF=1 + ( 0x37, 0x11 ), # AL=0xd1, AF=1 CF=0 + ( 0x37, 0x11 ), # AL=0xd1, AF=1 CF=1 + ( 0x32, 0x01 ), # AL=0xd2, AF=0 CF=0 + ( 0x32, 0x01 ), # AL=0xd2, AF=0 CF=1 + ( 0x38, 0x11 ), # AL=0xd2, AF=1 CF=0 + ( 0x38, 0x11 ), # AL=0xd2, AF=1 CF=1 + ( 0x33, 0x05 ), # AL=0xd3, AF=0 CF=0 + ( 0x33, 0x05 ), # AL=0xd3, AF=0 CF=1 + ( 0x39, 0x15 ), # AL=0xd3, AF=1 CF=0 + ( 0x39, 0x15 ), # AL=0xd3, AF=1 CF=1 + ( 0x34, 0x01 ), # AL=0xd4, AF=0 CF=0 + ( 0x34, 0x01 ), # AL=0xd4, AF=0 CF=1 + ( 0x3a, 0x15 ), # AL=0xd4, AF=1 CF=0 + ( 0x3a, 0x15 ), # AL=0xd4, AF=1 CF=1 + ( 0x35, 0x05 ), # AL=0xd5, AF=0 CF=0 + ( 0x35, 0x05 ), # AL=0xd5, AF=0 CF=1 + ( 0x3b, 0x11 ), # AL=0xd5, AF=1 CF=0 + ( 0x3b, 0x11 ), # AL=0xd5, AF=1 CF=1 + ( 0x36, 0x05 ), # AL=0xd6, AF=0 CF=0 + ( 0x36, 0x05 ), # AL=0xd6, AF=0 CF=1 + ( 0x3c, 0x15 ), # AL=0xd6, AF=1 CF=0 + ( 0x3c, 0x15 ), # AL=0xd6, AF=1 CF=1 + ( 0x37, 0x01 ), # AL=0xd7, AF=0 CF=0 + ( 0x37, 0x01 ), # AL=0xd7, AF=0 CF=1 + ( 0x3d, 0x11 ), # AL=0xd7, AF=1 CF=0 + ( 0x3d, 0x11 ), # AL=0xd7, AF=1 CF=1 + ( 0x38, 0x01 ), # AL=0xd8, AF=0 CF=0 + ( 0x38, 0x01 ), # AL=0xd8, AF=0 CF=1 + ( 0x3e, 0x11 ), # AL=0xd8, AF=1 CF=0 + ( 0x3e, 0x11 ), # AL=0xd8, AF=1 CF=1 + ( 0x39, 0x05 ), # AL=0xd9, AF=0 CF=0 + ( 0x39, 0x05 ), # AL=0xd9, AF=0 CF=1 + ( 0x3f, 0x15 ), # AL=0xd9, AF=1 CF=0 + ( 0x3f, 0x15 ), # AL=0xd9, AF=1 CF=1 + ( 0x40, 0x11 ), # AL=0xda, AF=0 CF=0 + ( 0x40, 0x11 ), # AL=0xda, AF=0 CF=1 + ( 0x40, 0x11 ), # AL=0xda, AF=1 CF=0 + ( 0x40, 0x11 ), # AL=0xda, AF=1 CF=1 + ( 0x41, 0x15 ), # AL=0xdb, AF=0 CF=0 + ( 0x41, 0x15 ), # AL=0xdb, AF=0 CF=1 + ( 0x41, 0x15 ), # AL=0xdb, AF=1 CF=0 + ( 0x41, 0x15 ), # AL=0xdb, AF=1 CF=1 + ( 0x42, 0x15 ), # AL=0xdc, AF=0 CF=0 + ( 0x42, 0x15 ), # AL=0xdc, AF=0 CF=1 + ( 0x42, 0x15 ), # AL=0xdc, AF=1 CF=0 + ( 0x42, 0x15 ), # AL=0xdc, AF=1 CF=1 + ( 0x43, 0x11 ), # AL=0xdd, AF=0 CF=0 + ( 0x43, 0x11 ), # AL=0xdd, AF=0 CF=1 + ( 0x43, 0x11 ), # AL=0xdd, AF=1 CF=0 + ( 0x43, 0x11 ), # AL=0xdd, AF=1 CF=1 + ( 0x44, 0x15 ), # AL=0xde, AF=0 CF=0 + ( 0x44, 0x15 ), # AL=0xde, AF=0 CF=1 + ( 0x44, 0x15 ), # AL=0xde, AF=1 CF=0 + ( 0x44, 0x15 ), # AL=0xde, AF=1 CF=1 + ( 0x45, 0x11 ), # AL=0xdf, AF=0 CF=0 + ( 0x45, 0x11 ), # AL=0xdf, AF=0 CF=1 + ( 0x45, 0x11 ), # AL=0xdf, AF=1 CF=0 + ( 0x45, 0x11 ), # AL=0xdf, AF=1 CF=1 + ( 0x40, 0x01 ), # AL=0xe0, AF=0 CF=0 + ( 0x40, 0x01 ), # AL=0xe0, AF=0 CF=1 + ( 0x46, 0x11 ), # AL=0xe0, AF=1 CF=0 + ( 0x46, 0x11 ), # AL=0xe0, AF=1 CF=1 + ( 0x41, 0x05 ), # AL=0xe1, AF=0 CF=0 + ( 0x41, 0x05 ), # AL=0xe1, AF=0 CF=1 + ( 0x47, 0x15 ), # AL=0xe1, AF=1 CF=0 + ( 0x47, 0x15 ), # AL=0xe1, AF=1 CF=1 + ( 0x42, 0x05 ), # AL=0xe2, AF=0 CF=0 + ( 0x42, 0x05 ), # AL=0xe2, AF=0 CF=1 + ( 0x48, 0x15 ), # AL=0xe2, AF=1 CF=0 + ( 0x48, 0x15 ), # AL=0xe2, AF=1 CF=1 + ( 0x43, 0x01 ), # AL=0xe3, AF=0 CF=0 + ( 0x43, 0x01 ), # AL=0xe3, AF=0 CF=1 + ( 0x49, 0x11 ), # AL=0xe3, AF=1 CF=0 + ( 0x49, 0x11 ), # AL=0xe3, AF=1 CF=1 + ( 0x44, 0x05 ), # AL=0xe4, AF=0 CF=0 + ( 0x44, 0x05 ), # AL=0xe4, AF=0 CF=1 + ( 0x4a, 0x11 ), # AL=0xe4, AF=1 CF=0 + ( 0x4a, 0x11 ), # AL=0xe4, AF=1 CF=1 + ( 0x45, 0x01 ), # AL=0xe5, AF=0 CF=0 + ( 0x45, 0x01 ), # AL=0xe5, AF=0 CF=1 + ( 0x4b, 0x15 ), # AL=0xe5, AF=1 CF=0 + ( 0x4b, 0x15 ), # AL=0xe5, AF=1 CF=1 + ( 0x46, 0x01 ), # AL=0xe6, AF=0 CF=0 + ( 0x46, 0x01 ), # AL=0xe6, AF=0 CF=1 + ( 0x4c, 0x11 ), # AL=0xe6, AF=1 CF=0 + ( 0x4c, 0x11 ), # AL=0xe6, AF=1 CF=1 + ( 0x47, 0x05 ), # AL=0xe7, AF=0 CF=0 + ( 0x47, 0x05 ), # AL=0xe7, AF=0 CF=1 + ( 0x4d, 0x15 ), # AL=0xe7, AF=1 CF=0 + ( 0x4d, 0x15 ), # AL=0xe7, AF=1 CF=1 + ( 0x48, 0x05 ), # AL=0xe8, AF=0 CF=0 + ( 0x48, 0x05 ), # AL=0xe8, AF=0 CF=1 + ( 0x4e, 0x15 ), # AL=0xe8, AF=1 CF=0 + ( 0x4e, 0x15 ), # AL=0xe8, AF=1 CF=1 + ( 0x49, 0x01 ), # AL=0xe9, AF=0 CF=0 + ( 0x49, 0x01 ), # AL=0xe9, AF=0 CF=1 + ( 0x4f, 0x11 ), # AL=0xe9, AF=1 CF=0 + ( 0x4f, 0x11 ), # AL=0xe9, AF=1 CF=1 + ( 0x50, 0x15 ), # AL=0xea, AF=0 CF=0 + ( 0x50, 0x15 ), # AL=0xea, AF=0 CF=1 + ( 0x50, 0x15 ), # AL=0xea, AF=1 CF=0 + ( 0x50, 0x15 ), # AL=0xea, AF=1 CF=1 + ( 0x51, 0x11 ), # AL=0xeb, AF=0 CF=0 + ( 0x51, 0x11 ), # AL=0xeb, AF=0 CF=1 + ( 0x51, 0x11 ), # AL=0xeb, AF=1 CF=0 + ( 0x51, 0x11 ), # AL=0xeb, AF=1 CF=1 + ( 0x52, 0x11 ), # AL=0xec, AF=0 CF=0 + ( 0x52, 0x11 ), # AL=0xec, AF=0 CF=1 + ( 0x52, 0x11 ), # AL=0xec, AF=1 CF=0 + ( 0x52, 0x11 ), # AL=0xec, AF=1 CF=1 + ( 0x53, 0x15 ), # AL=0xed, AF=0 CF=0 + ( 0x53, 0x15 ), # AL=0xed, AF=0 CF=1 + ( 0x53, 0x15 ), # AL=0xed, AF=1 CF=0 + ( 0x53, 0x15 ), # AL=0xed, AF=1 CF=1 + ( 0x54, 0x11 ), # AL=0xee, AF=0 CF=0 + ( 0x54, 0x11 ), # AL=0xee, AF=0 CF=1 + ( 0x54, 0x11 ), # AL=0xee, AF=1 CF=0 + ( 0x54, 0x11 ), # AL=0xee, AF=1 CF=1 + ( 0x55, 0x15 ), # AL=0xef, AF=0 CF=0 + ( 0x55, 0x15 ), # AL=0xef, AF=0 CF=1 + ( 0x55, 0x15 ), # AL=0xef, AF=1 CF=0 + ( 0x55, 0x15 ), # AL=0xef, AF=1 CF=1 + ( 0x50, 0x05 ), # AL=0xf0, AF=0 CF=0 + ( 0x50, 0x05 ), # AL=0xf0, AF=0 CF=1 + ( 0x56, 0x15 ), # AL=0xf0, AF=1 CF=0 + ( 0x56, 0x15 ), # AL=0xf0, AF=1 CF=1 + ( 0x51, 0x01 ), # AL=0xf1, AF=0 CF=0 + ( 0x51, 0x01 ), # AL=0xf1, AF=0 CF=1 + ( 0x57, 0x11 ), # AL=0xf1, AF=1 CF=0 + ( 0x57, 0x11 ), # AL=0xf1, AF=1 CF=1 + ( 0x52, 0x01 ), # AL=0xf2, AF=0 CF=0 + ( 0x52, 0x01 ), # AL=0xf2, AF=0 CF=1 + ( 0x58, 0x11 ), # AL=0xf2, AF=1 CF=0 + ( 0x58, 0x11 ), # AL=0xf2, AF=1 CF=1 + ( 0x53, 0x05 ), # AL=0xf3, AF=0 CF=0 + ( 0x53, 0x05 ), # AL=0xf3, AF=0 CF=1 + ( 0x59, 0x15 ), # AL=0xf3, AF=1 CF=0 + ( 0x59, 0x15 ), # AL=0xf3, AF=1 CF=1 + ( 0x54, 0x01 ), # AL=0xf4, AF=0 CF=0 + ( 0x54, 0x01 ), # AL=0xf4, AF=0 CF=1 + ( 0x5a, 0x15 ), # AL=0xf4, AF=1 CF=0 + ( 0x5a, 0x15 ), # AL=0xf4, AF=1 CF=1 + ( 0x55, 0x05 ), # AL=0xf5, AF=0 CF=0 + ( 0x55, 0x05 ), # AL=0xf5, AF=0 CF=1 + ( 0x5b, 0x11 ), # AL=0xf5, AF=1 CF=0 + ( 0x5b, 0x11 ), # AL=0xf5, AF=1 CF=1 + ( 0x56, 0x05 ), # AL=0xf6, AF=0 CF=0 + ( 0x56, 0x05 ), # AL=0xf6, AF=0 CF=1 + ( 0x5c, 0x15 ), # AL=0xf6, AF=1 CF=0 + ( 0x5c, 0x15 ), # AL=0xf6, AF=1 CF=1 + ( 0x57, 0x01 ), # AL=0xf7, AF=0 CF=0 + ( 0x57, 0x01 ), # AL=0xf7, AF=0 CF=1 + ( 0x5d, 0x11 ), # AL=0xf7, AF=1 CF=0 + ( 0x5d, 0x11 ), # AL=0xf7, AF=1 CF=1 + ( 0x58, 0x01 ), # AL=0xf8, AF=0 CF=0 + ( 0x58, 0x01 ), # AL=0xf8, AF=0 CF=1 + ( 0x5e, 0x11 ), # AL=0xf8, AF=1 CF=0 + ( 0x5e, 0x11 ), # AL=0xf8, AF=1 CF=1 + ( 0x59, 0x05 ), # AL=0xf9, AF=0 CF=0 + ( 0x59, 0x05 ), # AL=0xf9, AF=0 CF=1 + ( 0x5f, 0x15 ), # AL=0xf9, AF=1 CF=0 + ( 0x5f, 0x15 ), # AL=0xf9, AF=1 CF=1 + ( 0x60, 0x15 ), # AL=0xfa, AF=0 CF=0 + ( 0x60, 0x15 ), # AL=0xfa, AF=0 CF=1 + ( 0x60, 0x15 ), # AL=0xfa, AF=1 CF=0 + ( 0x60, 0x15 ), # AL=0xfa, AF=1 CF=1 + ( 0x61, 0x11 ), # AL=0xfb, AF=0 CF=0 + ( 0x61, 0x11 ), # AL=0xfb, AF=0 CF=1 + ( 0x61, 0x11 ), # AL=0xfb, AF=1 CF=0 + ( 0x61, 0x11 ), # AL=0xfb, AF=1 CF=1 + ( 0x62, 0x11 ), # AL=0xfc, AF=0 CF=0 + ( 0x62, 0x11 ), # AL=0xfc, AF=0 CF=1 + ( 0x62, 0x11 ), # AL=0xfc, AF=1 CF=0 + ( 0x62, 0x11 ), # AL=0xfc, AF=1 CF=1 + ( 0x63, 0x15 ), # AL=0xfd, AF=0 CF=0 + ( 0x63, 0x15 ), # AL=0xfd, AF=0 CF=1 + ( 0x63, 0x15 ), # AL=0xfd, AF=1 CF=0 + ( 0x63, 0x15 ), # AL=0xfd, AF=1 CF=1 + ( 0x64, 0x11 ), # AL=0xfe, AF=0 CF=0 + ( 0x64, 0x11 ), # AL=0xfe, AF=0 CF=1 + ( 0x64, 0x11 ), # AL=0xfe, AF=1 CF=0 + ( 0x64, 0x11 ), # AL=0xfe, AF=1 CF=1 + ( 0x65, 0x15 ), # AL=0xff, AF=0 CF=0 + ( 0x65, 0x15 ), # AL=0xff, AF=0 CF=1 + ( 0x65, 0x15 ), # AL=0xff, AF=1 CF=0 + ( 0x65, 0x15 ), # AL=0xff, AF=1 CF=1 +]; + diff --git a/src/VBox/VMM/testcase/Instructions/itgTableDas.py b/src/VBox/VMM/testcase/Instructions/itgTableDas.py new file mode 100644 index 00000000..702b95f4 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/itgTableDas.py @@ -0,0 +1,1105 @@ +# -*- coding: utf-8 -*- +# $Id: itgTableDas.py $ + +""" +DAS (instruction) result table. +""" + + +__copyright__ = \ +""" +Copyright (C) 2012-2013 Oracle Corporation + +This file is part of VirtualBox Open Source Edition (OSE), as +available from http://www.virtualbox.org. This file is free software; +you can redistribute it and/or modify it under the terms of the GNU +General Public License (GPL) as published by the Free Software +Foundation, in version 2 as it comes in the "COPYING" file of the +VirtualBox OSE distribution. VirtualBox OSE is distributed in the +hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. +""" +__version__ = "$Revision: 90928 $"; + + +## The 32-bit GCC (C99) program that produced the table below. +g_sItgCProgramDas = \ +""" +#include <stdio.h> + +int main() +{ + for (unsigned uInputAL = 0; uInputAL < 256; uInputAL++) + for (unsigned fAux = 0; fAux < 2; fAux++) + for (unsigned fCarry = 0; fCarry < 2; fCarry++) + { + unsigned uInputEFlags = fCarry | (fAux << 4); + unsigned uResultAL; + unsigned uResultEFlags; + __asm__ __volatile__("pushl %1\\n" + "popfl\\n" + "das\\n" + "pushf\\n" + "pop %1\\n" + : "=a" (uResultAL), + "=r" (uResultEFlags) + : "0" (uInputAL), + "1" (uInputEFlags) + : "memory" + ); + printf(" ( 0x%02x, 0x%02x ), # AL=0x%02x, AF=%u CF=%u\\n", + uResultAL, uResultEFlags & 0xd5, uInputAL, fAux, fCarry); + /* 0xd5 = CF, PF, AF, ZF, SF */ + } + return 0; +} +"""; + + +# +# Compile and run the above program if requested to do so. +# +if __name__ == '__main__': + import sys; + if len(sys.argv) > 1 and sys.argv[1] == 'gen': + import subprocess; + oProc = subprocess.Popen(['gcc', '-x', 'c', '-std=gnu99', '-m32', '-o', './itgTableDas', '-'], stdin = subprocess.PIPE); + oProc.communicate(g_sItgCProgramDas); + oProc.wait(); + oProc = subprocess.Popen(['./itgTableDas',]).wait(); + sys.exit(0); + + + +## +# The DAS results. +# +# The index / input relation is: index = (AL << 2) | (CF << 1) | AF +# +g_aItgDasResults = \ +[ + ( 0x00, 0x44 ), # AL=0x00, AF=0 CF=0 + ( 0xa0, 0x85 ), # AL=0x00, AF=0 CF=1 + ( 0xfa, 0x95 ), # AL=0x00, AF=1 CF=0 + ( 0x9a, 0x95 ), # AL=0x00, AF=1 CF=1 + ( 0x01, 0x00 ), # AL=0x01, AF=0 CF=0 + ( 0xa1, 0x81 ), # AL=0x01, AF=0 CF=1 + ( 0xfb, 0x91 ), # AL=0x01, AF=1 CF=0 + ( 0x9b, 0x91 ), # AL=0x01, AF=1 CF=1 + ( 0x02, 0x00 ), # AL=0x02, AF=0 CF=0 + ( 0xa2, 0x81 ), # AL=0x02, AF=0 CF=1 + ( 0xfc, 0x95 ), # AL=0x02, AF=1 CF=0 + ( 0x9c, 0x95 ), # AL=0x02, AF=1 CF=1 + ( 0x03, 0x04 ), # AL=0x03, AF=0 CF=0 + ( 0xa3, 0x85 ), # AL=0x03, AF=0 CF=1 + ( 0xfd, 0x91 ), # AL=0x03, AF=1 CF=0 + ( 0x9d, 0x91 ), # AL=0x03, AF=1 CF=1 + ( 0x04, 0x00 ), # AL=0x04, AF=0 CF=0 + ( 0xa4, 0x81 ), # AL=0x04, AF=0 CF=1 + ( 0xfe, 0x91 ), # AL=0x04, AF=1 CF=0 + ( 0x9e, 0x91 ), # AL=0x04, AF=1 CF=1 + ( 0x05, 0x04 ), # AL=0x05, AF=0 CF=0 + ( 0xa5, 0x85 ), # AL=0x05, AF=0 CF=1 + ( 0xff, 0x95 ), # AL=0x05, AF=1 CF=0 + ( 0x9f, 0x95 ), # AL=0x05, AF=1 CF=1 + ( 0x06, 0x04 ), # AL=0x06, AF=0 CF=0 + ( 0xa6, 0x85 ), # AL=0x06, AF=0 CF=1 + ( 0x00, 0x54 ), # AL=0x06, AF=1 CF=0 + ( 0xa0, 0x95 ), # AL=0x06, AF=1 CF=1 + ( 0x07, 0x00 ), # AL=0x07, AF=0 CF=0 + ( 0xa7, 0x81 ), # AL=0x07, AF=0 CF=1 + ( 0x01, 0x10 ), # AL=0x07, AF=1 CF=0 + ( 0xa1, 0x91 ), # AL=0x07, AF=1 CF=1 + ( 0x08, 0x00 ), # AL=0x08, AF=0 CF=0 + ( 0xa8, 0x81 ), # AL=0x08, AF=0 CF=1 + ( 0x02, 0x10 ), # AL=0x08, AF=1 CF=0 + ( 0xa2, 0x91 ), # AL=0x08, AF=1 CF=1 + ( 0x09, 0x04 ), # AL=0x09, AF=0 CF=0 + ( 0xa9, 0x85 ), # AL=0x09, AF=0 CF=1 + ( 0x03, 0x14 ), # AL=0x09, AF=1 CF=0 + ( 0xa3, 0x95 ), # AL=0x09, AF=1 CF=1 + ( 0x04, 0x10 ), # AL=0x0a, AF=0 CF=0 + ( 0xa4, 0x91 ), # AL=0x0a, AF=0 CF=1 + ( 0x04, 0x10 ), # AL=0x0a, AF=1 CF=0 + ( 0xa4, 0x91 ), # AL=0x0a, AF=1 CF=1 + ( 0x05, 0x14 ), # AL=0x0b, AF=0 CF=0 + ( 0xa5, 0x95 ), # AL=0x0b, AF=0 CF=1 + ( 0x05, 0x14 ), # AL=0x0b, AF=1 CF=0 + ( 0xa5, 0x95 ), # AL=0x0b, AF=1 CF=1 + ( 0x06, 0x14 ), # AL=0x0c, AF=0 CF=0 + ( 0xa6, 0x95 ), # AL=0x0c, AF=0 CF=1 + ( 0x06, 0x14 ), # AL=0x0c, AF=1 CF=0 + ( 0xa6, 0x95 ), # AL=0x0c, AF=1 CF=1 + ( 0x07, 0x10 ), # AL=0x0d, AF=0 CF=0 + ( 0xa7, 0x91 ), # AL=0x0d, AF=0 CF=1 + ( 0x07, 0x10 ), # AL=0x0d, AF=1 CF=0 + ( 0xa7, 0x91 ), # AL=0x0d, AF=1 CF=1 + ( 0x08, 0x10 ), # AL=0x0e, AF=0 CF=0 + ( 0xa8, 0x91 ), # AL=0x0e, AF=0 CF=1 + ( 0x08, 0x10 ), # AL=0x0e, AF=1 CF=0 + ( 0xa8, 0x91 ), # AL=0x0e, AF=1 CF=1 + ( 0x09, 0x14 ), # AL=0x0f, AF=0 CF=0 + ( 0xa9, 0x95 ), # AL=0x0f, AF=0 CF=1 + ( 0x09, 0x14 ), # AL=0x0f, AF=1 CF=0 + ( 0xa9, 0x95 ), # AL=0x0f, AF=1 CF=1 + ( 0x10, 0x00 ), # AL=0x10, AF=0 CF=0 + ( 0xb0, 0x81 ), # AL=0x10, AF=0 CF=1 + ( 0x0a, 0x14 ), # AL=0x10, AF=1 CF=0 + ( 0xaa, 0x95 ), # AL=0x10, AF=1 CF=1 + ( 0x11, 0x04 ), # AL=0x11, AF=0 CF=0 + ( 0xb1, 0x85 ), # AL=0x11, AF=0 CF=1 + ( 0x0b, 0x10 ), # AL=0x11, AF=1 CF=0 + ( 0xab, 0x91 ), # AL=0x11, AF=1 CF=1 + ( 0x12, 0x04 ), # AL=0x12, AF=0 CF=0 + ( 0xb2, 0x85 ), # AL=0x12, AF=0 CF=1 + ( 0x0c, 0x14 ), # AL=0x12, AF=1 CF=0 + ( 0xac, 0x95 ), # AL=0x12, AF=1 CF=1 + ( 0x13, 0x00 ), # AL=0x13, AF=0 CF=0 + ( 0xb3, 0x81 ), # AL=0x13, AF=0 CF=1 + ( 0x0d, 0x10 ), # AL=0x13, AF=1 CF=0 + ( 0xad, 0x91 ), # AL=0x13, AF=1 CF=1 + ( 0x14, 0x04 ), # AL=0x14, AF=0 CF=0 + ( 0xb4, 0x85 ), # AL=0x14, AF=0 CF=1 + ( 0x0e, 0x10 ), # AL=0x14, AF=1 CF=0 + ( 0xae, 0x91 ), # AL=0x14, AF=1 CF=1 + ( 0x15, 0x00 ), # AL=0x15, AF=0 CF=0 + ( 0xb5, 0x81 ), # AL=0x15, AF=0 CF=1 + ( 0x0f, 0x14 ), # AL=0x15, AF=1 CF=0 + ( 0xaf, 0x95 ), # AL=0x15, AF=1 CF=1 + ( 0x16, 0x00 ), # AL=0x16, AF=0 CF=0 + ( 0xb6, 0x81 ), # AL=0x16, AF=0 CF=1 + ( 0x10, 0x10 ), # AL=0x16, AF=1 CF=0 + ( 0xb0, 0x91 ), # AL=0x16, AF=1 CF=1 + ( 0x17, 0x04 ), # AL=0x17, AF=0 CF=0 + ( 0xb7, 0x85 ), # AL=0x17, AF=0 CF=1 + ( 0x11, 0x14 ), # AL=0x17, AF=1 CF=0 + ( 0xb1, 0x95 ), # AL=0x17, AF=1 CF=1 + ( 0x18, 0x04 ), # AL=0x18, AF=0 CF=0 + ( 0xb8, 0x85 ), # AL=0x18, AF=0 CF=1 + ( 0x12, 0x14 ), # AL=0x18, AF=1 CF=0 + ( 0xb2, 0x95 ), # AL=0x18, AF=1 CF=1 + ( 0x19, 0x00 ), # AL=0x19, AF=0 CF=0 + ( 0xb9, 0x81 ), # AL=0x19, AF=0 CF=1 + ( 0x13, 0x10 ), # AL=0x19, AF=1 CF=0 + ( 0xb3, 0x91 ), # AL=0x19, AF=1 CF=1 + ( 0x14, 0x14 ), # AL=0x1a, AF=0 CF=0 + ( 0xb4, 0x95 ), # AL=0x1a, AF=0 CF=1 + ( 0x14, 0x14 ), # AL=0x1a, AF=1 CF=0 + ( 0xb4, 0x95 ), # AL=0x1a, AF=1 CF=1 + ( 0x15, 0x10 ), # AL=0x1b, AF=0 CF=0 + ( 0xb5, 0x91 ), # AL=0x1b, AF=0 CF=1 + ( 0x15, 0x10 ), # AL=0x1b, AF=1 CF=0 + ( 0xb5, 0x91 ), # AL=0x1b, AF=1 CF=1 + ( 0x16, 0x10 ), # AL=0x1c, AF=0 CF=0 + ( 0xb6, 0x91 ), # AL=0x1c, AF=0 CF=1 + ( 0x16, 0x10 ), # AL=0x1c, AF=1 CF=0 + ( 0xb6, 0x91 ), # AL=0x1c, AF=1 CF=1 + ( 0x17, 0x14 ), # AL=0x1d, AF=0 CF=0 + ( 0xb7, 0x95 ), # AL=0x1d, AF=0 CF=1 + ( 0x17, 0x14 ), # AL=0x1d, AF=1 CF=0 + ( 0xb7, 0x95 ), # AL=0x1d, AF=1 CF=1 + ( 0x18, 0x14 ), # AL=0x1e, AF=0 CF=0 + ( 0xb8, 0x95 ), # AL=0x1e, AF=0 CF=1 + ( 0x18, 0x14 ), # AL=0x1e, AF=1 CF=0 + ( 0xb8, 0x95 ), # AL=0x1e, AF=1 CF=1 + ( 0x19, 0x10 ), # AL=0x1f, AF=0 CF=0 + ( 0xb9, 0x91 ), # AL=0x1f, AF=0 CF=1 + ( 0x19, 0x10 ), # AL=0x1f, AF=1 CF=0 + ( 0xb9, 0x91 ), # AL=0x1f, AF=1 CF=1 + ( 0x20, 0x00 ), # AL=0x20, AF=0 CF=0 + ( 0xc0, 0x85 ), # AL=0x20, AF=0 CF=1 + ( 0x1a, 0x10 ), # AL=0x20, AF=1 CF=0 + ( 0xba, 0x91 ), # AL=0x20, AF=1 CF=1 + ( 0x21, 0x04 ), # AL=0x21, AF=0 CF=0 + ( 0xc1, 0x81 ), # AL=0x21, AF=0 CF=1 + ( 0x1b, 0x14 ), # AL=0x21, AF=1 CF=0 + ( 0xbb, 0x95 ), # AL=0x21, AF=1 CF=1 + ( 0x22, 0x04 ), # AL=0x22, AF=0 CF=0 + ( 0xc2, 0x81 ), # AL=0x22, AF=0 CF=1 + ( 0x1c, 0x10 ), # AL=0x22, AF=1 CF=0 + ( 0xbc, 0x91 ), # AL=0x22, AF=1 CF=1 + ( 0x23, 0x00 ), # AL=0x23, AF=0 CF=0 + ( 0xc3, 0x85 ), # AL=0x23, AF=0 CF=1 + ( 0x1d, 0x14 ), # AL=0x23, AF=1 CF=0 + ( 0xbd, 0x95 ), # AL=0x23, AF=1 CF=1 + ( 0x24, 0x04 ), # AL=0x24, AF=0 CF=0 + ( 0xc4, 0x81 ), # AL=0x24, AF=0 CF=1 + ( 0x1e, 0x14 ), # AL=0x24, AF=1 CF=0 + ( 0xbe, 0x95 ), # AL=0x24, AF=1 CF=1 + ( 0x25, 0x00 ), # AL=0x25, AF=0 CF=0 + ( 0xc5, 0x85 ), # AL=0x25, AF=0 CF=1 + ( 0x1f, 0x10 ), # AL=0x25, AF=1 CF=0 + ( 0xbf, 0x91 ), # AL=0x25, AF=1 CF=1 + ( 0x26, 0x00 ), # AL=0x26, AF=0 CF=0 + ( 0xc6, 0x85 ), # AL=0x26, AF=0 CF=1 + ( 0x20, 0x10 ), # AL=0x26, AF=1 CF=0 + ( 0xc0, 0x95 ), # AL=0x26, AF=1 CF=1 + ( 0x27, 0x04 ), # AL=0x27, AF=0 CF=0 + ( 0xc7, 0x81 ), # AL=0x27, AF=0 CF=1 + ( 0x21, 0x14 ), # AL=0x27, AF=1 CF=0 + ( 0xc1, 0x91 ), # AL=0x27, AF=1 CF=1 + ( 0x28, 0x04 ), # AL=0x28, AF=0 CF=0 + ( 0xc8, 0x81 ), # AL=0x28, AF=0 CF=1 + ( 0x22, 0x14 ), # AL=0x28, AF=1 CF=0 + ( 0xc2, 0x91 ), # AL=0x28, AF=1 CF=1 + ( 0x29, 0x00 ), # AL=0x29, AF=0 CF=0 + ( 0xc9, 0x85 ), # AL=0x29, AF=0 CF=1 + ( 0x23, 0x10 ), # AL=0x29, AF=1 CF=0 + ( 0xc3, 0x95 ), # AL=0x29, AF=1 CF=1 + ( 0x24, 0x14 ), # AL=0x2a, AF=0 CF=0 + ( 0xc4, 0x91 ), # AL=0x2a, AF=0 CF=1 + ( 0x24, 0x14 ), # AL=0x2a, AF=1 CF=0 + ( 0xc4, 0x91 ), # AL=0x2a, AF=1 CF=1 + ( 0x25, 0x10 ), # AL=0x2b, AF=0 CF=0 + ( 0xc5, 0x95 ), # AL=0x2b, AF=0 CF=1 + ( 0x25, 0x10 ), # AL=0x2b, AF=1 CF=0 + ( 0xc5, 0x95 ), # AL=0x2b, AF=1 CF=1 + ( 0x26, 0x10 ), # AL=0x2c, AF=0 CF=0 + ( 0xc6, 0x95 ), # AL=0x2c, AF=0 CF=1 + ( 0x26, 0x10 ), # AL=0x2c, AF=1 CF=0 + ( 0xc6, 0x95 ), # AL=0x2c, AF=1 CF=1 + ( 0x27, 0x14 ), # AL=0x2d, AF=0 CF=0 + ( 0xc7, 0x91 ), # AL=0x2d, AF=0 CF=1 + ( 0x27, 0x14 ), # AL=0x2d, AF=1 CF=0 + ( 0xc7, 0x91 ), # AL=0x2d, AF=1 CF=1 + ( 0x28, 0x14 ), # AL=0x2e, AF=0 CF=0 + ( 0xc8, 0x91 ), # AL=0x2e, AF=0 CF=1 + ( 0x28, 0x14 ), # AL=0x2e, AF=1 CF=0 + ( 0xc8, 0x91 ), # AL=0x2e, AF=1 CF=1 + ( 0x29, 0x10 ), # AL=0x2f, AF=0 CF=0 + ( 0xc9, 0x95 ), # AL=0x2f, AF=0 CF=1 + ( 0x29, 0x10 ), # AL=0x2f, AF=1 CF=0 + ( 0xc9, 0x95 ), # AL=0x2f, AF=1 CF=1 + ( 0x30, 0x04 ), # AL=0x30, AF=0 CF=0 + ( 0xd0, 0x81 ), # AL=0x30, AF=0 CF=1 + ( 0x2a, 0x10 ), # AL=0x30, AF=1 CF=0 + ( 0xca, 0x95 ), # AL=0x30, AF=1 CF=1 + ( 0x31, 0x00 ), # AL=0x31, AF=0 CF=0 + ( 0xd1, 0x85 ), # AL=0x31, AF=0 CF=1 + ( 0x2b, 0x14 ), # AL=0x31, AF=1 CF=0 + ( 0xcb, 0x91 ), # AL=0x31, AF=1 CF=1 + ( 0x32, 0x00 ), # AL=0x32, AF=0 CF=0 + ( 0xd2, 0x85 ), # AL=0x32, AF=0 CF=1 + ( 0x2c, 0x10 ), # AL=0x32, AF=1 CF=0 + ( 0xcc, 0x95 ), # AL=0x32, AF=1 CF=1 + ( 0x33, 0x04 ), # AL=0x33, AF=0 CF=0 + ( 0xd3, 0x81 ), # AL=0x33, AF=0 CF=1 + ( 0x2d, 0x14 ), # AL=0x33, AF=1 CF=0 + ( 0xcd, 0x91 ), # AL=0x33, AF=1 CF=1 + ( 0x34, 0x00 ), # AL=0x34, AF=0 CF=0 + ( 0xd4, 0x85 ), # AL=0x34, AF=0 CF=1 + ( 0x2e, 0x14 ), # AL=0x34, AF=1 CF=0 + ( 0xce, 0x91 ), # AL=0x34, AF=1 CF=1 + ( 0x35, 0x04 ), # AL=0x35, AF=0 CF=0 + ( 0xd5, 0x81 ), # AL=0x35, AF=0 CF=1 + ( 0x2f, 0x10 ), # AL=0x35, AF=1 CF=0 + ( 0xcf, 0x95 ), # AL=0x35, AF=1 CF=1 + ( 0x36, 0x04 ), # AL=0x36, AF=0 CF=0 + ( 0xd6, 0x81 ), # AL=0x36, AF=0 CF=1 + ( 0x30, 0x14 ), # AL=0x36, AF=1 CF=0 + ( 0xd0, 0x91 ), # AL=0x36, AF=1 CF=1 + ( 0x37, 0x00 ), # AL=0x37, AF=0 CF=0 + ( 0xd7, 0x85 ), # AL=0x37, AF=0 CF=1 + ( 0x31, 0x10 ), # AL=0x37, AF=1 CF=0 + ( 0xd1, 0x95 ), # AL=0x37, AF=1 CF=1 + ( 0x38, 0x00 ), # AL=0x38, AF=0 CF=0 + ( 0xd8, 0x85 ), # AL=0x38, AF=0 CF=1 + ( 0x32, 0x10 ), # AL=0x38, AF=1 CF=0 + ( 0xd2, 0x95 ), # AL=0x38, AF=1 CF=1 + ( 0x39, 0x04 ), # AL=0x39, AF=0 CF=0 + ( 0xd9, 0x81 ), # AL=0x39, AF=0 CF=1 + ( 0x33, 0x14 ), # AL=0x39, AF=1 CF=0 + ( 0xd3, 0x91 ), # AL=0x39, AF=1 CF=1 + ( 0x34, 0x10 ), # AL=0x3a, AF=0 CF=0 + ( 0xd4, 0x95 ), # AL=0x3a, AF=0 CF=1 + ( 0x34, 0x10 ), # AL=0x3a, AF=1 CF=0 + ( 0xd4, 0x95 ), # AL=0x3a, AF=1 CF=1 + ( 0x35, 0x14 ), # AL=0x3b, AF=0 CF=0 + ( 0xd5, 0x91 ), # AL=0x3b, AF=0 CF=1 + ( 0x35, 0x14 ), # AL=0x3b, AF=1 CF=0 + ( 0xd5, 0x91 ), # AL=0x3b, AF=1 CF=1 + ( 0x36, 0x14 ), # AL=0x3c, AF=0 CF=0 + ( 0xd6, 0x91 ), # AL=0x3c, AF=0 CF=1 + ( 0x36, 0x14 ), # AL=0x3c, AF=1 CF=0 + ( 0xd6, 0x91 ), # AL=0x3c, AF=1 CF=1 + ( 0x37, 0x10 ), # AL=0x3d, AF=0 CF=0 + ( 0xd7, 0x95 ), # AL=0x3d, AF=0 CF=1 + ( 0x37, 0x10 ), # AL=0x3d, AF=1 CF=0 + ( 0xd7, 0x95 ), # AL=0x3d, AF=1 CF=1 + ( 0x38, 0x10 ), # AL=0x3e, AF=0 CF=0 + ( 0xd8, 0x95 ), # AL=0x3e, AF=0 CF=1 + ( 0x38, 0x10 ), # AL=0x3e, AF=1 CF=0 + ( 0xd8, 0x95 ), # AL=0x3e, AF=1 CF=1 + ( 0x39, 0x14 ), # AL=0x3f, AF=0 CF=0 + ( 0xd9, 0x91 ), # AL=0x3f, AF=0 CF=1 + ( 0x39, 0x14 ), # AL=0x3f, AF=1 CF=0 + ( 0xd9, 0x91 ), # AL=0x3f, AF=1 CF=1 + ( 0x40, 0x00 ), # AL=0x40, AF=0 CF=0 + ( 0xe0, 0x81 ), # AL=0x40, AF=0 CF=1 + ( 0x3a, 0x14 ), # AL=0x40, AF=1 CF=0 + ( 0xda, 0x91 ), # AL=0x40, AF=1 CF=1 + ( 0x41, 0x04 ), # AL=0x41, AF=0 CF=0 + ( 0xe1, 0x85 ), # AL=0x41, AF=0 CF=1 + ( 0x3b, 0x10 ), # AL=0x41, AF=1 CF=0 + ( 0xdb, 0x95 ), # AL=0x41, AF=1 CF=1 + ( 0x42, 0x04 ), # AL=0x42, AF=0 CF=0 + ( 0xe2, 0x85 ), # AL=0x42, AF=0 CF=1 + ( 0x3c, 0x14 ), # AL=0x42, AF=1 CF=0 + ( 0xdc, 0x91 ), # AL=0x42, AF=1 CF=1 + ( 0x43, 0x00 ), # AL=0x43, AF=0 CF=0 + ( 0xe3, 0x81 ), # AL=0x43, AF=0 CF=1 + ( 0x3d, 0x10 ), # AL=0x43, AF=1 CF=0 + ( 0xdd, 0x95 ), # AL=0x43, AF=1 CF=1 + ( 0x44, 0x04 ), # AL=0x44, AF=0 CF=0 + ( 0xe4, 0x85 ), # AL=0x44, AF=0 CF=1 + ( 0x3e, 0x10 ), # AL=0x44, AF=1 CF=0 + ( 0xde, 0x95 ), # AL=0x44, AF=1 CF=1 + ( 0x45, 0x00 ), # AL=0x45, AF=0 CF=0 + ( 0xe5, 0x81 ), # AL=0x45, AF=0 CF=1 + ( 0x3f, 0x14 ), # AL=0x45, AF=1 CF=0 + ( 0xdf, 0x91 ), # AL=0x45, AF=1 CF=1 + ( 0x46, 0x00 ), # AL=0x46, AF=0 CF=0 + ( 0xe6, 0x81 ), # AL=0x46, AF=0 CF=1 + ( 0x40, 0x10 ), # AL=0x46, AF=1 CF=0 + ( 0xe0, 0x91 ), # AL=0x46, AF=1 CF=1 + ( 0x47, 0x04 ), # AL=0x47, AF=0 CF=0 + ( 0xe7, 0x85 ), # AL=0x47, AF=0 CF=1 + ( 0x41, 0x14 ), # AL=0x47, AF=1 CF=0 + ( 0xe1, 0x95 ), # AL=0x47, AF=1 CF=1 + ( 0x48, 0x04 ), # AL=0x48, AF=0 CF=0 + ( 0xe8, 0x85 ), # AL=0x48, AF=0 CF=1 + ( 0x42, 0x14 ), # AL=0x48, AF=1 CF=0 + ( 0xe2, 0x95 ), # AL=0x48, AF=1 CF=1 + ( 0x49, 0x00 ), # AL=0x49, AF=0 CF=0 + ( 0xe9, 0x81 ), # AL=0x49, AF=0 CF=1 + ( 0x43, 0x10 ), # AL=0x49, AF=1 CF=0 + ( 0xe3, 0x91 ), # AL=0x49, AF=1 CF=1 + ( 0x44, 0x14 ), # AL=0x4a, AF=0 CF=0 + ( 0xe4, 0x95 ), # AL=0x4a, AF=0 CF=1 + ( 0x44, 0x14 ), # AL=0x4a, AF=1 CF=0 + ( 0xe4, 0x95 ), # AL=0x4a, AF=1 CF=1 + ( 0x45, 0x10 ), # AL=0x4b, AF=0 CF=0 + ( 0xe5, 0x91 ), # AL=0x4b, AF=0 CF=1 + ( 0x45, 0x10 ), # AL=0x4b, AF=1 CF=0 + ( 0xe5, 0x91 ), # AL=0x4b, AF=1 CF=1 + ( 0x46, 0x10 ), # AL=0x4c, AF=0 CF=0 + ( 0xe6, 0x91 ), # AL=0x4c, AF=0 CF=1 + ( 0x46, 0x10 ), # AL=0x4c, AF=1 CF=0 + ( 0xe6, 0x91 ), # AL=0x4c, AF=1 CF=1 + ( 0x47, 0x14 ), # AL=0x4d, AF=0 CF=0 + ( 0xe7, 0x95 ), # AL=0x4d, AF=0 CF=1 + ( 0x47, 0x14 ), # AL=0x4d, AF=1 CF=0 + ( 0xe7, 0x95 ), # AL=0x4d, AF=1 CF=1 + ( 0x48, 0x14 ), # AL=0x4e, AF=0 CF=0 + ( 0xe8, 0x95 ), # AL=0x4e, AF=0 CF=1 + ( 0x48, 0x14 ), # AL=0x4e, AF=1 CF=0 + ( 0xe8, 0x95 ), # AL=0x4e, AF=1 CF=1 + ( 0x49, 0x10 ), # AL=0x4f, AF=0 CF=0 + ( 0xe9, 0x91 ), # AL=0x4f, AF=0 CF=1 + ( 0x49, 0x10 ), # AL=0x4f, AF=1 CF=0 + ( 0xe9, 0x91 ), # AL=0x4f, AF=1 CF=1 + ( 0x50, 0x04 ), # AL=0x50, AF=0 CF=0 + ( 0xf0, 0x85 ), # AL=0x50, AF=0 CF=1 + ( 0x4a, 0x10 ), # AL=0x50, AF=1 CF=0 + ( 0xea, 0x91 ), # AL=0x50, AF=1 CF=1 + ( 0x51, 0x00 ), # AL=0x51, AF=0 CF=0 + ( 0xf1, 0x81 ), # AL=0x51, AF=0 CF=1 + ( 0x4b, 0x14 ), # AL=0x51, AF=1 CF=0 + ( 0xeb, 0x95 ), # AL=0x51, AF=1 CF=1 + ( 0x52, 0x00 ), # AL=0x52, AF=0 CF=0 + ( 0xf2, 0x81 ), # AL=0x52, AF=0 CF=1 + ( 0x4c, 0x10 ), # AL=0x52, AF=1 CF=0 + ( 0xec, 0x91 ), # AL=0x52, AF=1 CF=1 + ( 0x53, 0x04 ), # AL=0x53, AF=0 CF=0 + ( 0xf3, 0x85 ), # AL=0x53, AF=0 CF=1 + ( 0x4d, 0x14 ), # AL=0x53, AF=1 CF=0 + ( 0xed, 0x95 ), # AL=0x53, AF=1 CF=1 + ( 0x54, 0x00 ), # AL=0x54, AF=0 CF=0 + ( 0xf4, 0x81 ), # AL=0x54, AF=0 CF=1 + ( 0x4e, 0x14 ), # AL=0x54, AF=1 CF=0 + ( 0xee, 0x95 ), # AL=0x54, AF=1 CF=1 + ( 0x55, 0x04 ), # AL=0x55, AF=0 CF=0 + ( 0xf5, 0x85 ), # AL=0x55, AF=0 CF=1 + ( 0x4f, 0x10 ), # AL=0x55, AF=1 CF=0 + ( 0xef, 0x91 ), # AL=0x55, AF=1 CF=1 + ( 0x56, 0x04 ), # AL=0x56, AF=0 CF=0 + ( 0xf6, 0x85 ), # AL=0x56, AF=0 CF=1 + ( 0x50, 0x14 ), # AL=0x56, AF=1 CF=0 + ( 0xf0, 0x95 ), # AL=0x56, AF=1 CF=1 + ( 0x57, 0x00 ), # AL=0x57, AF=0 CF=0 + ( 0xf7, 0x81 ), # AL=0x57, AF=0 CF=1 + ( 0x51, 0x10 ), # AL=0x57, AF=1 CF=0 + ( 0xf1, 0x91 ), # AL=0x57, AF=1 CF=1 + ( 0x58, 0x00 ), # AL=0x58, AF=0 CF=0 + ( 0xf8, 0x81 ), # AL=0x58, AF=0 CF=1 + ( 0x52, 0x10 ), # AL=0x58, AF=1 CF=0 + ( 0xf2, 0x91 ), # AL=0x58, AF=1 CF=1 + ( 0x59, 0x04 ), # AL=0x59, AF=0 CF=0 + ( 0xf9, 0x85 ), # AL=0x59, AF=0 CF=1 + ( 0x53, 0x14 ), # AL=0x59, AF=1 CF=0 + ( 0xf3, 0x95 ), # AL=0x59, AF=1 CF=1 + ( 0x54, 0x10 ), # AL=0x5a, AF=0 CF=0 + ( 0xf4, 0x91 ), # AL=0x5a, AF=0 CF=1 + ( 0x54, 0x10 ), # AL=0x5a, AF=1 CF=0 + ( 0xf4, 0x91 ), # AL=0x5a, AF=1 CF=1 + ( 0x55, 0x14 ), # AL=0x5b, AF=0 CF=0 + ( 0xf5, 0x95 ), # AL=0x5b, AF=0 CF=1 + ( 0x55, 0x14 ), # AL=0x5b, AF=1 CF=0 + ( 0xf5, 0x95 ), # AL=0x5b, AF=1 CF=1 + ( 0x56, 0x14 ), # AL=0x5c, AF=0 CF=0 + ( 0xf6, 0x95 ), # AL=0x5c, AF=0 CF=1 + ( 0x56, 0x14 ), # AL=0x5c, AF=1 CF=0 + ( 0xf6, 0x95 ), # AL=0x5c, AF=1 CF=1 + ( 0x57, 0x10 ), # AL=0x5d, AF=0 CF=0 + ( 0xf7, 0x91 ), # AL=0x5d, AF=0 CF=1 + ( 0x57, 0x10 ), # AL=0x5d, AF=1 CF=0 + ( 0xf7, 0x91 ), # AL=0x5d, AF=1 CF=1 + ( 0x58, 0x10 ), # AL=0x5e, AF=0 CF=0 + ( 0xf8, 0x91 ), # AL=0x5e, AF=0 CF=1 + ( 0x58, 0x10 ), # AL=0x5e, AF=1 CF=0 + ( 0xf8, 0x91 ), # AL=0x5e, AF=1 CF=1 + ( 0x59, 0x14 ), # AL=0x5f, AF=0 CF=0 + ( 0xf9, 0x95 ), # AL=0x5f, AF=0 CF=1 + ( 0x59, 0x14 ), # AL=0x5f, AF=1 CF=0 + ( 0xf9, 0x95 ), # AL=0x5f, AF=1 CF=1 + ( 0x60, 0x04 ), # AL=0x60, AF=0 CF=0 + ( 0x00, 0x45 ), # AL=0x60, AF=0 CF=1 + ( 0x5a, 0x14 ), # AL=0x60, AF=1 CF=0 + ( 0xfa, 0x95 ), # AL=0x60, AF=1 CF=1 + ( 0x61, 0x00 ), # AL=0x61, AF=0 CF=0 + ( 0x01, 0x01 ), # AL=0x61, AF=0 CF=1 + ( 0x5b, 0x10 ), # AL=0x61, AF=1 CF=0 + ( 0xfb, 0x91 ), # AL=0x61, AF=1 CF=1 + ( 0x62, 0x00 ), # AL=0x62, AF=0 CF=0 + ( 0x02, 0x01 ), # AL=0x62, AF=0 CF=1 + ( 0x5c, 0x14 ), # AL=0x62, AF=1 CF=0 + ( 0xfc, 0x95 ), # AL=0x62, AF=1 CF=1 + ( 0x63, 0x04 ), # AL=0x63, AF=0 CF=0 + ( 0x03, 0x05 ), # AL=0x63, AF=0 CF=1 + ( 0x5d, 0x10 ), # AL=0x63, AF=1 CF=0 + ( 0xfd, 0x91 ), # AL=0x63, AF=1 CF=1 + ( 0x64, 0x00 ), # AL=0x64, AF=0 CF=0 + ( 0x04, 0x01 ), # AL=0x64, AF=0 CF=1 + ( 0x5e, 0x10 ), # AL=0x64, AF=1 CF=0 + ( 0xfe, 0x91 ), # AL=0x64, AF=1 CF=1 + ( 0x65, 0x04 ), # AL=0x65, AF=0 CF=0 + ( 0x05, 0x05 ), # AL=0x65, AF=0 CF=1 + ( 0x5f, 0x14 ), # AL=0x65, AF=1 CF=0 + ( 0xff, 0x95 ), # AL=0x65, AF=1 CF=1 + ( 0x66, 0x04 ), # AL=0x66, AF=0 CF=0 + ( 0x06, 0x05 ), # AL=0x66, AF=0 CF=1 + ( 0x60, 0x14 ), # AL=0x66, AF=1 CF=0 + ( 0x00, 0x55 ), # AL=0x66, AF=1 CF=1 + ( 0x67, 0x00 ), # AL=0x67, AF=0 CF=0 + ( 0x07, 0x01 ), # AL=0x67, AF=0 CF=1 + ( 0x61, 0x10 ), # AL=0x67, AF=1 CF=0 + ( 0x01, 0x11 ), # AL=0x67, AF=1 CF=1 + ( 0x68, 0x00 ), # AL=0x68, AF=0 CF=0 + ( 0x08, 0x01 ), # AL=0x68, AF=0 CF=1 + ( 0x62, 0x10 ), # AL=0x68, AF=1 CF=0 + ( 0x02, 0x11 ), # AL=0x68, AF=1 CF=1 + ( 0x69, 0x04 ), # AL=0x69, AF=0 CF=0 + ( 0x09, 0x05 ), # AL=0x69, AF=0 CF=1 + ( 0x63, 0x14 ), # AL=0x69, AF=1 CF=0 + ( 0x03, 0x15 ), # AL=0x69, AF=1 CF=1 + ( 0x64, 0x10 ), # AL=0x6a, AF=0 CF=0 + ( 0x04, 0x11 ), # AL=0x6a, AF=0 CF=1 + ( 0x64, 0x10 ), # AL=0x6a, AF=1 CF=0 + ( 0x04, 0x11 ), # AL=0x6a, AF=1 CF=1 + ( 0x65, 0x14 ), # AL=0x6b, AF=0 CF=0 + ( 0x05, 0x15 ), # AL=0x6b, AF=0 CF=1 + ( 0x65, 0x14 ), # AL=0x6b, AF=1 CF=0 + ( 0x05, 0x15 ), # AL=0x6b, AF=1 CF=1 + ( 0x66, 0x14 ), # AL=0x6c, AF=0 CF=0 + ( 0x06, 0x15 ), # AL=0x6c, AF=0 CF=1 + ( 0x66, 0x14 ), # AL=0x6c, AF=1 CF=0 + ( 0x06, 0x15 ), # AL=0x6c, AF=1 CF=1 + ( 0x67, 0x10 ), # AL=0x6d, AF=0 CF=0 + ( 0x07, 0x11 ), # AL=0x6d, AF=0 CF=1 + ( 0x67, 0x10 ), # AL=0x6d, AF=1 CF=0 + ( 0x07, 0x11 ), # AL=0x6d, AF=1 CF=1 + ( 0x68, 0x10 ), # AL=0x6e, AF=0 CF=0 + ( 0x08, 0x11 ), # AL=0x6e, AF=0 CF=1 + ( 0x68, 0x10 ), # AL=0x6e, AF=1 CF=0 + ( 0x08, 0x11 ), # AL=0x6e, AF=1 CF=1 + ( 0x69, 0x14 ), # AL=0x6f, AF=0 CF=0 + ( 0x09, 0x15 ), # AL=0x6f, AF=0 CF=1 + ( 0x69, 0x14 ), # AL=0x6f, AF=1 CF=0 + ( 0x09, 0x15 ), # AL=0x6f, AF=1 CF=1 + ( 0x70, 0x00 ), # AL=0x70, AF=0 CF=0 + ( 0x10, 0x01 ), # AL=0x70, AF=0 CF=1 + ( 0x6a, 0x14 ), # AL=0x70, AF=1 CF=0 + ( 0x0a, 0x15 ), # AL=0x70, AF=1 CF=1 + ( 0x71, 0x04 ), # AL=0x71, AF=0 CF=0 + ( 0x11, 0x05 ), # AL=0x71, AF=0 CF=1 + ( 0x6b, 0x10 ), # AL=0x71, AF=1 CF=0 + ( 0x0b, 0x11 ), # AL=0x71, AF=1 CF=1 + ( 0x72, 0x04 ), # AL=0x72, AF=0 CF=0 + ( 0x12, 0x05 ), # AL=0x72, AF=0 CF=1 + ( 0x6c, 0x14 ), # AL=0x72, AF=1 CF=0 + ( 0x0c, 0x15 ), # AL=0x72, AF=1 CF=1 + ( 0x73, 0x00 ), # AL=0x73, AF=0 CF=0 + ( 0x13, 0x01 ), # AL=0x73, AF=0 CF=1 + ( 0x6d, 0x10 ), # AL=0x73, AF=1 CF=0 + ( 0x0d, 0x11 ), # AL=0x73, AF=1 CF=1 + ( 0x74, 0x04 ), # AL=0x74, AF=0 CF=0 + ( 0x14, 0x05 ), # AL=0x74, AF=0 CF=1 + ( 0x6e, 0x10 ), # AL=0x74, AF=1 CF=0 + ( 0x0e, 0x11 ), # AL=0x74, AF=1 CF=1 + ( 0x75, 0x00 ), # AL=0x75, AF=0 CF=0 + ( 0x15, 0x01 ), # AL=0x75, AF=0 CF=1 + ( 0x6f, 0x14 ), # AL=0x75, AF=1 CF=0 + ( 0x0f, 0x15 ), # AL=0x75, AF=1 CF=1 + ( 0x76, 0x00 ), # AL=0x76, AF=0 CF=0 + ( 0x16, 0x01 ), # AL=0x76, AF=0 CF=1 + ( 0x70, 0x10 ), # AL=0x76, AF=1 CF=0 + ( 0x10, 0x11 ), # AL=0x76, AF=1 CF=1 + ( 0x77, 0x04 ), # AL=0x77, AF=0 CF=0 + ( 0x17, 0x05 ), # AL=0x77, AF=0 CF=1 + ( 0x71, 0x14 ), # AL=0x77, AF=1 CF=0 + ( 0x11, 0x15 ), # AL=0x77, AF=1 CF=1 + ( 0x78, 0x04 ), # AL=0x78, AF=0 CF=0 + ( 0x18, 0x05 ), # AL=0x78, AF=0 CF=1 + ( 0x72, 0x14 ), # AL=0x78, AF=1 CF=0 + ( 0x12, 0x15 ), # AL=0x78, AF=1 CF=1 + ( 0x79, 0x00 ), # AL=0x79, AF=0 CF=0 + ( 0x19, 0x01 ), # AL=0x79, AF=0 CF=1 + ( 0x73, 0x10 ), # AL=0x79, AF=1 CF=0 + ( 0x13, 0x11 ), # AL=0x79, AF=1 CF=1 + ( 0x74, 0x14 ), # AL=0x7a, AF=0 CF=0 + ( 0x14, 0x15 ), # AL=0x7a, AF=0 CF=1 + ( 0x74, 0x14 ), # AL=0x7a, AF=1 CF=0 + ( 0x14, 0x15 ), # AL=0x7a, AF=1 CF=1 + ( 0x75, 0x10 ), # AL=0x7b, AF=0 CF=0 + ( 0x15, 0x11 ), # AL=0x7b, AF=0 CF=1 + ( 0x75, 0x10 ), # AL=0x7b, AF=1 CF=0 + ( 0x15, 0x11 ), # AL=0x7b, AF=1 CF=1 + ( 0x76, 0x10 ), # AL=0x7c, AF=0 CF=0 + ( 0x16, 0x11 ), # AL=0x7c, AF=0 CF=1 + ( 0x76, 0x10 ), # AL=0x7c, AF=1 CF=0 + ( 0x16, 0x11 ), # AL=0x7c, AF=1 CF=1 + ( 0x77, 0x14 ), # AL=0x7d, AF=0 CF=0 + ( 0x17, 0x15 ), # AL=0x7d, AF=0 CF=1 + ( 0x77, 0x14 ), # AL=0x7d, AF=1 CF=0 + ( 0x17, 0x15 ), # AL=0x7d, AF=1 CF=1 + ( 0x78, 0x14 ), # AL=0x7e, AF=0 CF=0 + ( 0x18, 0x15 ), # AL=0x7e, AF=0 CF=1 + ( 0x78, 0x14 ), # AL=0x7e, AF=1 CF=0 + ( 0x18, 0x15 ), # AL=0x7e, AF=1 CF=1 + ( 0x79, 0x10 ), # AL=0x7f, AF=0 CF=0 + ( 0x19, 0x11 ), # AL=0x7f, AF=0 CF=1 + ( 0x79, 0x10 ), # AL=0x7f, AF=1 CF=0 + ( 0x19, 0x11 ), # AL=0x7f, AF=1 CF=1 + ( 0x80, 0x80 ), # AL=0x80, AF=0 CF=0 + ( 0x20, 0x01 ), # AL=0x80, AF=0 CF=1 + ( 0x7a, 0x10 ), # AL=0x80, AF=1 CF=0 + ( 0x1a, 0x11 ), # AL=0x80, AF=1 CF=1 + ( 0x81, 0x84 ), # AL=0x81, AF=0 CF=0 + ( 0x21, 0x05 ), # AL=0x81, AF=0 CF=1 + ( 0x7b, 0x14 ), # AL=0x81, AF=1 CF=0 + ( 0x1b, 0x15 ), # AL=0x81, AF=1 CF=1 + ( 0x82, 0x84 ), # AL=0x82, AF=0 CF=0 + ( 0x22, 0x05 ), # AL=0x82, AF=0 CF=1 + ( 0x7c, 0x10 ), # AL=0x82, AF=1 CF=0 + ( 0x1c, 0x11 ), # AL=0x82, AF=1 CF=1 + ( 0x83, 0x80 ), # AL=0x83, AF=0 CF=0 + ( 0x23, 0x01 ), # AL=0x83, AF=0 CF=1 + ( 0x7d, 0x14 ), # AL=0x83, AF=1 CF=0 + ( 0x1d, 0x15 ), # AL=0x83, AF=1 CF=1 + ( 0x84, 0x84 ), # AL=0x84, AF=0 CF=0 + ( 0x24, 0x05 ), # AL=0x84, AF=0 CF=1 + ( 0x7e, 0x14 ), # AL=0x84, AF=1 CF=0 + ( 0x1e, 0x15 ), # AL=0x84, AF=1 CF=1 + ( 0x85, 0x80 ), # AL=0x85, AF=0 CF=0 + ( 0x25, 0x01 ), # AL=0x85, AF=0 CF=1 + ( 0x7f, 0x10 ), # AL=0x85, AF=1 CF=0 + ( 0x1f, 0x11 ), # AL=0x85, AF=1 CF=1 + ( 0x86, 0x80 ), # AL=0x86, AF=0 CF=0 + ( 0x26, 0x01 ), # AL=0x86, AF=0 CF=1 + ( 0x80, 0x90 ), # AL=0x86, AF=1 CF=0 + ( 0x20, 0x11 ), # AL=0x86, AF=1 CF=1 + ( 0x87, 0x84 ), # AL=0x87, AF=0 CF=0 + ( 0x27, 0x05 ), # AL=0x87, AF=0 CF=1 + ( 0x81, 0x94 ), # AL=0x87, AF=1 CF=0 + ( 0x21, 0x15 ), # AL=0x87, AF=1 CF=1 + ( 0x88, 0x84 ), # AL=0x88, AF=0 CF=0 + ( 0x28, 0x05 ), # AL=0x88, AF=0 CF=1 + ( 0x82, 0x94 ), # AL=0x88, AF=1 CF=0 + ( 0x22, 0x15 ), # AL=0x88, AF=1 CF=1 + ( 0x89, 0x80 ), # AL=0x89, AF=0 CF=0 + ( 0x29, 0x01 ), # AL=0x89, AF=0 CF=1 + ( 0x83, 0x90 ), # AL=0x89, AF=1 CF=0 + ( 0x23, 0x11 ), # AL=0x89, AF=1 CF=1 + ( 0x84, 0x94 ), # AL=0x8a, AF=0 CF=0 + ( 0x24, 0x15 ), # AL=0x8a, AF=0 CF=1 + ( 0x84, 0x94 ), # AL=0x8a, AF=1 CF=0 + ( 0x24, 0x15 ), # AL=0x8a, AF=1 CF=1 + ( 0x85, 0x90 ), # AL=0x8b, AF=0 CF=0 + ( 0x25, 0x11 ), # AL=0x8b, AF=0 CF=1 + ( 0x85, 0x90 ), # AL=0x8b, AF=1 CF=0 + ( 0x25, 0x11 ), # AL=0x8b, AF=1 CF=1 + ( 0x86, 0x90 ), # AL=0x8c, AF=0 CF=0 + ( 0x26, 0x11 ), # AL=0x8c, AF=0 CF=1 + ( 0x86, 0x90 ), # AL=0x8c, AF=1 CF=0 + ( 0x26, 0x11 ), # AL=0x8c, AF=1 CF=1 + ( 0x87, 0x94 ), # AL=0x8d, AF=0 CF=0 + ( 0x27, 0x15 ), # AL=0x8d, AF=0 CF=1 + ( 0x87, 0x94 ), # AL=0x8d, AF=1 CF=0 + ( 0x27, 0x15 ), # AL=0x8d, AF=1 CF=1 + ( 0x88, 0x94 ), # AL=0x8e, AF=0 CF=0 + ( 0x28, 0x15 ), # AL=0x8e, AF=0 CF=1 + ( 0x88, 0x94 ), # AL=0x8e, AF=1 CF=0 + ( 0x28, 0x15 ), # AL=0x8e, AF=1 CF=1 + ( 0x89, 0x90 ), # AL=0x8f, AF=0 CF=0 + ( 0x29, 0x11 ), # AL=0x8f, AF=0 CF=1 + ( 0x89, 0x90 ), # AL=0x8f, AF=1 CF=0 + ( 0x29, 0x11 ), # AL=0x8f, AF=1 CF=1 + ( 0x90, 0x84 ), # AL=0x90, AF=0 CF=0 + ( 0x30, 0x05 ), # AL=0x90, AF=0 CF=1 + ( 0x8a, 0x90 ), # AL=0x90, AF=1 CF=0 + ( 0x2a, 0x11 ), # AL=0x90, AF=1 CF=1 + ( 0x91, 0x80 ), # AL=0x91, AF=0 CF=0 + ( 0x31, 0x01 ), # AL=0x91, AF=0 CF=1 + ( 0x8b, 0x94 ), # AL=0x91, AF=1 CF=0 + ( 0x2b, 0x15 ), # AL=0x91, AF=1 CF=1 + ( 0x92, 0x80 ), # AL=0x92, AF=0 CF=0 + ( 0x32, 0x01 ), # AL=0x92, AF=0 CF=1 + ( 0x8c, 0x90 ), # AL=0x92, AF=1 CF=0 + ( 0x2c, 0x11 ), # AL=0x92, AF=1 CF=1 + ( 0x93, 0x84 ), # AL=0x93, AF=0 CF=0 + ( 0x33, 0x05 ), # AL=0x93, AF=0 CF=1 + ( 0x8d, 0x94 ), # AL=0x93, AF=1 CF=0 + ( 0x2d, 0x15 ), # AL=0x93, AF=1 CF=1 + ( 0x94, 0x80 ), # AL=0x94, AF=0 CF=0 + ( 0x34, 0x01 ), # AL=0x94, AF=0 CF=1 + ( 0x8e, 0x94 ), # AL=0x94, AF=1 CF=0 + ( 0x2e, 0x15 ), # AL=0x94, AF=1 CF=1 + ( 0x95, 0x84 ), # AL=0x95, AF=0 CF=0 + ( 0x35, 0x05 ), # AL=0x95, AF=0 CF=1 + ( 0x8f, 0x90 ), # AL=0x95, AF=1 CF=0 + ( 0x2f, 0x11 ), # AL=0x95, AF=1 CF=1 + ( 0x96, 0x84 ), # AL=0x96, AF=0 CF=0 + ( 0x36, 0x05 ), # AL=0x96, AF=0 CF=1 + ( 0x90, 0x94 ), # AL=0x96, AF=1 CF=0 + ( 0x30, 0x15 ), # AL=0x96, AF=1 CF=1 + ( 0x97, 0x80 ), # AL=0x97, AF=0 CF=0 + ( 0x37, 0x01 ), # AL=0x97, AF=0 CF=1 + ( 0x91, 0x90 ), # AL=0x97, AF=1 CF=0 + ( 0x31, 0x11 ), # AL=0x97, AF=1 CF=1 + ( 0x98, 0x80 ), # AL=0x98, AF=0 CF=0 + ( 0x38, 0x01 ), # AL=0x98, AF=0 CF=1 + ( 0x92, 0x90 ), # AL=0x98, AF=1 CF=0 + ( 0x32, 0x11 ), # AL=0x98, AF=1 CF=1 + ( 0x99, 0x84 ), # AL=0x99, AF=0 CF=0 + ( 0x39, 0x05 ), # AL=0x99, AF=0 CF=1 + ( 0x93, 0x94 ), # AL=0x99, AF=1 CF=0 + ( 0x33, 0x15 ), # AL=0x99, AF=1 CF=1 + ( 0x34, 0x11 ), # AL=0x9a, AF=0 CF=0 + ( 0x34, 0x11 ), # AL=0x9a, AF=0 CF=1 + ( 0x34, 0x11 ), # AL=0x9a, AF=1 CF=0 + ( 0x34, 0x11 ), # AL=0x9a, AF=1 CF=1 + ( 0x35, 0x15 ), # AL=0x9b, AF=0 CF=0 + ( 0x35, 0x15 ), # AL=0x9b, AF=0 CF=1 + ( 0x35, 0x15 ), # AL=0x9b, AF=1 CF=0 + ( 0x35, 0x15 ), # AL=0x9b, AF=1 CF=1 + ( 0x36, 0x15 ), # AL=0x9c, AF=0 CF=0 + ( 0x36, 0x15 ), # AL=0x9c, AF=0 CF=1 + ( 0x36, 0x15 ), # AL=0x9c, AF=1 CF=0 + ( 0x36, 0x15 ), # AL=0x9c, AF=1 CF=1 + ( 0x37, 0x11 ), # AL=0x9d, AF=0 CF=0 + ( 0x37, 0x11 ), # AL=0x9d, AF=0 CF=1 + ( 0x37, 0x11 ), # AL=0x9d, AF=1 CF=0 + ( 0x37, 0x11 ), # AL=0x9d, AF=1 CF=1 + ( 0x38, 0x11 ), # AL=0x9e, AF=0 CF=0 + ( 0x38, 0x11 ), # AL=0x9e, AF=0 CF=1 + ( 0x38, 0x11 ), # AL=0x9e, AF=1 CF=0 + ( 0x38, 0x11 ), # AL=0x9e, AF=1 CF=1 + ( 0x39, 0x15 ), # AL=0x9f, AF=0 CF=0 + ( 0x39, 0x15 ), # AL=0x9f, AF=0 CF=1 + ( 0x39, 0x15 ), # AL=0x9f, AF=1 CF=0 + ( 0x39, 0x15 ), # AL=0x9f, AF=1 CF=1 + ( 0x40, 0x01 ), # AL=0xa0, AF=0 CF=0 + ( 0x40, 0x01 ), # AL=0xa0, AF=0 CF=1 + ( 0x3a, 0x15 ), # AL=0xa0, AF=1 CF=0 + ( 0x3a, 0x15 ), # AL=0xa0, AF=1 CF=1 + ( 0x41, 0x05 ), # AL=0xa1, AF=0 CF=0 + ( 0x41, 0x05 ), # AL=0xa1, AF=0 CF=1 + ( 0x3b, 0x11 ), # AL=0xa1, AF=1 CF=0 + ( 0x3b, 0x11 ), # AL=0xa1, AF=1 CF=1 + ( 0x42, 0x05 ), # AL=0xa2, AF=0 CF=0 + ( 0x42, 0x05 ), # AL=0xa2, AF=0 CF=1 + ( 0x3c, 0x15 ), # AL=0xa2, AF=1 CF=0 + ( 0x3c, 0x15 ), # AL=0xa2, AF=1 CF=1 + ( 0x43, 0x01 ), # AL=0xa3, AF=0 CF=0 + ( 0x43, 0x01 ), # AL=0xa3, AF=0 CF=1 + ( 0x3d, 0x11 ), # AL=0xa3, AF=1 CF=0 + ( 0x3d, 0x11 ), # AL=0xa3, AF=1 CF=1 + ( 0x44, 0x05 ), # AL=0xa4, AF=0 CF=0 + ( 0x44, 0x05 ), # AL=0xa4, AF=0 CF=1 + ( 0x3e, 0x11 ), # AL=0xa4, AF=1 CF=0 + ( 0x3e, 0x11 ), # AL=0xa4, AF=1 CF=1 + ( 0x45, 0x01 ), # AL=0xa5, AF=0 CF=0 + ( 0x45, 0x01 ), # AL=0xa5, AF=0 CF=1 + ( 0x3f, 0x15 ), # AL=0xa5, AF=1 CF=0 + ( 0x3f, 0x15 ), # AL=0xa5, AF=1 CF=1 + ( 0x46, 0x01 ), # AL=0xa6, AF=0 CF=0 + ( 0x46, 0x01 ), # AL=0xa6, AF=0 CF=1 + ( 0x40, 0x11 ), # AL=0xa6, AF=1 CF=0 + ( 0x40, 0x11 ), # AL=0xa6, AF=1 CF=1 + ( 0x47, 0x05 ), # AL=0xa7, AF=0 CF=0 + ( 0x47, 0x05 ), # AL=0xa7, AF=0 CF=1 + ( 0x41, 0x15 ), # AL=0xa7, AF=1 CF=0 + ( 0x41, 0x15 ), # AL=0xa7, AF=1 CF=1 + ( 0x48, 0x05 ), # AL=0xa8, AF=0 CF=0 + ( 0x48, 0x05 ), # AL=0xa8, AF=0 CF=1 + ( 0x42, 0x15 ), # AL=0xa8, AF=1 CF=0 + ( 0x42, 0x15 ), # AL=0xa8, AF=1 CF=1 + ( 0x49, 0x01 ), # AL=0xa9, AF=0 CF=0 + ( 0x49, 0x01 ), # AL=0xa9, AF=0 CF=1 + ( 0x43, 0x11 ), # AL=0xa9, AF=1 CF=0 + ( 0x43, 0x11 ), # AL=0xa9, AF=1 CF=1 + ( 0x44, 0x15 ), # AL=0xaa, AF=0 CF=0 + ( 0x44, 0x15 ), # AL=0xaa, AF=0 CF=1 + ( 0x44, 0x15 ), # AL=0xaa, AF=1 CF=0 + ( 0x44, 0x15 ), # AL=0xaa, AF=1 CF=1 + ( 0x45, 0x11 ), # AL=0xab, AF=0 CF=0 + ( 0x45, 0x11 ), # AL=0xab, AF=0 CF=1 + ( 0x45, 0x11 ), # AL=0xab, AF=1 CF=0 + ( 0x45, 0x11 ), # AL=0xab, AF=1 CF=1 + ( 0x46, 0x11 ), # AL=0xac, AF=0 CF=0 + ( 0x46, 0x11 ), # AL=0xac, AF=0 CF=1 + ( 0x46, 0x11 ), # AL=0xac, AF=1 CF=0 + ( 0x46, 0x11 ), # AL=0xac, AF=1 CF=1 + ( 0x47, 0x15 ), # AL=0xad, AF=0 CF=0 + ( 0x47, 0x15 ), # AL=0xad, AF=0 CF=1 + ( 0x47, 0x15 ), # AL=0xad, AF=1 CF=0 + ( 0x47, 0x15 ), # AL=0xad, AF=1 CF=1 + ( 0x48, 0x15 ), # AL=0xae, AF=0 CF=0 + ( 0x48, 0x15 ), # AL=0xae, AF=0 CF=1 + ( 0x48, 0x15 ), # AL=0xae, AF=1 CF=0 + ( 0x48, 0x15 ), # AL=0xae, AF=1 CF=1 + ( 0x49, 0x11 ), # AL=0xaf, AF=0 CF=0 + ( 0x49, 0x11 ), # AL=0xaf, AF=0 CF=1 + ( 0x49, 0x11 ), # AL=0xaf, AF=1 CF=0 + ( 0x49, 0x11 ), # AL=0xaf, AF=1 CF=1 + ( 0x50, 0x05 ), # AL=0xb0, AF=0 CF=0 + ( 0x50, 0x05 ), # AL=0xb0, AF=0 CF=1 + ( 0x4a, 0x11 ), # AL=0xb0, AF=1 CF=0 + ( 0x4a, 0x11 ), # AL=0xb0, AF=1 CF=1 + ( 0x51, 0x01 ), # AL=0xb1, AF=0 CF=0 + ( 0x51, 0x01 ), # AL=0xb1, AF=0 CF=1 + ( 0x4b, 0x15 ), # AL=0xb1, AF=1 CF=0 + ( 0x4b, 0x15 ), # AL=0xb1, AF=1 CF=1 + ( 0x52, 0x01 ), # AL=0xb2, AF=0 CF=0 + ( 0x52, 0x01 ), # AL=0xb2, AF=0 CF=1 + ( 0x4c, 0x11 ), # AL=0xb2, AF=1 CF=0 + ( 0x4c, 0x11 ), # AL=0xb2, AF=1 CF=1 + ( 0x53, 0x05 ), # AL=0xb3, AF=0 CF=0 + ( 0x53, 0x05 ), # AL=0xb3, AF=0 CF=1 + ( 0x4d, 0x15 ), # AL=0xb3, AF=1 CF=0 + ( 0x4d, 0x15 ), # AL=0xb3, AF=1 CF=1 + ( 0x54, 0x01 ), # AL=0xb4, AF=0 CF=0 + ( 0x54, 0x01 ), # AL=0xb4, AF=0 CF=1 + ( 0x4e, 0x15 ), # AL=0xb4, AF=1 CF=0 + ( 0x4e, 0x15 ), # AL=0xb4, AF=1 CF=1 + ( 0x55, 0x05 ), # AL=0xb5, AF=0 CF=0 + ( 0x55, 0x05 ), # AL=0xb5, AF=0 CF=1 + ( 0x4f, 0x11 ), # AL=0xb5, AF=1 CF=0 + ( 0x4f, 0x11 ), # AL=0xb5, AF=1 CF=1 + ( 0x56, 0x05 ), # AL=0xb6, AF=0 CF=0 + ( 0x56, 0x05 ), # AL=0xb6, AF=0 CF=1 + ( 0x50, 0x15 ), # AL=0xb6, AF=1 CF=0 + ( 0x50, 0x15 ), # AL=0xb6, AF=1 CF=1 + ( 0x57, 0x01 ), # AL=0xb7, AF=0 CF=0 + ( 0x57, 0x01 ), # AL=0xb7, AF=0 CF=1 + ( 0x51, 0x11 ), # AL=0xb7, AF=1 CF=0 + ( 0x51, 0x11 ), # AL=0xb7, AF=1 CF=1 + ( 0x58, 0x01 ), # AL=0xb8, AF=0 CF=0 + ( 0x58, 0x01 ), # AL=0xb8, AF=0 CF=1 + ( 0x52, 0x11 ), # AL=0xb8, AF=1 CF=0 + ( 0x52, 0x11 ), # AL=0xb8, AF=1 CF=1 + ( 0x59, 0x05 ), # AL=0xb9, AF=0 CF=0 + ( 0x59, 0x05 ), # AL=0xb9, AF=0 CF=1 + ( 0x53, 0x15 ), # AL=0xb9, AF=1 CF=0 + ( 0x53, 0x15 ), # AL=0xb9, AF=1 CF=1 + ( 0x54, 0x11 ), # AL=0xba, AF=0 CF=0 + ( 0x54, 0x11 ), # AL=0xba, AF=0 CF=1 + ( 0x54, 0x11 ), # AL=0xba, AF=1 CF=0 + ( 0x54, 0x11 ), # AL=0xba, AF=1 CF=1 + ( 0x55, 0x15 ), # AL=0xbb, AF=0 CF=0 + ( 0x55, 0x15 ), # AL=0xbb, AF=0 CF=1 + ( 0x55, 0x15 ), # AL=0xbb, AF=1 CF=0 + ( 0x55, 0x15 ), # AL=0xbb, AF=1 CF=1 + ( 0x56, 0x15 ), # AL=0xbc, AF=0 CF=0 + ( 0x56, 0x15 ), # AL=0xbc, AF=0 CF=1 + ( 0x56, 0x15 ), # AL=0xbc, AF=1 CF=0 + ( 0x56, 0x15 ), # AL=0xbc, AF=1 CF=1 + ( 0x57, 0x11 ), # AL=0xbd, AF=0 CF=0 + ( 0x57, 0x11 ), # AL=0xbd, AF=0 CF=1 + ( 0x57, 0x11 ), # AL=0xbd, AF=1 CF=0 + ( 0x57, 0x11 ), # AL=0xbd, AF=1 CF=1 + ( 0x58, 0x11 ), # AL=0xbe, AF=0 CF=0 + ( 0x58, 0x11 ), # AL=0xbe, AF=0 CF=1 + ( 0x58, 0x11 ), # AL=0xbe, AF=1 CF=0 + ( 0x58, 0x11 ), # AL=0xbe, AF=1 CF=1 + ( 0x59, 0x15 ), # AL=0xbf, AF=0 CF=0 + ( 0x59, 0x15 ), # AL=0xbf, AF=0 CF=1 + ( 0x59, 0x15 ), # AL=0xbf, AF=1 CF=0 + ( 0x59, 0x15 ), # AL=0xbf, AF=1 CF=1 + ( 0x60, 0x05 ), # AL=0xc0, AF=0 CF=0 + ( 0x60, 0x05 ), # AL=0xc0, AF=0 CF=1 + ( 0x5a, 0x15 ), # AL=0xc0, AF=1 CF=0 + ( 0x5a, 0x15 ), # AL=0xc0, AF=1 CF=1 + ( 0x61, 0x01 ), # AL=0xc1, AF=0 CF=0 + ( 0x61, 0x01 ), # AL=0xc1, AF=0 CF=1 + ( 0x5b, 0x11 ), # AL=0xc1, AF=1 CF=0 + ( 0x5b, 0x11 ), # AL=0xc1, AF=1 CF=1 + ( 0x62, 0x01 ), # AL=0xc2, AF=0 CF=0 + ( 0x62, 0x01 ), # AL=0xc2, AF=0 CF=1 + ( 0x5c, 0x15 ), # AL=0xc2, AF=1 CF=0 + ( 0x5c, 0x15 ), # AL=0xc2, AF=1 CF=1 + ( 0x63, 0x05 ), # AL=0xc3, AF=0 CF=0 + ( 0x63, 0x05 ), # AL=0xc3, AF=0 CF=1 + ( 0x5d, 0x11 ), # AL=0xc3, AF=1 CF=0 + ( 0x5d, 0x11 ), # AL=0xc3, AF=1 CF=1 + ( 0x64, 0x01 ), # AL=0xc4, AF=0 CF=0 + ( 0x64, 0x01 ), # AL=0xc4, AF=0 CF=1 + ( 0x5e, 0x11 ), # AL=0xc4, AF=1 CF=0 + ( 0x5e, 0x11 ), # AL=0xc4, AF=1 CF=1 + ( 0x65, 0x05 ), # AL=0xc5, AF=0 CF=0 + ( 0x65, 0x05 ), # AL=0xc5, AF=0 CF=1 + ( 0x5f, 0x15 ), # AL=0xc5, AF=1 CF=0 + ( 0x5f, 0x15 ), # AL=0xc5, AF=1 CF=1 + ( 0x66, 0x05 ), # AL=0xc6, AF=0 CF=0 + ( 0x66, 0x05 ), # AL=0xc6, AF=0 CF=1 + ( 0x60, 0x15 ), # AL=0xc6, AF=1 CF=0 + ( 0x60, 0x15 ), # AL=0xc6, AF=1 CF=1 + ( 0x67, 0x01 ), # AL=0xc7, AF=0 CF=0 + ( 0x67, 0x01 ), # AL=0xc7, AF=0 CF=1 + ( 0x61, 0x11 ), # AL=0xc7, AF=1 CF=0 + ( 0x61, 0x11 ), # AL=0xc7, AF=1 CF=1 + ( 0x68, 0x01 ), # AL=0xc8, AF=0 CF=0 + ( 0x68, 0x01 ), # AL=0xc8, AF=0 CF=1 + ( 0x62, 0x11 ), # AL=0xc8, AF=1 CF=0 + ( 0x62, 0x11 ), # AL=0xc8, AF=1 CF=1 + ( 0x69, 0x05 ), # AL=0xc9, AF=0 CF=0 + ( 0x69, 0x05 ), # AL=0xc9, AF=0 CF=1 + ( 0x63, 0x15 ), # AL=0xc9, AF=1 CF=0 + ( 0x63, 0x15 ), # AL=0xc9, AF=1 CF=1 + ( 0x64, 0x11 ), # AL=0xca, AF=0 CF=0 + ( 0x64, 0x11 ), # AL=0xca, AF=0 CF=1 + ( 0x64, 0x11 ), # AL=0xca, AF=1 CF=0 + ( 0x64, 0x11 ), # AL=0xca, AF=1 CF=1 + ( 0x65, 0x15 ), # AL=0xcb, AF=0 CF=0 + ( 0x65, 0x15 ), # AL=0xcb, AF=0 CF=1 + ( 0x65, 0x15 ), # AL=0xcb, AF=1 CF=0 + ( 0x65, 0x15 ), # AL=0xcb, AF=1 CF=1 + ( 0x66, 0x15 ), # AL=0xcc, AF=0 CF=0 + ( 0x66, 0x15 ), # AL=0xcc, AF=0 CF=1 + ( 0x66, 0x15 ), # AL=0xcc, AF=1 CF=0 + ( 0x66, 0x15 ), # AL=0xcc, AF=1 CF=1 + ( 0x67, 0x11 ), # AL=0xcd, AF=0 CF=0 + ( 0x67, 0x11 ), # AL=0xcd, AF=0 CF=1 + ( 0x67, 0x11 ), # AL=0xcd, AF=1 CF=0 + ( 0x67, 0x11 ), # AL=0xcd, AF=1 CF=1 + ( 0x68, 0x11 ), # AL=0xce, AF=0 CF=0 + ( 0x68, 0x11 ), # AL=0xce, AF=0 CF=1 + ( 0x68, 0x11 ), # AL=0xce, AF=1 CF=0 + ( 0x68, 0x11 ), # AL=0xce, AF=1 CF=1 + ( 0x69, 0x15 ), # AL=0xcf, AF=0 CF=0 + ( 0x69, 0x15 ), # AL=0xcf, AF=0 CF=1 + ( 0x69, 0x15 ), # AL=0xcf, AF=1 CF=0 + ( 0x69, 0x15 ), # AL=0xcf, AF=1 CF=1 + ( 0x70, 0x01 ), # AL=0xd0, AF=0 CF=0 + ( 0x70, 0x01 ), # AL=0xd0, AF=0 CF=1 + ( 0x6a, 0x15 ), # AL=0xd0, AF=1 CF=0 + ( 0x6a, 0x15 ), # AL=0xd0, AF=1 CF=1 + ( 0x71, 0x05 ), # AL=0xd1, AF=0 CF=0 + ( 0x71, 0x05 ), # AL=0xd1, AF=0 CF=1 + ( 0x6b, 0x11 ), # AL=0xd1, AF=1 CF=0 + ( 0x6b, 0x11 ), # AL=0xd1, AF=1 CF=1 + ( 0x72, 0x05 ), # AL=0xd2, AF=0 CF=0 + ( 0x72, 0x05 ), # AL=0xd2, AF=0 CF=1 + ( 0x6c, 0x15 ), # AL=0xd2, AF=1 CF=0 + ( 0x6c, 0x15 ), # AL=0xd2, AF=1 CF=1 + ( 0x73, 0x01 ), # AL=0xd3, AF=0 CF=0 + ( 0x73, 0x01 ), # AL=0xd3, AF=0 CF=1 + ( 0x6d, 0x11 ), # AL=0xd3, AF=1 CF=0 + ( 0x6d, 0x11 ), # AL=0xd3, AF=1 CF=1 + ( 0x74, 0x05 ), # AL=0xd4, AF=0 CF=0 + ( 0x74, 0x05 ), # AL=0xd4, AF=0 CF=1 + ( 0x6e, 0x11 ), # AL=0xd4, AF=1 CF=0 + ( 0x6e, 0x11 ), # AL=0xd4, AF=1 CF=1 + ( 0x75, 0x01 ), # AL=0xd5, AF=0 CF=0 + ( 0x75, 0x01 ), # AL=0xd5, AF=0 CF=1 + ( 0x6f, 0x15 ), # AL=0xd5, AF=1 CF=0 + ( 0x6f, 0x15 ), # AL=0xd5, AF=1 CF=1 + ( 0x76, 0x01 ), # AL=0xd6, AF=0 CF=0 + ( 0x76, 0x01 ), # AL=0xd6, AF=0 CF=1 + ( 0x70, 0x11 ), # AL=0xd6, AF=1 CF=0 + ( 0x70, 0x11 ), # AL=0xd6, AF=1 CF=1 + ( 0x77, 0x05 ), # AL=0xd7, AF=0 CF=0 + ( 0x77, 0x05 ), # AL=0xd7, AF=0 CF=1 + ( 0x71, 0x15 ), # AL=0xd7, AF=1 CF=0 + ( 0x71, 0x15 ), # AL=0xd7, AF=1 CF=1 + ( 0x78, 0x05 ), # AL=0xd8, AF=0 CF=0 + ( 0x78, 0x05 ), # AL=0xd8, AF=0 CF=1 + ( 0x72, 0x15 ), # AL=0xd8, AF=1 CF=0 + ( 0x72, 0x15 ), # AL=0xd8, AF=1 CF=1 + ( 0x79, 0x01 ), # AL=0xd9, AF=0 CF=0 + ( 0x79, 0x01 ), # AL=0xd9, AF=0 CF=1 + ( 0x73, 0x11 ), # AL=0xd9, AF=1 CF=0 + ( 0x73, 0x11 ), # AL=0xd9, AF=1 CF=1 + ( 0x74, 0x15 ), # AL=0xda, AF=0 CF=0 + ( 0x74, 0x15 ), # AL=0xda, AF=0 CF=1 + ( 0x74, 0x15 ), # AL=0xda, AF=1 CF=0 + ( 0x74, 0x15 ), # AL=0xda, AF=1 CF=1 + ( 0x75, 0x11 ), # AL=0xdb, AF=0 CF=0 + ( 0x75, 0x11 ), # AL=0xdb, AF=0 CF=1 + ( 0x75, 0x11 ), # AL=0xdb, AF=1 CF=0 + ( 0x75, 0x11 ), # AL=0xdb, AF=1 CF=1 + ( 0x76, 0x11 ), # AL=0xdc, AF=0 CF=0 + ( 0x76, 0x11 ), # AL=0xdc, AF=0 CF=1 + ( 0x76, 0x11 ), # AL=0xdc, AF=1 CF=0 + ( 0x76, 0x11 ), # AL=0xdc, AF=1 CF=1 + ( 0x77, 0x15 ), # AL=0xdd, AF=0 CF=0 + ( 0x77, 0x15 ), # AL=0xdd, AF=0 CF=1 + ( 0x77, 0x15 ), # AL=0xdd, AF=1 CF=0 + ( 0x77, 0x15 ), # AL=0xdd, AF=1 CF=1 + ( 0x78, 0x15 ), # AL=0xde, AF=0 CF=0 + ( 0x78, 0x15 ), # AL=0xde, AF=0 CF=1 + ( 0x78, 0x15 ), # AL=0xde, AF=1 CF=0 + ( 0x78, 0x15 ), # AL=0xde, AF=1 CF=1 + ( 0x79, 0x11 ), # AL=0xdf, AF=0 CF=0 + ( 0x79, 0x11 ), # AL=0xdf, AF=0 CF=1 + ( 0x79, 0x11 ), # AL=0xdf, AF=1 CF=0 + ( 0x79, 0x11 ), # AL=0xdf, AF=1 CF=1 + ( 0x80, 0x81 ), # AL=0xe0, AF=0 CF=0 + ( 0x80, 0x81 ), # AL=0xe0, AF=0 CF=1 + ( 0x7a, 0x11 ), # AL=0xe0, AF=1 CF=0 + ( 0x7a, 0x11 ), # AL=0xe0, AF=1 CF=1 + ( 0x81, 0x85 ), # AL=0xe1, AF=0 CF=0 + ( 0x81, 0x85 ), # AL=0xe1, AF=0 CF=1 + ( 0x7b, 0x15 ), # AL=0xe1, AF=1 CF=0 + ( 0x7b, 0x15 ), # AL=0xe1, AF=1 CF=1 + ( 0x82, 0x85 ), # AL=0xe2, AF=0 CF=0 + ( 0x82, 0x85 ), # AL=0xe2, AF=0 CF=1 + ( 0x7c, 0x11 ), # AL=0xe2, AF=1 CF=0 + ( 0x7c, 0x11 ), # AL=0xe2, AF=1 CF=1 + ( 0x83, 0x81 ), # AL=0xe3, AF=0 CF=0 + ( 0x83, 0x81 ), # AL=0xe3, AF=0 CF=1 + ( 0x7d, 0x15 ), # AL=0xe3, AF=1 CF=0 + ( 0x7d, 0x15 ), # AL=0xe3, AF=1 CF=1 + ( 0x84, 0x85 ), # AL=0xe4, AF=0 CF=0 + ( 0x84, 0x85 ), # AL=0xe4, AF=0 CF=1 + ( 0x7e, 0x15 ), # AL=0xe4, AF=1 CF=0 + ( 0x7e, 0x15 ), # AL=0xe4, AF=1 CF=1 + ( 0x85, 0x81 ), # AL=0xe5, AF=0 CF=0 + ( 0x85, 0x81 ), # AL=0xe5, AF=0 CF=1 + ( 0x7f, 0x11 ), # AL=0xe5, AF=1 CF=0 + ( 0x7f, 0x11 ), # AL=0xe5, AF=1 CF=1 + ( 0x86, 0x81 ), # AL=0xe6, AF=0 CF=0 + ( 0x86, 0x81 ), # AL=0xe6, AF=0 CF=1 + ( 0x80, 0x91 ), # AL=0xe6, AF=1 CF=0 + ( 0x80, 0x91 ), # AL=0xe6, AF=1 CF=1 + ( 0x87, 0x85 ), # AL=0xe7, AF=0 CF=0 + ( 0x87, 0x85 ), # AL=0xe7, AF=0 CF=1 + ( 0x81, 0x95 ), # AL=0xe7, AF=1 CF=0 + ( 0x81, 0x95 ), # AL=0xe7, AF=1 CF=1 + ( 0x88, 0x85 ), # AL=0xe8, AF=0 CF=0 + ( 0x88, 0x85 ), # AL=0xe8, AF=0 CF=1 + ( 0x82, 0x95 ), # AL=0xe8, AF=1 CF=0 + ( 0x82, 0x95 ), # AL=0xe8, AF=1 CF=1 + ( 0x89, 0x81 ), # AL=0xe9, AF=0 CF=0 + ( 0x89, 0x81 ), # AL=0xe9, AF=0 CF=1 + ( 0x83, 0x91 ), # AL=0xe9, AF=1 CF=0 + ( 0x83, 0x91 ), # AL=0xe9, AF=1 CF=1 + ( 0x84, 0x95 ), # AL=0xea, AF=0 CF=0 + ( 0x84, 0x95 ), # AL=0xea, AF=0 CF=1 + ( 0x84, 0x95 ), # AL=0xea, AF=1 CF=0 + ( 0x84, 0x95 ), # AL=0xea, AF=1 CF=1 + ( 0x85, 0x91 ), # AL=0xeb, AF=0 CF=0 + ( 0x85, 0x91 ), # AL=0xeb, AF=0 CF=1 + ( 0x85, 0x91 ), # AL=0xeb, AF=1 CF=0 + ( 0x85, 0x91 ), # AL=0xeb, AF=1 CF=1 + ( 0x86, 0x91 ), # AL=0xec, AF=0 CF=0 + ( 0x86, 0x91 ), # AL=0xec, AF=0 CF=1 + ( 0x86, 0x91 ), # AL=0xec, AF=1 CF=0 + ( 0x86, 0x91 ), # AL=0xec, AF=1 CF=1 + ( 0x87, 0x95 ), # AL=0xed, AF=0 CF=0 + ( 0x87, 0x95 ), # AL=0xed, AF=0 CF=1 + ( 0x87, 0x95 ), # AL=0xed, AF=1 CF=0 + ( 0x87, 0x95 ), # AL=0xed, AF=1 CF=1 + ( 0x88, 0x95 ), # AL=0xee, AF=0 CF=0 + ( 0x88, 0x95 ), # AL=0xee, AF=0 CF=1 + ( 0x88, 0x95 ), # AL=0xee, AF=1 CF=0 + ( 0x88, 0x95 ), # AL=0xee, AF=1 CF=1 + ( 0x89, 0x91 ), # AL=0xef, AF=0 CF=0 + ( 0x89, 0x91 ), # AL=0xef, AF=0 CF=1 + ( 0x89, 0x91 ), # AL=0xef, AF=1 CF=0 + ( 0x89, 0x91 ), # AL=0xef, AF=1 CF=1 + ( 0x90, 0x85 ), # AL=0xf0, AF=0 CF=0 + ( 0x90, 0x85 ), # AL=0xf0, AF=0 CF=1 + ( 0x8a, 0x91 ), # AL=0xf0, AF=1 CF=0 + ( 0x8a, 0x91 ), # AL=0xf0, AF=1 CF=1 + ( 0x91, 0x81 ), # AL=0xf1, AF=0 CF=0 + ( 0x91, 0x81 ), # AL=0xf1, AF=0 CF=1 + ( 0x8b, 0x95 ), # AL=0xf1, AF=1 CF=0 + ( 0x8b, 0x95 ), # AL=0xf1, AF=1 CF=1 + ( 0x92, 0x81 ), # AL=0xf2, AF=0 CF=0 + ( 0x92, 0x81 ), # AL=0xf2, AF=0 CF=1 + ( 0x8c, 0x91 ), # AL=0xf2, AF=1 CF=0 + ( 0x8c, 0x91 ), # AL=0xf2, AF=1 CF=1 + ( 0x93, 0x85 ), # AL=0xf3, AF=0 CF=0 + ( 0x93, 0x85 ), # AL=0xf3, AF=0 CF=1 + ( 0x8d, 0x95 ), # AL=0xf3, AF=1 CF=0 + ( 0x8d, 0x95 ), # AL=0xf3, AF=1 CF=1 + ( 0x94, 0x81 ), # AL=0xf4, AF=0 CF=0 + ( 0x94, 0x81 ), # AL=0xf4, AF=0 CF=1 + ( 0x8e, 0x95 ), # AL=0xf4, AF=1 CF=0 + ( 0x8e, 0x95 ), # AL=0xf4, AF=1 CF=1 + ( 0x95, 0x85 ), # AL=0xf5, AF=0 CF=0 + ( 0x95, 0x85 ), # AL=0xf5, AF=0 CF=1 + ( 0x8f, 0x91 ), # AL=0xf5, AF=1 CF=0 + ( 0x8f, 0x91 ), # AL=0xf5, AF=1 CF=1 + ( 0x96, 0x85 ), # AL=0xf6, AF=0 CF=0 + ( 0x96, 0x85 ), # AL=0xf6, AF=0 CF=1 + ( 0x90, 0x95 ), # AL=0xf6, AF=1 CF=0 + ( 0x90, 0x95 ), # AL=0xf6, AF=1 CF=1 + ( 0x97, 0x81 ), # AL=0xf7, AF=0 CF=0 + ( 0x97, 0x81 ), # AL=0xf7, AF=0 CF=1 + ( 0x91, 0x91 ), # AL=0xf7, AF=1 CF=0 + ( 0x91, 0x91 ), # AL=0xf7, AF=1 CF=1 + ( 0x98, 0x81 ), # AL=0xf8, AF=0 CF=0 + ( 0x98, 0x81 ), # AL=0xf8, AF=0 CF=1 + ( 0x92, 0x91 ), # AL=0xf8, AF=1 CF=0 + ( 0x92, 0x91 ), # AL=0xf8, AF=1 CF=1 + ( 0x99, 0x85 ), # AL=0xf9, AF=0 CF=0 + ( 0x99, 0x85 ), # AL=0xf9, AF=0 CF=1 + ( 0x93, 0x95 ), # AL=0xf9, AF=1 CF=0 + ( 0x93, 0x95 ), # AL=0xf9, AF=1 CF=1 + ( 0x94, 0x91 ), # AL=0xfa, AF=0 CF=0 + ( 0x94, 0x91 ), # AL=0xfa, AF=0 CF=1 + ( 0x94, 0x91 ), # AL=0xfa, AF=1 CF=0 + ( 0x94, 0x91 ), # AL=0xfa, AF=1 CF=1 + ( 0x95, 0x95 ), # AL=0xfb, AF=0 CF=0 + ( 0x95, 0x95 ), # AL=0xfb, AF=0 CF=1 + ( 0x95, 0x95 ), # AL=0xfb, AF=1 CF=0 + ( 0x95, 0x95 ), # AL=0xfb, AF=1 CF=1 + ( 0x96, 0x95 ), # AL=0xfc, AF=0 CF=0 + ( 0x96, 0x95 ), # AL=0xfc, AF=0 CF=1 + ( 0x96, 0x95 ), # AL=0xfc, AF=1 CF=0 + ( 0x96, 0x95 ), # AL=0xfc, AF=1 CF=1 + ( 0x97, 0x91 ), # AL=0xfd, AF=0 CF=0 + ( 0x97, 0x91 ), # AL=0xfd, AF=0 CF=1 + ( 0x97, 0x91 ), # AL=0xfd, AF=1 CF=0 + ( 0x97, 0x91 ), # AL=0xfd, AF=1 CF=1 + ( 0x98, 0x91 ), # AL=0xfe, AF=0 CF=0 + ( 0x98, 0x91 ), # AL=0xfe, AF=0 CF=1 + ( 0x98, 0x91 ), # AL=0xfe, AF=1 CF=0 + ( 0x98, 0x91 ), # AL=0xfe, AF=1 CF=1 + ( 0x99, 0x95 ), # AL=0xff, AF=0 CF=0 + ( 0x99, 0x95 ), # AL=0xff, AF=0 CF=1 + ( 0x99, 0x95 ), # AL=0xff, AF=1 CF=0 + ( 0x99, 0x95 ), # AL=0xff, AF=1 CF=1 +]; + diff --git a/src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp b/src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp new file mode 100644 index 00000000..4e645a75 --- /dev/null +++ b/src/VBox/VMM/testcase/Instructions/tstVBInsTstR3.cpp @@ -0,0 +1,120 @@ +/* $Id: tstVBInsTstR3.cpp $ */ +/** @file + * Instruction Test Environment - IPRT ring-3 driver. + */ + +/* + * Copyright (C) 2006-2013 Oracle Corporation + * + * This file is part of VirtualBox Open Source Edition (OSE), as + * available from http://www.virtualbox.org. This file is free software; + * you can redistribute it and/or modify it under the terms of the GNU + * General Public License (GPL) as published by the Free Software + * Foundation, in version 2 as it comes in the "COPYING" file of the + * VirtualBox OSE distribution. VirtualBox OSE is distributed in the + * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. + */ + + +/******************************************************************************* +* Header Files * +*******************************************************************************/ +#include <iprt/mem.h> +#include <iprt/string.h> +#include <iprt/test.h> + +#ifdef RT_OS_WINDOWS +# define NO_LOW_MEM +#elif defined(RT_OS_OS2) || defined(RT_OS_HAIKU) +# define NO_LOW_MEM +#else +# include <sys/mman.h> +#endif + + +/******************************************************************************* +* Structures and Typedefs * +*******************************************************************************/ +#if HC_ARCH_BITS == 64 +typedef uint64_t VBINSTSTREG; +#else +typedef uint32_t VBINSTSTREG; +#endif + + +/******************************************************************************* +* Global Variables * +*******************************************************************************/ +RTTEST g_hTest; + + +RT_C_DECLS_BEGIN +extern void *g_pvLow16Mem4K; +extern void *g_pvLow32Mem4K; +DECLASM(void) TestInstrMain(void); + +DECLEXPORT(void) VBInsTstFailure(const char *pszMessage); +DECLEXPORT(void) VBInsTstFailure1(const char *pszFmt, VBINSTSTREG uArg1); +DECLEXPORT(void) VBInsTstFailure2(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2); +DECLEXPORT(void) VBInsTstFailure3(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3); +DECLEXPORT(void) VBInsTstFailure4(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3, VBINSTSTREG uArg4); +RT_C_DECLS_END + + +DECLEXPORT(void) VBInsTstFailure(const char *pszMessage) +{ + RTTestFailed(g_hTest, "%s", pszMessage); +} + +DECLEXPORT(void) VBInsTstFailure1(const char *pszFmt, VBINSTSTREG uArg1) +{ + RTTestFailed(g_hTest, pszFmt, uArg1); +} + + +DECLEXPORT(void) VBInsTstFailure2(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2) +{ + RTTestFailed(g_hTest, pszFmt, uArg1, uArg2); +} + + +DECLEXPORT(void) VBInsTstFailure3(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3) +{ + RTTestFailed(g_hTest, pszFmt, uArg1, uArg2, uArg3); +} + + +DECLEXPORT(void) VBInsTstFailure4(const char *pszFmt, VBINSTSTREG uArg1, VBINSTSTREG uArg2, VBINSTSTREG uArg3, VBINSTSTREG uArg4) +{ + RTTestFailed(g_hTest, pszFmt, uArg1, uArg2, uArg3, uArg4); +} + + + + +int main() +{ + RTEXITCODE rcExit = RTTestInitAndCreate("VBInsTstR3", &g_hTest); + if (rcExit != RTEXITCODE_SUCCESS) + return rcExit; + RTTestBanner(g_hTest); + + int rc = RTMemAllocEx(_4K, 0, RTMEMALLOCEX_FLAGS_16BIT_REACH, &g_pvLow16Mem4K); + if (RT_FAILURE(rc)) + { + RTTestPrintf(g_hTest, RTTESTLVL_ALWAYS, "Could not allocate low 16-bit memory (%Rrc)\n", rc); + g_pvLow16Mem4K = NULL; + } + + rc = RTMemAllocEx(_4K, 0, RTMEMALLOCEX_FLAGS_32BIT_REACH, &g_pvLow32Mem4K); + if (RT_FAILURE(rc)) + { + RTTestPrintf(g_hTest, RTTESTLVL_ALWAYS, "Could not allocate low 32-bit memory (%Rrc)\n", rc); + g_pvLow32Mem4K = NULL; + } + + TestInstrMain(); + + return RTTestSummaryAndDestroy(g_hTest); +} + diff --git a/src/VBox/VMM/testcase/Makefile.kmk b/src/VBox/VMM/testcase/Makefile.kmk index 050728bf..31c20458 100644 --- a/src/VBox/VMM/testcase/Makefile.kmk +++ b/src/VBox/VMM/testcase/Makefile.kmk @@ -4,7 +4,7 @@ # # -# Copyright (C) 2006-2012 Oracle Corporation +# Copyright (C) 2006-2013 Oracle Corporation # # This file is part of VirtualBox Open Source Edition (OSE), as # available from http://www.virtualbox.org. This file is free software; @@ -19,6 +19,13 @@ SUB_DEPTH = ../../../.. include $(KBUILD_PATH)/subheader.kmk # +# Include sub-makefiles. +# +if 0 # Not ready for general consumption yet. + include $(PATH_SUB_CURRENT)/Instructions/Makefile.kmk +endif + +# # Target lists. # PROGRAMS += tstVMStructSize tstAsmStructs @@ -35,7 +42,7 @@ endif ifndef VBOX_ONLY_EXTPACKS_USE_IMPLIBS PROGRAMS += tstGlobalConfig tstInstrEmul ifdef VBOX_WITH_RAW_MODE - PROGRAMS += tstVMM tstVMM-HwAccm + PROGRAMS += tstVMM tstVMM-HM ifneq ($(KBUILD_TARGET),win) PROGRAMS += tstVMMFork endif @@ -255,9 +262,9 @@ ifdef VBOX_WITH_RAW_MODE tstVMM_SOURCES = tstVMM.cpp tstVMM_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) - tstVMM-HwAccm_TEMPLATE = VBOXR3EXE - tstVMM-HwAccm_SOURCES = tstVMM-HwAccm.cpp - tstVMM-HwAccm_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + tstVMM-HM_TEMPLATE = VBOXR3EXE + tstVMM-HM_SOURCES = tstVMM-HM.cpp + tstVMM-HM_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) tstVMMFork_TEMPLATE = VBOXR3EXE tstVMMFork_SOURCES = tstVMMFork.cpp @@ -266,10 +273,11 @@ ifdef VBOX_WITH_RAW_MODE tstMicro_TEMPLATE = VBOXR3EXE tstMicro_SOURCES = tstMicro.cpp tstMicro_LIBS = $(LIB_VMM) $(LIB_REM) $(LIB_RUNTIME) + tstMicro_DEFS = $(if $(VBOX_WITH_RAW_MODE),VBOX_WITH_RAW_MODE,) tstMicroRC_TEMPLATE = VBoxRc tstMicroRC_SOURCES = tstMicroRC.cpp tstMicroRCA.asm - tstMicroRC_DEFS = + tstMicroRC_DEFS = $(if $(VBOX_WITH_RAW_MODE),VBOX_WITH_RAW_MODE,) tstMicroRC_INCS = $(VBOX_PATH_VMM_SRC)/testcase ifeq ($(VBOX_LDR_FMT32),pe) tstMicroRC_LDFLAGS = -Entry:tstMicroRC @@ -395,7 +403,7 @@ $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac: \ $(DEPTH)/include/iprt/x86.mac \ $(VBOX_PATH_VMM_SRC)/include/CPUMInternal.mac \ $(VBOX_PATH_VMM_SRC)/include/TRPMInternal.mac \ - $(VBOX_PATH_VMM_SRC)/include/HWACCMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/HMInternal.mac \ $(VBOX_PATH_VMM_SRC)/include/VMMInternal.mac \ $(VBOX_PATH_VMM_SRC)/testcase/Makefile.kmk \ $(PATH_ROOT)/Config.kmk $(LOCALCFG) $(AUTOCFG) \ @@ -418,11 +426,14 @@ $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.o: \ $(VBOX_VMM_TESTCASE_OUT_DIR)/tstAsmStructsAsm.mac \ $(DEPTH)/include/iprt/asmdefs.mac \ $(DEPTH)/include/VBox/vmm/cpum.mac \ + $(DEPTH)/include/VBox/vmm/hm_vmx.mac \ + $(DEPTH)/include/VBox/vmm/stam.mac \ + $(DEPTH)/include/VBox/vmm/trpm.mac \ $(DEPTH)/include/VBox/vmm/vm.mac \ $(DEPTH)/include/VBox/sup.mac \ $(DEPTH)/include/iprt/x86.mac \ $(VBOX_PATH_VMM_SRC)/include/CPUMInternal.mac \ - $(VBOX_PATH_VMM_SRC)/include/HWACCMInternal.mac \ + $(VBOX_PATH_VMM_SRC)/include/HMInternal.mac \ $(VBOX_PATH_VMM_SRC)/include/VMMInternal.mac \ $(VBOX_PATH_VMM_SRC)/include/VMMSwitcher.mac \ $(VBOX_PATH_VMM_SRC)/testcase/Makefile.kmk \ diff --git a/src/VBox/VMM/testcase/mkdsk.sh b/src/VBox/VMM/testcase/mkdsk.sh index 0e55746d..bf28fc32 100755 --- a/src/VBox/VMM/testcase/mkdsk.sh +++ b/src/VBox/VMM/testcase/mkdsk.sh @@ -1,6 +1,6 @@ #!/bin/sh # -# Copyright (C) 2006-2007 Oracle Corporation +# Copyright (C) 2006-2010 Oracle Corporation # # This file is part of VirtualBox Open Source Edition (OSE), as # available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstAnimate.cpp b/src/VBox/VMM/testcase/tstAnimate.cpp index a80404cf..732e05ca 100644 --- a/src/VBox/VMM/testcase/tstAnimate.cpp +++ b/src/VBox/VMM/testcase/tstAnimate.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2011 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -328,7 +328,7 @@ static DECLCALLBACK(int) loadMem(PVM pVM, RTFILE File, uint64_t *poff) * @returns VBox status code. * @param pVM Pointer to the VM. */ -static DECLCALLBACK(int) cfgmR3CreateDefault(PVM pVM, void *pvUser) +static DECLCALLBACK(int) cfgmR3CreateDefault(PUVM pUVM, PVM pVM, void *pvUser) { uint64_t cbMem = *(uint64_t *)pvUser; int rc; @@ -831,25 +831,26 @@ int main(int argc, char **argv) * Create empty VM. */ PVM pVM; - rc = VMR3Create(1, NULL, NULL, NULL, cfgmR3CreateDefault, &cbMem, &pVM); + PUVM pUVM; + rc = VMR3Create(1, NULL, NULL, NULL, cfgmR3CreateDefault, &cbMem, &pVM, &pUVM); if (RT_SUCCESS(rc)) { /* * Load memory. */ if (FileRawMem != NIL_RTFILE) - rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)loadMem, 3, pVM, FileRawMem, &offRawMem); + rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)loadMem, 3, pVM, FileRawMem, &offRawMem); else - rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)SSMR3Load, - 7, pVM, pszSavedState, (uintptr_t)NULL /*pStreamOps*/, (uintptr_t)NULL /*pvUser*/, - SSMAFTER_DEBUG_IT, (uintptr_t)NULL /*pfnProgress*/, (uintptr_t)NULL /*pvProgressUser*/); + rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)SSMR3Load, + 7, pVM, pszSavedState, (uintptr_t)NULL /*pStreamOps*/, (uintptr_t)NULL /*pvUser*/, + SSMAFTER_DEBUG_IT, (uintptr_t)NULL /*pfnProgress*/, (uintptr_t)NULL /*pvProgressUser*/); if (RT_SUCCESS(rc)) { /* * Load register script. */ if (FileScript != NIL_RTFILE) - rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)scriptRun, 2, pVM, FileScript); + rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)scriptRun, 2, pVM, FileScript); if (RT_SUCCESS(rc)) { if (fPowerOn) @@ -859,7 +860,7 @@ int main(int argc, char **argv) */ if (u32WarpDrive != 100) { - rc = TMR3SetWarpDrive(pVM, u32WarpDrive); + rc = TMR3SetWarpDrive(pUVM, u32WarpDrive); if (RT_FAILURE(rc)) RTPrintf("warning: TMVirtualSetWarpDrive(,%u) -> %Rrc\n", u32WarpDrive, rc); } @@ -877,11 +878,11 @@ int main(int argc, char **argv) #endif if (RT_SUCCESS(rc)) { - rc = EMR3SetExecutionPolicy(pVM, EMEXECPOLICY_RECOMPILE_RING0, true); AssertReleaseRC(rc); - rc = EMR3SetExecutionPolicy(pVM, EMEXECPOLICY_RECOMPILE_RING3, true); AssertReleaseRC(rc); - DBGFR3Info(pVM, "cpumguest", "verbose", NULL); + rc = EMR3SetExecutionPolicy(pUVM, EMEXECPOLICY_RECOMPILE_RING0, true); AssertReleaseRC(rc); + rc = EMR3SetExecutionPolicy(pUVM, EMEXECPOLICY_RECOMPILE_RING3, true); AssertReleaseRC(rc); + DBGFR3Info(pUVM, "cpumguest", "verbose", NULL); if (fPowerOn) - rc = VMR3PowerOn(pVM); + rc = VMR3PowerOn(pUVM); if (RT_SUCCESS(rc)) { RTPrintf("info: VM is running\n"); @@ -901,7 +902,7 @@ int main(int argc, char **argv) * Don't start it, just enter the debugger. */ RTPrintf("info: entering debugger...\n"); - DBGFR3Info(pVM, "cpumguest", "verbose", NULL); + DBGFR3Info(pUVM, "cpumguest", "verbose", NULL); signal(SIGINT, SigInterrupt); while (!g_fSignaled) RTThreadSleep(1000); @@ -917,12 +918,14 @@ int main(int argc, char **argv) /* * Cleanup. */ - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf("tstAnimate: error: failed to destroy vm! rc=%Rrc\n", rc); rcRet++; } + + VMR3ReleaseUVM(pUVM); } else { diff --git a/src/VBox/VMM/testcase/tstAsmStructs.cpp b/src/VBox/VMM/testcase/tstAsmStructs.cpp index 2b5400d8..c17c2108 100644 --- a/src/VBox/VMM/testcase/tstAsmStructs.cpp +++ b/src/VBox/VMM/testcase/tstAsmStructs.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2012 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -22,10 +22,11 @@ #include "CPUMInternal.h" #include <VBox/vmm/trpm.h> #include "TRPMInternal.h" -#include "HWACCMInternal.h" +#include "HMInternal.h" #include "VMMSwitcher.h" #include "VMMInternal.h" #include <VBox/vmm/vm.h> +#include <VBox/vmm/hm_vmx.h> #include "tstHelp.h" #include <stdio.h> diff --git a/src/VBox/VMM/testcase/tstAsmStructsAsm.asm b/src/VBox/VMM/testcase/tstAsmStructsAsm.asm index 95747e6d..2f2ad2b3 100644 --- a/src/VBox/VMM/testcase/tstAsmStructsAsm.asm +++ b/src/VBox/VMM/testcase/tstAsmStructsAsm.asm @@ -7,7 +7,7 @@ ; ; -; Copyright (C) 2006-2007 Oracle Corporation +; Copyright (C) 2006-2013 Oracle Corporation ; ; This file is part of VirtualBox Open Source Edition (OSE), as ; available from http://www.virtualbox.org. This file is free software; @@ -23,11 +23,12 @@ BITS 64 %endif %include "CPUMInternal.mac" -%include "HWACCMInternal.mac" +%include "HMInternal.mac" %include "TRPMInternal.mac" %include "VMMInternal.mac" %include "VBox/vmm/cpum.mac" %include "VBox/vmm/vm.mac" +%include "VBox/vmm/hm_vmx.mac" %include "VBox/sup.mac" %include "VMMSwitcher.mac" %ifdef DO_GLOBALS diff --git a/src/VBox/VMM/testcase/tstCFGM.cpp b/src/VBox/VMM/testcase/tstCFGM.cpp index d34174c0..d95eb245 100644 --- a/src/VBox/VMM/testcase/tstCFGM.cpp +++ b/src/VBox/VMM/testcase/tstCFGM.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -30,143 +30,125 @@ #include <VBox/param.h> #include <iprt/initterm.h> #include <iprt/stream.h> +#include <iprt/mem.h> #include <iprt/string.h> +#include <iprt/test.h> -int main() + +static void doGeneralTests(PCFGMNODE pRoot) { - /* - * Init runtime. - */ - RTR3InitExeNoArguments(RTR3INIT_FLAGS_SUPLIB); + /* test multilevel node creation */ + PCFGMNODE pChild = NULL; + RTTESTI_CHECK_RC_RETV(CFGMR3InsertNode(pRoot, "First/Second/Third//Final", &pChild), VINF_SUCCESS); + RTTESTI_CHECK_RETV(RT_VALID_PTR(pChild)); + RTTESTI_CHECK(CFGMR3GetChild(pRoot, "First/Second/Third/Final") == pChild); /* - * Create empty VM structure and init SSM. + * Boolean queries. */ - PVM pVM; - int rc = SUPR3Init(NULL); - if (RT_SUCCESS(rc)) - rc = SUPR3PageAlloc(RT_ALIGN_Z(sizeof(*pVM), PAGE_SIZE) >> PAGE_SHIFT, (void **)&pVM); - if (RT_FAILURE(rc)) - { - RTPrintf("Fatal error: SUP Failure! rc=%Rrc\n", rc); - return 1; - } + RTTESTI_CHECK_RC(CFGMR3InsertInteger(pChild, "BoolValue", 1), VINF_SUCCESS); + bool f = false; + RTTESTI_CHECK_RC(CFGMR3QueryBool(pChild, "BoolValue", &f), VINF_SUCCESS); + RTTESTI_CHECK(f == true); - static UVM s_UVM; - PUVM pUVM = &s_UVM; - pUVM->pVM = pVM; - pVM->pUVM = pUVM; + RTTESTI_CHECK_RC(CFGMR3QueryBool(pRoot, "BoolValue", &f), VERR_CFGM_VALUE_NOT_FOUND); + RTTESTI_CHECK_RC(CFGMR3QueryBool(NULL, "BoolValue", &f), VERR_CFGM_NO_PARENT); - rc = STAMR3InitUVM(pUVM); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: STAMR3Init failed. rc=%Rrc\n", rc); - return 1; - } + RTTESTI_CHECK_RC(CFGMR3QueryBoolDef(pChild, "ValueNotFound", &f, true), VINF_SUCCESS); + RTTESTI_CHECK(f == true); + RTTESTI_CHECK_RC(CFGMR3QueryBoolDef(pChild, "ValueNotFound", &f, false), VINF_SUCCESS); + RTTESTI_CHECK(f == false); - rc = MMR3InitUVM(pUVM); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: STAMR3Init failed. rc=%Rrc\n", rc); - return 1; - } + RTTESTI_CHECK_RC(CFGMR3QueryBoolDef(NULL, "BoolValue", &f, true), VINF_SUCCESS); + RTTESTI_CHECK(f == true); + RTTESTI_CHECK_RC(CFGMR3QueryBoolDef(NULL, "BoolValue", &f, false), VINF_SUCCESS); + RTTESTI_CHECK(f == false); + +} - rc = CFGMR3Init(pVM, NULL, NULL); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3Init failed. rc=%Rrc\n", rc); - return 1; - } - if (!CFGMR3GetRoot(pVM)) - { - RTPrintf("FAILURE: CFGMR3GetRoot failed\n"); - return 1; - } +static void doTestsOnDefaultValues(PCFGMNODE pRoot) +{ /* integer */ uint64_t u64; - rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &u64); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3QueryU64(,\"RamSize\",) failed. rc=%Rrc\n", rc); - return 1; - } + RTTESTI_CHECK_RC(CFGMR3QueryU64(pRoot, "RamSize", &u64), VINF_SUCCESS); - size_t cb; - rc = CFGMR3QuerySize(CFGMR3GetRoot(pVM), "RamSize", &cb); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3QuerySize(,\"RamSize\",) failed. rc=%Rrc\n", rc); - return 1; - } - if (cb != sizeof(uint64_t)) - { - RTPrintf("FAILURE: Incorrect valuesize %d for \"RamSize\" value.\n", cb); - return 1; - } + size_t cb = 0; + RTTESTI_CHECK_RC(CFGMR3QuerySize(pRoot, "RamSize", &cb), VINF_SUCCESS); + RTTESTI_CHECK(cb == sizeof(uint64_t)); /* string */ char *pszName = NULL; - rc = CFGMR3QueryStringAlloc(CFGMR3GetRoot(pVM), "Name", &pszName); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3QueryStringAlloc(,\"Name\" failed. rc=%Rrc\n", rc); - return 1; - } - - rc = CFGMR3QuerySize(CFGMR3GetRoot(pVM), "Name", &cb); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3QuerySize(,\"RamSize\",) failed. rc=%Rrc\n", rc); - return 1; - } - if (cb != strlen(pszName) + 1) - { - RTPrintf("FAILURE: Incorrect valuesize %d for \"Name\" value '%s'.\n", cb, pszName); - return 1; - } + RTTESTI_CHECK_RC(CFGMR3QueryStringAlloc(pRoot, "Name", &pszName), VINF_SUCCESS); + RTTESTI_CHECK_RC(CFGMR3QuerySize(pRoot, "Name", &cb), VINF_SUCCESS); + RTTESTI_CHECK(cb == strlen(pszName) + 1); MMR3HeapFree(pszName); +} - /* test multilevel node creation */ - PCFGMNODE pChild = NULL; - rc = CFGMR3InsertNode(CFGMR3GetRoot(pVM), "First/Second/Third//Final", &pChild); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3InsertNode(,\"First/Second/Third//Final\" failed. rc=%Rrc\n", rc); - return 1; - } - rc = CFGMR3InsertInteger(pChild, "BoolValue", 1); +static void doInVmmTests(RTTEST hTest) +{ + /* + * Create empty VM structure and init SSM. + */ + int rc = SUPR3Init(NULL); if (RT_FAILURE(rc)) { - RTPrintf("FAILURE: CFGMR3InsertInteger(,\"BoolValue\", 1) failed. rc=%Rrc\n", rc); - return 1; - } - PCFGMNODE pNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "First/Second/Third/Final"); - if (pNode != pChild) - { - RTPrintf("FAILURE: CFGMR3GetChild(,\"First/Second/Third/Final/BoolValue\") failed. pNode=%p expected %p\n", pNode, pChild); - return 1; - } - bool f = false; - rc = CFGMR3QueryBool(pNode, "BoolValue", &f); - if (RT_FAILURE(rc) || !f) - { - RTPrintf("FAILURE: CFGMR3QueryBool(,\"BoolValue\",) failed. rc=%Rrc f=%d\n", rc, f); - return 1; + RTTestSkipped(hTest, "SUPR3Init failed with rc=%Rrc", rc); + return; } + PVM pVM; + RTTESTI_CHECK_RC_RETV(SUPR3PageAlloc(RT_ALIGN_Z(sizeof(*pVM), PAGE_SIZE) >> PAGE_SHIFT, (void **)&pVM), VINF_SUCCESS); + + + PUVM pUVM = (PUVM)RTMemPageAlloc(sizeof(*pUVM)); + pUVM->u32Magic = UVM_MAGIC; + pUVM->pVM = pVM; + pVM->pUVM = pUVM; + + /* + * Do the testing. + */ + RTTESTI_CHECK_RC_RETV(STAMR3InitUVM(pUVM), VINF_SUCCESS); + RTTESTI_CHECK_RC_RETV(MMR3InitUVM(pUVM), VINF_SUCCESS); + RTTESTI_CHECK_RC_RETV(CFGMR3Init(pVM, NULL, NULL), VINF_SUCCESS); + RTTESTI_CHECK_RETV(CFGMR3GetRoot(pVM) != NULL); + + doTestsOnDefaultValues(CFGMR3GetRoot(pVM)); + doGeneralTests(CFGMR3GetRoot(pVM)); + /* done */ - rc = CFGMR3Term(pVM); - if (RT_FAILURE(rc)) - { - RTPrintf("FAILURE: CFGMR3QueryU64(,\"RamSize\" failed. rc=%Rrc\n", rc); - return 1; - } + RTTESTI_CHECK_RC_RETV(CFGMR3Term(pVM), VINF_SUCCESS); +} + + +static void doStandaloneTests(void) +{ + RTTestISub("Standalone"); + PCFGMNODE pRoot;; + RTTESTI_CHECK_RETV((pRoot = CFGMR3CreateTree(NULL)) != NULL); + doGeneralTests(pRoot); + CFGMR3DestroyTree(pRoot); +} - RTPrintf("tstCFGM: SUCCESS\n"); - return rc; +int main() +{ + /* + * Init runtime. + */ + RTTEST hTest; + RTR3InitExeNoArguments(RTR3INIT_FLAGS_SUPLIB); + RTEXITCODE rcExit = RTTestInitAndCreate("tstCFGM", &hTest); + if (rcExit != RTEXITCODE_SUCCESS) + return rcExit; + + doInVmmTests(hTest); + doStandaloneTests(); + + return RTTestSummaryAndDestroy(hTest); } + diff --git a/src/VBox/VMM/testcase/tstCompressionBenchmark.cpp b/src/VBox/VMM/testcase/tstCompressionBenchmark.cpp index cee7fa72..ee8f3794 100644 --- a/src/VBox/VMM/testcase/tstCompressionBenchmark.cpp +++ b/src/VBox/VMM/testcase/tstCompressionBenchmark.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2009 Oracle Corporation + * Copyright (C) 2009-2011 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstGlobalConfig.cpp b/src/VBox/VMM/testcase/tstGlobalConfig.cpp index 9b051d27..8b717443 100644 --- a/src/VBox/VMM/testcase/tstGlobalConfig.cpp +++ b/src/VBox/VMM/testcase/tstGlobalConfig.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2007 Oracle Corporation + * Copyright (C) 2007-2014 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -69,7 +69,7 @@ int main(int argc, char **argv) } if (cch >= sizeof(Req.szName)) { - RTPrintf("syntax error: the name is too long. (max %zu chars)\n", argv[1], sizeof(Req.szName) - 1); + RTPrintf("syntax error: the name '%s' is too long. (max %zu chars)\n", argv[1], sizeof(Req.szName) - 1); return 1; } memcpy(&Req.szName[0], argv[1], cch + 1); diff --git a/src/VBox/VMM/testcase/tstHelp.h b/src/VBox/VMM/testcase/tstHelp.h index f4403d84..1a3bba8f 100644 --- a/src/VBox/VMM/testcase/tstHelp.h +++ b/src/VBox/VMM/testcase/tstHelp.h @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2011 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -67,7 +67,7 @@ RT_C_DECLS_END { \ if (RT_OFFSETOF(strct, member) & ((align) - 1) ) \ { \ - printf("error! %s::%s offset=%#x (%u) expected alignment %x, meaning %#x (%u) off\n", \ + printf("error! %s::%s offset=%#x (%u) expected alignment %#x, meaning %#x (%u) off\n", \ #strct, #member, \ (unsigned)RT_OFFSETOF(strct, member), \ (unsigned)RT_OFFSETOF(strct, member), \ diff --git a/src/VBox/VMM/testcase/tstIEMCheckMc.cpp b/src/VBox/VMM/testcase/tstIEMCheckMc.cpp index bee7fae7..1ae3e8b0 100644 --- a/src/VBox/VMM/testcase/tstIEMCheckMc.cpp +++ b/src/VBox/VMM/testcase/tstIEMCheckMc.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2011 Oracle Corporation + * Copyright (C) 2011-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -33,6 +33,7 @@ *******************************************************************************/ bool volatile g_fRandom; uint8_t volatile g_bRandom; +uint128_t g_u128Zero; /** For hacks. */ @@ -63,6 +64,9 @@ uint8_t volatile g_bRandom; uint8_t iMySeg = (a_iSeg); NOREF(iMySeg); /** @todo const or variable. grr. */ \ } while (0) +#define CHK_CALL_ARG(a_Name, a_iArg) \ + do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; } while (0) + /** @name Other stubs. * @{ */ @@ -97,10 +101,14 @@ typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu); #define IEMOP_HLP_NO_REAL_OR_V86_MODE() do { } while (0) #define IEMOP_HLP_NO_LOCK_PREFIX() do { } while (0) #define IEMOP_HLP_NO_64BIT() do { } while (0) +#define IEMOP_HLP_ONLY_64BIT() do { } while (0) #define IEMOP_HLP_64BIT_OP_SIZE() do { } while (0) #define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0) +#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0) #define IEMOP_HLP_DONE_DECODING() do { } while (0) #define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0) +#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) do { } while (0) +#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) do { } while (0) #define IEMOP_RAISE_DIVIDE_ERROR() VERR_TRPM_ACTIVE_TRAP #define IEMOP_RAISE_INVALID_OPCODE() VERR_TRPM_ACTIVE_TRAP #define IEMOP_RAISE_INVALID_LOCK_PREFIX() VERR_TRPM_ACTIVE_TRAP @@ -133,6 +141,10 @@ typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu); #define IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX(a_fEdx) (g_fRandom) #define IEM_IS_AMD_CPUID_FEATURES_ANY_PRESENT(a_fEdx, a_fEcx) (g_fRandom) #define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(a_fEdx) (g_fRandom) +#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_ECX(a_fEcx) (g_fRandom) +#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX_ON_HOST(a_fEdx) (g_fRandom) +#define IEM_IS_GUEST_CPU_AMD(a_pIemCpu) (g_fRandom) +#define IEM_IS_GUEST_CPU_INTEL(a_pIemCpu) (g_fRandom) #define iemRecalEffOpSize(a_pIemCpu) do { } while (0) @@ -170,6 +182,18 @@ IEMOPMULDIVSIZES g_iemAImpl_div; IEMOPMULDIVSIZES g_iemAImpl_idiv; IEMOPSHIFTDBLSIZES g_iemAImpl_shld; IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; +IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw; +IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd; +IEMOPMEDIAF1L1 g_iemAImpl_punpckldq; +IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq; +IEMOPMEDIAF2 g_iemAImpl_pxor; +IEMOPMEDIAF2 g_iemAImpl_pcmpeqb; +IEMOPMEDIAF2 g_iemAImpl_pcmpeqw; +IEMOPMEDIAF2 g_iemAImpl_pcmpeqd; #define iemAImpl_idiv_u8 ((PFNIEMAIMPLMULDIVU8)0) @@ -250,6 +274,10 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define iemCImpl_callf NULL #define iemCImpl_FarJmp NULL +#define iemAImpl_pshufhw NULL +#define iemAImpl_pshuflw NULL +#define iemAImpl_pshufd NULL + /** @} */ @@ -292,6 +320,9 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_RAISE_DIVIDE_ERROR() return VERR_TRPM_ACTIVE_TRAP #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() do {} while (0) #define IEM_MC_MAYBE_RAISE_FPU_XCPT() do {} while (0) +#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() do {} while (0) +#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() do {} while (0) +#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() do {} while (0) #define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() do {} while (0) #define IEM_MC_LOCAL(a_Type, a_Name) \ @@ -322,7 +353,7 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; NOREF(a_Name) #define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \ RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \ - int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \ + int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_pName)); \ AssertCompile((a_iArg) < cArgs); \ uint32_t a_Name; \ uint32_t *a_pName = &a_Name; \ @@ -436,6 +467,25 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FLIP_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0) #define IEM_MC_CLEAR_FSW_EX() do { } while (0) + +#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); } while (0) +#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); } while (0) +#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); } while (0) + +#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(uint128_t, a_u128Value); } while (0) +#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(uint128_t, a_u128Value); } while (0) +#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t *)((uintptr_t)0); CHK_PTYPE(uint128_t *, a_pu128Dst); } while (0) +#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t const *)((uintptr_t)0); CHK_PTYPE(uint128_t const *, a_pu128Dst); } while (0) +#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); } while (0) + #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) do { CHK_TYPE(uint16_t, a_GCPtrMem16); } while (0) #define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) do { CHK_TYPE(uint32_t, a_GCPtrMem32); } while (0) @@ -445,6 +495,7 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); } while (0) #define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) +#define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U8_DISP(a_u8Dst, a_iSeg, a_GCPtrMem, a_offDisp) \ do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint8_t, a_u8Dst); } while (0) @@ -455,10 +506,6 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \ do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint64_t, a_u64Dst); } while (0) -#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst);} while (0) -#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst);} while (0) -#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst);} while (0) - #define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) @@ -471,7 +518,13 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) -#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0) +#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst);} while (0) +#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst);} while (0) +#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst);} while (0) +#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst);} while (0) +#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst);} while (0) + +#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0) #define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); } while (0) #define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); } while (0) #define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); } while (0) @@ -486,9 +539,12 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); } while (0) #define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); } while (0) #define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); } while (0) +#define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Dst) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst); CHK_SEG_IDX(a_iSeg);} while (0) +#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Dst) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst); CHK_SEG_IDX(a_iSeg);} while (0) #define IEM_MC_PUSH_U16(a_u16Value) do {} while (0) #define IEM_MC_PUSH_U32(a_u32Value) do {} while (0) +#define IEM_MC_PUSH_U32_SREG(a_u32Value) do {} while (0) #define IEM_MC_PUSH_U64(a_u64Value) do {} while (0) #define IEM_MC_POP_U16(a_pu16Value) do {} while (0) #define IEM_MC_POP_U32(a_pu32Value) do {} while (0) @@ -497,25 +553,42 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) do {} while (0) #define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do {} while (0) #define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do {} while (0) -#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0) -#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) do {} while (0) -#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) do {} while (0) -#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) do {} while (0) -#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) do {} while (0) -#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) do { (a_rc) = VINF_SUCCESS; } while (0) -#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return VINF_SUCCESS +#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) do {} while (0) +#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) \ + do { CHK_CALL_ARG(a0, 0); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); } while (0) +#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (a_rc) = VINF_SUCCESS; } while (0) +#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (a_rc) = VINF_SUCCESS; } while (0) +#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) do { } while (0) +#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) \ + do { CHK_CALL_ARG(a0, 0); } while (0) +#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) +#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); } while (0) +#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); } while (0) #define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (VINF_SUCCESS) #define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (VINF_SUCCESS) #define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (VINF_SUCCESS) #define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (VINF_SUCCESS) -#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) do { } while (0) -#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) do { } while (0) -#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a3) do { } while (0) +#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \ + do { CHK_CALL_ARG(a0, 0); } while (0) +#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) #define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { } while (0) #define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { } while (0) #define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { } while (0) @@ -545,6 +618,15 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { } while (0) #define IEM_MC_USED_FPU() do { } while (0) +#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0) +#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0) + #define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (g_fRandom) { #define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) { #define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (g_fRandom) { diff --git a/src/VBox/VMM/testcase/tstInstrEmul.cpp b/src/VBox/VMM/testcase/tstInstrEmul.cpp index 5c74b9d2..3173c48c 100644 --- a/src/VBox/VMM/testcase/tstInstrEmul.cpp +++ b/src/VBox/VMM/testcase/tstInstrEmul.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2014 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -50,7 +50,7 @@ int main(int argc, char **argv) if ( !(eflags & X86_EFL_ZF) || val != UINT64_C(0x200000001)) { - RTPrintf("tstInstrEmul: FAILURE - Lock cmpxchg8b failed the equal case! (val=%x%x)\n", val); + RTPrintf("tstInstrEmul: FAILURE - Lock cmpxchg8b failed the equal case! (val=%RX64)\n", val); return 1; } val = UINT64_C(0x123456789); @@ -59,7 +59,7 @@ int main(int argc, char **argv) || eax != 0x23456789 || edx != 0x1) { - RTPrintf("tstInstrEmul: FAILURE - Lock cmpxchg8b failed the non-equal case! (val=%x%x)\n", val); + RTPrintf("tstInstrEmul: FAILURE - Lock cmpxchg8b failed the non-equal case! (val=%RX64)\n", val); return 1; } RTPrintf("tstInstrEmul: Testing lock cmpxchg instruction emulation - SUCCESS\n"); @@ -73,7 +73,7 @@ int main(int argc, char **argv) if ( !(eflags & X86_EFL_ZF) || val != UINT64_C(0x200000001)) { - RTPrintf("tstInstrEmul: FAILURE - Cmpxchg8b failed the equal case! (val=%x%x)\n", val); + RTPrintf("tstInstrEmul: FAILURE - Cmpxchg8b failed the equal case! (val=%RX64)\n", val); return 1; } val = UINT64_C(0x123456789); @@ -82,7 +82,7 @@ int main(int argc, char **argv) || eax != 0x23456789 || edx != 0x1) { - RTPrintf("tstInstrEmul: FAILURE - Cmpxchg8b failed the non-equal case! (val=%x%x)\n", val); + RTPrintf("tstInstrEmul: FAILURE - Cmpxchg8b failed the non-equal case! (val=%RX64)\n", val); return 1; } RTPrintf("tstInstrEmul: Testing cmpxchg instruction emulation - SUCCESS\n"); diff --git a/src/VBox/VMM/testcase/tstMMHyperHeap.cpp b/src/VBox/VMM/testcase/tstMMHyperHeap.cpp index d4366be2..9dad3590 100644 --- a/src/VBox/VMM/testcase/tstMMHyperHeap.cpp +++ b/src/VBox/VMM/testcase/tstMMHyperHeap.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -85,6 +85,13 @@ int main(int argc, char **argv) return 1; } + rc = CFGMR3Init(pVM, NULL, NULL); + if (RT_FAILURE(rc)) + { + RTPrintf("FAILURE: CFGMR3Init failed. rc=%Rrc\n", rc); + return 1; + } + rc = MMR3Init(pVM); if (RT_FAILURE(rc)) { diff --git a/src/VBox/VMM/testcase/tstMicro.cpp b/src/VBox/VMM/testcase/tstMicro.cpp index 5a3524c2..bebd147e 100644 --- a/src/VBox/VMM/testcase/tstMicro.cpp +++ b/src/VBox/VMM/testcase/tstMicro.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -254,7 +254,7 @@ static DECLCALLBACK(int) doit(PVM pVM) RTPrintf(TESTCASE ": PGMMapModifyPage -> rc=%Rra\n", rc); return rc; } - DBGFR3PagingDumpEx(pVM, 0 /*idCpu*/, DBGFPGDMP_FLAGS_CURRENT_CR3 | DBGFPGDMP_FLAGS_CURRENT_MODE + DBGFR3PagingDumpEx(pVM->pUVM, 0 /*idCpu*/, DBGFPGDMP_FLAGS_CURRENT_CR3 | DBGFPGDMP_FLAGS_CURRENT_MODE | DBGFPGDMP_FLAGS_SHADOW | DBGFPGDMP_FLAGS_HEADER | DBGFPGDMP_FLAGS_PRINT_CR3, 0 /*cr3*/, 0 /*u64FirstAddr*/, UINT64_MAX /*u64LastAddr*/, 99 /*cMaxDepth*/, NULL); @@ -279,6 +279,7 @@ static DECLCALLBACK(int) doit(PVM pVM) } #endif +#ifdef VBOX_WITH_RAW_MODE /* * Do the profiling. */ @@ -316,8 +317,10 @@ static DECLCALLBACK(int) doit(PVM pVM) if (enmTest == TSTMICROTEST_OVERHEAD) pTst->u64Overhead = cMin; } +#endif +#ifdef VBOX_WITH_RAW_MODE /* execute the trap/cycle profiling tests. */ RTPrintf("\n"); PrintHeaderTraps(); @@ -329,7 +332,7 @@ static DECLCALLBACK(int) doit(PVM pVM) rc = VMMR3CallRC(pVM, RCPtrEntry, 2, pTst->RCPtr, enmTest); PrintResultTrap(pTst, enmTest, rc); } - +#endif RTPrintf(TESTCASE ": done!\n"); return VINF_SUCCESS; @@ -346,31 +349,33 @@ int main(int argc, char **argv) * Create empty VM. */ PVM pVM; - int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM, &pUVM); if (RT_SUCCESS(rc)) { /* * Do testing. */ - rc = VMR3ReqCallVoidWait(pVM, VMCPUID_ANY, (PFNRT)doit, 1, pVM); + rc = VMR3ReqCallVoidWaitU(pUVM, VMCPUID_ANY, (PFNRT)doit, 1, pVM); AssertRC(rc); - STAMR3Dump(pVM, "*"); + STAMR3Dump(pUVM, "*"); /* * Cleanup. */ - rc = VMR3PowerOff(pVM); + rc = VMR3PowerOff(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf(TESTCASE ": error: failed to power off vm! rc=%Rrc\n", rc); rcRet++; } - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf(TESTCASE ": error: failed to destroy vm! rc=%Rrc\n", rc); rcRet++; } + VMR3ReleaseUVM(pUVM); } else { diff --git a/src/VBox/VMM/testcase/tstMicro.h b/src/VBox/VMM/testcase/tstMicro.h index 3473c365..dcdcb7bf 100644 --- a/src/VBox/VMM/testcase/tstMicro.h +++ b/src/VBox/VMM/testcase/tstMicro.h @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2010 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstMicro.mac b/src/VBox/VMM/testcase/tstMicro.mac index 92e50ca3..6ff7519d 100644 --- a/src/VBox/VMM/testcase/tstMicro.mac +++ b/src/VBox/VMM/testcase/tstMicro.mac @@ -4,7 +4,7 @@ ; ; -; Copyright (C) 2006-2007 Oracle Corporation +; Copyright (C) 2006-2010 Oracle Corporation ; ; This file is part of VirtualBox Open Source Edition (OSE), as ; available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstMicroRC.cpp b/src/VBox/VMM/testcase/tstMicroRC.cpp index a1a71936..ce5936b0 100644 --- a/src/VBox/VMM/testcase/tstMicroRC.cpp +++ b/src/VBox/VMM/testcase/tstMicroRC.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstMicroRC.def b/src/VBox/VMM/testcase/tstMicroRC.def index 7455a2e7..3ea7f018 100644 --- a/src/VBox/VMM/testcase/tstMicroRC.def +++ b/src/VBox/VMM/testcase/tstMicroRC.def @@ -2,7 +2,7 @@ ; ; VMM Guest Context Micro Benchmark - Definition file. -; Copyright (C) 2006-2007 Oracle Corporation +; Copyright (C) 2006-2010 Oracle Corporation ; ; This file is part of VirtualBox Open Source Edition (OSE), as ; available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstMicroRCA.asm b/src/VBox/VMM/testcase/tstMicroRCA.asm index 785cf4b1..b5606688 100644 --- a/src/VBox/VMM/testcase/tstMicroRCA.asm +++ b/src/VBox/VMM/testcase/tstMicroRCA.asm @@ -4,7 +4,7 @@ ; ; -; Copyright (C) 2006-2007 Oracle Corporation +; Copyright (C) 2006-2012 Oracle Corporation ; ; This file is part of VirtualBox Open Source Edition (OSE), as ; available from http://www.virtualbox.org. This file is free software; diff --git a/src/VBox/VMM/testcase/tstPDMAsyncCompletion.cpp b/src/VBox/VMM/testcase/tstPDMAsyncCompletion.cpp index bf554bea..e51ae5d0 100644 --- a/src/VBox/VMM/testcase/tstPDMAsyncCompletion.cpp +++ b/src/VBox/VMM/testcase/tstPDMAsyncCompletion.cpp @@ -9,7 +9,7 @@ */ /* - * Copyright (C) 2008-2010 Oracle Corporation + * Copyright (C) 2008-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -86,11 +86,10 @@ int main(int argc, char *argv[]) } PVM pVM; - int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM, &pUVM); if (RT_SUCCESS(rc)) { - PPDMASYNCCOMPLETIONTEMPLATE pTemplate; - /* * Little hack to avoid the VM_ASSERT_EMT assertion. */ @@ -101,6 +100,7 @@ int main(int argc, char *argv[]) /* * Create the template. */ + PPDMASYNCCOMPLETIONTEMPLATE pTemplate; rc = PDMR3AsyncCompletionTemplateCreateInternal(pVM, &pTemplate, pfnAsyncTaskCompleted, NULL, "Test"); if (RT_FAILURE(rc)) { @@ -235,8 +235,9 @@ int main(int argc, char *argv[]) PDMR3AsyncCompletionEpClose(pEndpointSrc); } - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); AssertMsg(rc == VINF_SUCCESS, ("%s: Destroying VM failed rc=%Rrc!!\n", __FUNCTION__, rc)); + VMR3ReleaseUVM(pUVM); /* * Clean up. diff --git a/src/VBox/VMM/testcase/tstPDMAsyncCompletionStress.cpp b/src/VBox/VMM/testcase/tstPDMAsyncCompletionStress.cpp index 04b7fb67..4ce72baa 100644 --- a/src/VBox/VMM/testcase/tstPDMAsyncCompletionStress.cpp +++ b/src/VBox/VMM/testcase/tstPDMAsyncCompletionStress.cpp @@ -6,7 +6,7 @@ */ /* - * Copyright (C) 2008-2009 Oracle Corporation + * Copyright (C) 2008-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -574,7 +574,8 @@ int main(int argc, char *argv[]) RTR3InitExe(argc, &argv, RTR3INIT_FLAGS_SUPLIB); PVM pVM; - int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM, &pUVM); if (RT_SUCCESS(rc)) { /* @@ -616,7 +617,7 @@ int main(int argc, char *argv[]) rcRet++; } - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); AssertMsg(rc == VINF_SUCCESS, ("%s: Destroying VM failed rc=%Rrc!!\n", __FUNCTION__, rc)); } else diff --git a/src/VBox/VMM/testcase/tstSSM.cpp b/src/VBox/VMM/testcase/tstSSM.cpp index 3bfc5471..cd9c6fd3 100644 --- a/src/VBox/VMM/testcase/tstSSM.cpp +++ b/src/VBox/VMM/testcase/tstSSM.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -98,13 +98,13 @@ void initBigMem(void) * Execute state save operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. */ -DECLCALLBACK(int) Item01Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) +DECLCALLBACK(int) Item01Save(PVM pVM, PSSMHANDLE pSSM) { uint64_t u64Start = RTTimeNanoTS(); - NOREF(pDevIns); + NOREF(pVM); /* * Test writing some memory block. @@ -181,14 +181,14 @@ DECLCALLBACK(int) Item01Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) * Prepare state load operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. * @param uVersion The data layout version. * @param uPass The data pass. */ -DECLCALLBACK(int) Item01Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) +DECLCALLBACK(int) Item01Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) { - NOREF(pDevIns); NOREF(uPass); + NOREF(pVM); NOREF(uPass); if (uVersion != 0) { RTPrintf("Item01: uVersion=%#x, expected 0\n", uVersion); @@ -277,12 +277,12 @@ DECLCALLBACK(int) Item01Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVers * Execute state save operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. */ -DECLCALLBACK(int) Item02Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) +DECLCALLBACK(int) Item02Save(PVM pVM, PSSMHANDLE pSSM) { - NOREF(pDevIns); + NOREF(pVM); uint64_t u64Start = RTTimeNanoTS(); /* @@ -339,14 +339,14 @@ DECLCALLBACK(int) Item02Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) * Prepare state load operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. * @param uVersion The data layout version. * @param uPass The data pass. */ -DECLCALLBACK(int) Item02Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) +DECLCALLBACK(int) Item02Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) { - NOREF(pDevIns); NOREF(uPass); + NOREF(pVM); NOREF(uPass); if (uVersion != 0) { RTPrintf("Item02: uVersion=%#x, expected 0\n", uVersion); @@ -407,12 +407,12 @@ DECLCALLBACK(int) Item02Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVers * Execute state save operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. */ -DECLCALLBACK(int) Item03Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) +DECLCALLBACK(int) Item03Save(PVM pVM, PSSMHANDLE pSSM) { - NOREF(pDevIns); + NOREF(pVM); uint64_t u64Start = RTTimeNanoTS(); /* @@ -455,14 +455,14 @@ DECLCALLBACK(int) Item03Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) * Prepare state load operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. * @param uVersion The data layout version. * @param uPass The data pass. */ -DECLCALLBACK(int) Item03Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) +DECLCALLBACK(int) Item03Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) { - NOREF(pDevIns); NOREF(uPass); + NOREF(pVM); NOREF(uPass); if (uVersion != 123) { RTPrintf("Item03: uVersion=%#x, expected 123\n", uVersion); @@ -519,12 +519,12 @@ DECLCALLBACK(int) Item03Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVers * Execute state save operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. */ -DECLCALLBACK(int) Item04Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) +DECLCALLBACK(int) Item04Save(PVM pVM, PSSMHANDLE pSSM) { - NOREF(pDevIns); + NOREF(pVM); uint64_t u64Start = RTTimeNanoTS(); /* @@ -563,14 +563,14 @@ DECLCALLBACK(int) Item04Save(PPDMDEVINS pDevIns, PSSMHANDLE pSSM) * Prepare state load operation. * * @returns VBox status code. - * @param pDevIns Device instance of the device which registered the data unit. + * @param pVM The cross context VM handle. * @param pSSM SSM operation handle. * @param uVersion The data layout version. * @param uPass The data pass. */ -DECLCALLBACK(int) Item04Load(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) +DECLCALLBACK(int) Item04Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass) { - NOREF(pDevIns); NOREF(uPass); + NOREF(pVM); NOREF(uPass); if (uVersion != 42) { RTPrintf("Item04: uVersion=%#x, expected 42\n", uVersion); @@ -709,40 +709,40 @@ int main(int argc, char **argv) /* * Register a few callbacks. */ - rc = SSMR3RegisterDevice(pVM, NULL, "SSM Testcase Data Item no.1 (all types)", 1, 0, 256, NULL, - NULL, NULL, NULL, - NULL, Item01Save, NULL, - NULL, Item01Load, NULL); + rc = SSMR3RegisterInternal(pVM, "SSM Testcase Data Item no.1 (all types)", 1, 0, 256, + NULL, NULL, NULL, + NULL, Item01Save, NULL, + NULL, Item01Load, NULL); if (RT_FAILURE(rc)) { RTPrintf("SSMR3Register #1 -> %Rrc\n", rc); return 1; } - rc = SSMR3RegisterDevice(pVM, NULL, "SSM Testcase Data Item no.2 (rand mem)", 2, 0, _1M * 8, NULL, - NULL, NULL, NULL, - NULL, Item02Save, NULL, - NULL, Item02Load, NULL); + rc = SSMR3RegisterInternal(pVM, "SSM Testcase Data Item no.2 (rand mem)", 2, 0, _1M * 8, + NULL, NULL, NULL, + NULL, Item02Save, NULL, + NULL, Item02Load, NULL); if (RT_FAILURE(rc)) { RTPrintf("SSMR3Register #2 -> %Rrc\n", rc); return 1; } - rc = SSMR3RegisterDevice(pVM, NULL, "SSM Testcase Data Item no.3 (big mem)", 0, 123, 512*_1M, NULL, - NULL, NULL, NULL, - NULL, Item03Save, NULL, - NULL, Item03Load, NULL); + rc = SSMR3RegisterInternal(pVM, "SSM Testcase Data Item no.3 (big mem)", 0, 123, 512*_1M, + NULL, NULL, NULL, + NULL, Item03Save, NULL, + NULL, Item03Load, NULL); if (RT_FAILURE(rc)) { RTPrintf("SSMR3Register #3 -> %Rrc\n", rc); return 1; } - rc = SSMR3RegisterDevice(pVM, NULL, "SSM Testcase Data Item no.4 (big zero mem)", 0, 42, 512*_1M, NULL, - NULL, NULL, NULL, - NULL, Item04Save, NULL, - NULL, Item04Load, NULL); + rc = SSMR3RegisterInternal(pVM, "SSM Testcase Data Item no.4 (big zero mem)", 0, 42, 512*_1M, + NULL, NULL, NULL, + NULL, Item04Save, NULL, + NULL, Item04Load, NULL); if (RT_FAILURE(rc)) { RTPrintf("SSMR3Register #4 -> %Rrc\n", rc); diff --git a/src/VBox/VMM/testcase/tstVMM-HwAccm.cpp b/src/VBox/VMM/testcase/tstVMM-HM.cpp index fbecb43b..19d728bf 100644 --- a/src/VBox/VMM/testcase/tstVMM-HwAccm.cpp +++ b/src/VBox/VMM/testcase/tstVMM-HM.cpp @@ -1,10 +1,10 @@ -/* $Id: tstVMM-HwAccm.cpp $ */ +/* $Id: tstVMM-HM.cpp $ */ /** @file * VMM Testcase. */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -33,12 +33,12 @@ /******************************************************************************* * Defined Constants And Macros * *******************************************************************************/ -#define TESTCASE "tstVMM-HwAccm" +#define TESTCASE "tstVMM-Hm" -VMMR3DECL(int) VMMDoHwAccmTest(PVM pVM); +VMMR3DECL(int) VMMDoHmTest(PVM pVM); -static DECLCALLBACK(int) CFGMConstructor(PVM pVM, void *pvUser) +static DECLCALLBACK(int) tstVmmHmConfigConstructor(PUVM pUVM, PVM pVM, void *pvUser) { NOREF(pvUser); @@ -75,7 +75,7 @@ int main(int argc, char **argv) RTPrintf(TESTCASE ": This testcase hits a bunch of breakpoint assertions which\n" TESTCASE ": causes kernel panics on linux regardless of what\n" TESTCASE ": RTAssertDoBreakpoint returns. Only checked AMD-V on linux.\n"); - /** @todo Make tstVMM-HwAccm to cause kernel panics. */ + /** @todo Make tstVMM-Hm to cause kernel panics. */ return 1; /* @@ -83,27 +83,29 @@ int main(int argc, char **argv) */ RTPrintf(TESTCASE ": Initializing...\n"); PVM pVM; - int rc = VMR3Create(1, NULL, NULL, NULL, CFGMConstructor, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(1, NULL, NULL, NULL, tstVmmHmConfigConstructor, NULL, &pVM, &pUVM); if (RT_SUCCESS(rc)) { /* * Do testing. */ RTPrintf(TESTCASE ": Testing...\n"); - rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)VMMDoHwAccmTest, 1, pVM); + rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)VMMDoHmTest, 1, pVM); AssertRC(rc); - STAMR3Dump(pVM, "*"); + STAMR3Dump(pUVM, "*"); /* * Cleanup. */ - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); if (RT_FAILURE(rc)) { RTPrintf(TESTCASE ": error: failed to destroy vm! rc=%d\n", rc); rcRet++; } + VMR3ReleaseUVM(pUVM); } else { diff --git a/src/VBox/VMM/testcase/tstVMM.cpp b/src/VBox/VMM/testcase/tstVMM.cpp index e5ed29a0..2e77560f 100644 --- a/src/VBox/VMM/testcase/tstVMM.cpp +++ b/src/VBox/VMM/testcase/tstVMM.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -54,7 +54,8 @@ static uint32_t g_cCpus = 1; /******************************************************************************* * Internal Functions * *******************************************************************************/ -VMMR3DECL(int) VMMDoTest(PVM pVM); /* Linked into VMM, see ../VMMTests.cpp. */ +VMMR3DECL(int) VMMDoTest(PVM pVM); /* Linked into VMM, see ../VMMTests.cpp. */ +VMMR3DECL(int) VMMDoBruteForceMsrs(PVM pVM); /* Ditto. */ /** Dummy timer callback. */ @@ -139,38 +140,51 @@ DECLCALLBACK(int) tstTMWorker(PVM pVM, RTTEST hTest) /** PDMR3LdrEnumModules callback, see FNPDMR3ENUM. */ static DECLCALLBACK(int) -tstVMMLdrEnum(PVM pVM, const char *pszFilename, const char *pszName, RTUINTPTR ImageBase, size_t cbImage, bool fGC, void *pvUser) +tstVMMLdrEnum(PVM pVM, const char *pszFilename, const char *pszName, RTUINTPTR ImageBase, size_t cbImage, + PDMLDRCTX enmCtx, void *pvUser) { - NOREF(pVM); NOREF(pszFilename); NOREF(fGC); NOREF(pvUser); NOREF(cbImage); + NOREF(pVM); NOREF(pszFilename); NOREF(enmCtx); NOREF(pvUser); NOREF(cbImage); RTPrintf("tstVMM: %RTptr %s\n", ImageBase, pszName); return VINF_SUCCESS; } static DECLCALLBACK(int) -tstVMMConfigConstructor(PVM pVM, void *pvUser) +tstVMMConfigConstructor(PUVM pUVM, PVM pVM, void *pvUser) { NOREF(pvUser); int rc = CFGMR3ConstructDefaultTree(pVM); - if ( RT_SUCCESS(rc) - && g_cCpus > 1) + if (RT_SUCCESS(rc)) { PCFGMNODE pRoot = CFGMR3GetRoot(pVM); - CFGMR3RemoveValue(pRoot, "NumCPUs"); - rc = CFGMR3InsertInteger(pRoot, "NumCPUs", g_cCpus); - RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), ("CFGMR3InsertInteger(pRoot,\"NumCPUs\",) -> %Rrc\n", rc), rc); - - CFGMR3RemoveValue(pRoot, "HwVirtExtForced"); - rc = CFGMR3InsertInteger(pRoot, "HwVirtExtForced", true); - RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), ("CFGMR3InsertInteger(pRoot,\"HwVirtExtForced\",) -> %Rrc\n", rc), rc); - - PCFGMNODE pHwVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt"); - CFGMR3RemoveNode(pHwVirtExt); - rc = CFGMR3InsertNode(pRoot, "HWVirtExt", &pHwVirtExt); - RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), ("CFGMR3InsertNode(pRoot,\"HWVirtExt\",) -> %Rrc\n", rc), rc); - rc = CFGMR3InsertInteger(pHwVirtExt, "Enabled", true); - RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), ("CFGMR3InsertInteger(pHwVirtExt,\"Enabled\",) -> %Rrc\n", rc), rc); - rc = CFGMR3InsertInteger(pHwVirtExt, "64bitEnabled", false); - RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), ("CFGMR3InsertInteger(pHwVirtExt,\"64bitEnabled\",) -> %Rrc\n", rc), rc); + if (g_cCpus < 2) + { + rc = CFGMR3InsertInteger(pRoot, "HMEnabled", false); + RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), + ("CFGMR3InsertInteger(pRoot,\"HMEnabled\",) -> %Rrc\n", rc), rc); + } + else if (g_cCpus > 1) + { + CFGMR3RemoveValue(pRoot, "NumCPUs"); + rc = CFGMR3InsertInteger(pRoot, "NumCPUs", g_cCpus); + RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), + ("CFGMR3InsertInteger(pRoot,\"NumCPUs\",) -> %Rrc\n", rc), rc); + + CFGMR3RemoveValue(pRoot, "HwVirtExtForced"); + rc = CFGMR3InsertInteger(pRoot, "HwVirtExtForced", true); + RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), + ("CFGMR3InsertInteger(pRoot,\"HwVirtExtForced\",) -> %Rrc\n", rc), rc); + PCFGMNODE pHwVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt"); + CFGMR3RemoveNode(pHwVirtExt); + rc = CFGMR3InsertNode(pRoot, "HWVirtExt", &pHwVirtExt); + RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), + ("CFGMR3InsertNode(pRoot,\"HWVirtExt\",) -> %Rrc\n", rc), rc); + rc = CFGMR3InsertInteger(pHwVirtExt, "Enabled", true); + RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), + ("CFGMR3InsertInteger(pHwVirtExt,\"Enabled\",) -> %Rrc\n", rc), rc); + rc = CFGMR3InsertInteger(pHwVirtExt, "64bitEnabled", false); + RTTESTI_CHECK_MSG_RET(RT_SUCCESS(rc), + ("CFGMR3InsertInteger(pHwVirtExt,\"64bitEnabled\",) -> %Rrc\n", rc), rc); + } } return rc; } @@ -181,16 +195,10 @@ int main(int argc, char **argv) /* * Init runtime and the test environment. */ - int rc = RTR3InitExe(argc, &argv, RTR3INIT_FLAGS_SUPLIB); - if (RT_FAILURE(rc)) - return RTMsgInitFailure(rc); RTTEST hTest; - rc = RTTestCreate("tstVMM", &hTest); - if (RT_FAILURE(rc)) - { - RTPrintf("tstVMM: RTTestCreate failed: %Rrc\n", rc); - return 1; - } + RTEXITCODE rcExit = RTTestInitExAndCreate(argc, &argv, RTR3INIT_FLAGS_SUPLIB, "tstVMM", &hTest); + if (rcExit != RTEXITCODE_SUCCESS) + return rcExit; /* * Parse arguments. @@ -202,7 +210,7 @@ int main(int argc, char **argv) }; enum { - kTstVMMTest_VMM, kTstVMMTest_TM + kTstVMMTest_VMM, kTstVMMTest_TM, kTstVMMTest_MSRs } enmTestOpt = kTstVMMTest_VMM; int ch; @@ -222,6 +230,8 @@ int main(int argc, char **argv) enmTestOpt = kTstVMMTest_VMM; else if (!strcmp("tm", ValueUnion.psz)) enmTestOpt = kTstVMMTest_TM; + else if (!strcmp("msr", ValueUnion.psz) || !strcmp("msrs", ValueUnion.psz)) + enmTestOpt = kTstVMMTest_MSRs; else { RTPrintf("tstVMM: unknown test: '%s'\n", ValueUnion.psz); @@ -230,11 +240,11 @@ int main(int argc, char **argv) break; case 'h': - RTPrintf("usage: tstVMM [--cpus|-c cpus] [--test <vmm|tm>]\n"); + RTPrintf("usage: tstVMM [--cpus|-c cpus] [--test <vmm|tm|msr>]\n"); return 1; case 'V': - RTPrintf("$Revision: 78835 $\n"); + RTPrintf("$Revision: 91444 $\n"); return 0; default: @@ -247,7 +257,8 @@ int main(int argc, char **argv) */ RTPrintf(TESTCASE ": Initializing...\n"); PVM pVM; - rc = VMR3Create(g_cCpus, NULL, NULL, NULL, tstVMMConfigConstructor, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(g_cCpus, NULL, NULL, NULL, tstVMMConfigConstructor, NULL, &pVM, &pUVM); if (RT_SUCCESS(rc)) { PDMR3LdrEnumModules(pVM, tstVMMLdrEnum, NULL); @@ -262,9 +273,10 @@ int main(int argc, char **argv) case kTstVMMTest_VMM: { RTTestSub(hTest, "VMM"); - rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)VMMDoTest, 1, pVM); + rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)VMMDoTest, 1, pVM); if (RT_FAILURE(rc)) RTTestFailed(hTest, "VMMDoTest failed: rc=%Rrc\n", rc); + STAMR3Dump(pUVM, "*"); break; } @@ -273,29 +285,43 @@ int main(int argc, char **argv) RTTestSub(hTest, "TM"); for (VMCPUID idCpu = 1; idCpu < g_cCpus; idCpu++) { - rc = VMR3ReqCallNoWait(pVM, idCpu, (PFNRT)tstTMWorker, 2, pVM, hTest); + rc = VMR3ReqCallNoWaitU(pUVM, idCpu, (PFNRT)tstTMWorker, 2, pVM, hTest); if (RT_FAILURE(rc)) RTTestFailed(hTest, "VMR3ReqCall failed: rc=%Rrc\n", rc); } - rc = VMR3ReqCallWait(pVM, 0 /*idDstCpu*/, (PFNRT)tstTMWorker, 2, pVM, hTest); + rc = VMR3ReqCallWaitU(pUVM, 0 /*idDstCpu*/, (PFNRT)tstTMWorker, 2, pVM, hTest); if (RT_FAILURE(rc)) RTTestFailed(hTest, "VMMDoTest failed: rc=%Rrc\n", rc); + STAMR3Dump(pUVM, "*"); break; } - } - STAMR3Dump(pVM, "*"); + case kTstVMMTest_MSRs: + { + RTTestSub(hTest, "MSRs"); + if (g_cCpus == 1) + { + rc = VMR3ReqCallWaitU(pUVM, 0 /*idDstCpu*/, (PFNRT)VMMDoBruteForceMsrs, 1, pVM); + if (RT_FAILURE(rc)) + RTTestFailed(hTest, "VMMDoBruteForceMsrs failed: rc=%Rrc\n", rc); + } + else + RTTestFailed(hTest, "The MSR test can only be run with one VCpu!\n"); + break; + } + } /* * Cleanup. */ - rc = VMR3PowerOff(pVM); + rc = VMR3PowerOff(pUVM); if (RT_FAILURE(rc)) RTTestFailed(hTest, "VMR3PowerOff failed: rc=%Rrc\n", rc); - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); if (RT_FAILURE(rc)) RTTestFailed(hTest, "VMR3Destroy failed: rc=%Rrc\n", rc); + VMR3ReleaseUVM(pUVM); } else RTTestFailed(hTest, "VMR3Create failed: rc=%Rrc\n", rc); diff --git a/src/VBox/VMM/testcase/tstVMMFork.cpp b/src/VBox/VMM/testcase/tstVMMFork.cpp index f1a702c1..b5e429e6 100644 --- a/src/VBox/VMM/testcase/tstVMMFork.cpp +++ b/src/VBox/VMM/testcase/tstVMMFork.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2014 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -66,7 +66,8 @@ int main(int argc, char* argv[]) */ RTPrintf(TESTCASE ": Initializing...\n"); PVM pVM; - int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM, &pUVM); if (RT_SUCCESS(rc)) { /* @@ -131,32 +132,33 @@ int main(int argc, char* argv[]) { RTPrintf(TESTCASE ": fork() returned fine.\n"); RTPrintf(TESTCASE ": testing VM after fork.\n"); - VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)VMMDoTest, 1, pVM); + VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)VMMDoTest, 1, pVM); - STAMR3Dump(pVM, "*"); + STAMR3Dump(pUVM, "*"); } } if (rcErrors > 0) - RTPrintf(TESTCASE ": error: %d error(s) during fork(). Cannot proceed to test the VM.\n"); + RTPrintf(TESTCASE ": error: %d error(s) during fork(). Cannot proceed to test the VM.\n", rcErrors); else RTPrintf(TESTCASE ": fork() and VM test, SUCCESS.\n"); /* * Cleanup. */ - rc = VMR3PowerOff(pVM); + rc = VMR3PowerOff(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf(TESTCASE ": error: failed to power off vm! rc=%Rrc\n", rc); rcErrors++; } - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf(TESTCASE ": error: failed to destroy vm! rc=%Rrc\n", rc); rcErrors++; } + VMR3ReleaseUVM(pUVM); } else { diff --git a/src/VBox/VMM/testcase/tstVMMR0CallHost-1.cpp b/src/VBox/VMM/testcase/tstVMMR0CallHost-1.cpp index 92cb58cc..16616474 100644 --- a/src/VBox/VMM/testcase/tstVMMR0CallHost-1.cpp +++ b/src/VBox/VMM/testcase/tstVMMR0CallHost-1.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -115,7 +115,7 @@ void tst(int iFrom, int iTo, int iInc) for (int i = iFrom, iItr = 0; i != iTo; i += iInc, iItr++) { - int rc = vmmR0CallRing3SetJmp(&g_Jmp, (PFNVMMR0SETJMP)tst2, (PVM)i, 0); + int rc = vmmR0CallRing3SetJmp(&g_Jmp, (PFNVMMR0SETJMP)tst2, (PVM)(uintptr_t)i, 0); RTTESTI_CHECK_MSG_RETV(rc == 0 || rc == 42, ("i=%d rc=%d setjmp; cbFoo=%#x cbFooUsed=%#x\n", i, rc, g_cbFoo, g_cbFooUsed)); #ifdef VMM_R0_SWITCH_STACK @@ -145,13 +145,9 @@ int main() * Init. */ RTTEST hTest; - int rc; - if ( RT_FAILURE(rc = RTR3InitExeNoArguments(0)) - || RT_FAILURE(rc = RTTestCreate("tstVMMR0CallHost-1", &hTest))) - { - RTStrmPrintf(g_pStdErr, "tstVMMR0CallHost-1: Fatal error during init: %Rrc\n", rc); - return 1; - } + RTEXITCODE rcExit = RTTestInitAndCreate("tstVMMR0CallHost-1", &hTest); + if (rcExit != RTEXITCODE_SUCCESS) + return rcExit; RTTestBanner(hTest); g_Jmp.pvSavedStack = (RTR0PTR)RTTestGuardedAllocTail(hTest, VMM_STACK_SIZE); diff --git a/src/VBox/VMM/testcase/tstVMREQ.cpp b/src/VBox/VMM/testcase/tstVMREQ.cpp index 0f557e29..c321246b 100644 --- a/src/VBox/VMM/testcase/tstVMREQ.cpp +++ b/src/VBox/VMM/testcase/tstVMREQ.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -48,9 +48,9 @@ static int g_cErrors = 0; /** * Testings va_list passing in VMSetRuntimeError. */ -static DECLCALLBACK(void) MyAtRuntimeError(PVM pVM, void *pvUser, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va) +static DECLCALLBACK(void) MyAtRuntimeError(PUVM pUVM, void *pvUser, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va) { - NOREF(pVM); + NOREF(pUVM); if (strcmp((const char *)pvUser, "user argument")) { RTPrintf(TESTCASE ": pvUser=%p:{%s}!\n", pvUser, (const char *)pvUser); @@ -85,9 +85,9 @@ static DECLCALLBACK(void) MyAtRuntimeError(PVM pVM, void *pvUser, uint32_t fFlag /** * The function PassVA and PassVA2 calls. */ -static DECLCALLBACK(int) PassVACallback(PVM pVM, unsigned u4K, unsigned u1G, const char *pszFormat, va_list *pva) +static DECLCALLBACK(int) PassVACallback(PUVM pUVM, unsigned u4K, unsigned u1G, const char *pszFormat, va_list *pva) { - NOREF(pVM); + NOREF(pUVM); if (u4K != _4K) { RTPrintf(TESTCASE ": u4K=%#x!\n", u4K); @@ -121,17 +121,17 @@ static DECLCALLBACK(int) PassVACallback(PVM pVM, unsigned u4K, unsigned u1G, con * Functions that tests passing a va_list * argument in a request, * similar to VMSetRuntimeError. */ -static void PassVA2(PVM pVM, const char *pszFormat, va_list va) +static void PassVA2(PUVM pUVM, const char *pszFormat, va_list va) { #if 0 /** @todo test if this is a GCC problem only or also happens with AMD64+VCC80... */ void *pvVA = &va; #else va_list va2; va_copy(va2, va); - void *pvVA = va2; + void *pvVA = &va2; #endif - int rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)PassVACallback, 5, pVM, _4K, _1G, pszFormat, pvVA); + int rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)PassVACallback, 5, pUVM, _4K, _1G, pszFormat, pvVA); NOREF(rc); #if 1 @@ -144,19 +144,19 @@ static void PassVA2(PVM pVM, const char *pszFormat, va_list va) * Functions that tests passing a va_list * argument in a request, * similar to VMSetRuntimeError. */ -static void PassVA(PVM pVM, const char *pszFormat, ...) +static void PassVA(PUVM pUVM, const char *pszFormat, ...) { /* 1st test */ va_list va1; va_start(va1, pszFormat); - int rc = VMR3ReqCallWait(pVM, VMCPUID_ANY, (PFNRT)PassVACallback, 5, pVM, _4K, _1G, pszFormat, &va1); + int rc = VMR3ReqCallWaitU(pUVM, VMCPUID_ANY, (PFNRT)PassVACallback, 5, pUVM, _4K, _1G, pszFormat, &va1); va_end(va1); NOREF(rc); /* 2nd test */ va_list va2; va_start(va2, pszFormat); - PassVA2(pVM, pszFormat, va2); + PassVA2(pUVM, pszFormat, va2); va_end(va2); } @@ -167,7 +167,7 @@ static void PassVA(PVM pVM, const char *pszFormat, ...) static DECLCALLBACK(int) Thread(RTTHREAD hThreadSelf, void *pvUser) { int rc = VINF_SUCCESS; - PVM pVM = (PVM)pvUser; + PUVM pUVM = (PUVM)pvUser; NOREF(hThreadSelf); for (unsigned i = 0; i < 100000; i++) @@ -177,7 +177,7 @@ static DECLCALLBACK(int) Thread(RTTHREAD hThreadSelf, void *pvUser) unsigned iReq; for (iReq = 0; iReq < cReqs; iReq++) { - rc = VMR3ReqAlloc(pVM, &apReq[iReq], VMREQTYPE_INTERNAL, VMCPUID_ANY); + rc = VMR3ReqAlloc(pUVM, &apReq[iReq], VMREQTYPE_INTERNAL, VMCPUID_ANY); if (RT_FAILURE(rc)) { RTPrintf(TESTCASE ": i=%d iReq=%d cReqs=%d rc=%Rrc (alloc)\n", i, iReq, cReqs, rc); @@ -207,18 +207,34 @@ static DECLCALLBACK(int) Thread(RTTHREAD hThreadSelf, void *pvUser) return VINF_SUCCESS; } - +static DECLCALLBACK(int) +tstVMREQConfigConstructor(PUVM pUVM, PVM pVM, void *pvUser) +{ + NOREF(pvUser); + int rc = CFGMR3ConstructDefaultTree(pVM); + if (RT_SUCCESS(rc)) + { + /* Disable HM, otherwise it will fail on machines without unrestricted guest execution + * because the allocation of HM_VTX_TOTAL_DEVHEAP_MEM will fail -- no VMMDev */ + PCFGMNODE pRoot = CFGMR3GetRoot(pVM); + rc = CFGMR3InsertInteger(pRoot, "HMEnabled", false); + if (RT_FAILURE(rc)) + RTPrintf("CFGMR3InsertInteger(pRoot,\"HMEnabled\",) -> %Rrc\n", rc); + } + return rc; +} int main(int argc, char **argv) { RTR3InitExe(argc, &argv, RTR3INIT_FLAGS_SUPLIB); RTPrintf(TESTCASE ": TESTING...\n"); + RTStrmFlush(g_pStdOut); /* * Create empty VM. */ - PVM pVM; - int rc = VMR3Create(1, NULL, NULL, NULL, NULL, NULL, &pVM); + PUVM pUVM; + int rc = VMR3Create(1, NULL, NULL, NULL, tstVMREQConfigConstructor, NULL, NULL, &pUVM); if (RT_SUCCESS(rc)) { /* @@ -226,11 +242,11 @@ int main(int argc, char **argv) */ uint64_t u64StartTS = RTTimeNanoTS(); RTTHREAD Thread0; - rc = RTThreadCreate(&Thread0, Thread, pVM, 0, RTTHREADTYPE_DEFAULT, RTTHREADFLAGS_WAITABLE, "REQ1"); + rc = RTThreadCreate(&Thread0, Thread, pUVM, 0, RTTHREADTYPE_DEFAULT, RTTHREADFLAGS_WAITABLE, "REQ1"); if (RT_SUCCESS(rc)) { RTTHREAD Thread1; - rc = RTThreadCreate(&Thread1, Thread, pVM, 0, RTTHREADTYPE_DEFAULT, RTTHREADFLAGS_WAITABLE, "REQ1"); + rc = RTThreadCreate(&Thread1, Thread, pUVM, 0, RTTHREADTYPE_DEFAULT, RTTHREADFLAGS_WAITABLE, "REQ1"); if (RT_SUCCESS(rc)) { int rcThread1; @@ -266,35 +282,37 @@ int main(int argc, char **argv) } uint64_t u64ElapsedTS = RTTimeNanoTS() - u64StartTS; RTPrintf(TESTCASE ": %llu ns elapsed\n", u64ElapsedTS); + RTStrmFlush(g_pStdOut); /* * Print stats. */ - STAMR3Print(pVM, "/VM/Req/*"); + STAMR3Print(pUVM, "/VM/Req/*"); /* * Testing va_list fun. */ - RTPrintf(TESTCASE ": va_list argument test...\n"); - PassVA(pVM, "hello %s", "world"); - VMR3AtRuntimeErrorRegister(pVM, MyAtRuntimeError, (void *)"user argument"); - VMSetRuntimeError(pVM, 0 /*fFlags*/, "enum", "some %s string", "error"); + RTPrintf(TESTCASE ": va_list argument test...\n"); RTStrmFlush(g_pStdOut); + PassVA(pUVM, "hello %s", "world"); + VMR3AtRuntimeErrorRegister(pUVM, MyAtRuntimeError, (void *)"user argument"); + VMSetRuntimeError(VMR3GetVM(pUVM), 0 /*fFlags*/, "enum", "some %s string", "error"); /* * Cleanup. */ - rc = VMR3PowerOff(pVM); + rc = VMR3PowerOff(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf(TESTCASE ": error: failed to power off vm! rc=%Rrc\n", rc); g_cErrors++; } - rc = VMR3Destroy(pVM); + rc = VMR3Destroy(pUVM); if (!RT_SUCCESS(rc)) { RTPrintf(TESTCASE ": error: failed to destroy vm! rc=%Rrc\n", rc); g_cErrors++; } + VMR3ReleaseUVM(pUVM); } else { diff --git a/src/VBox/VMM/testcase/tstVMStruct.h b/src/VBox/VMM/testcase/tstVMStruct.h index 0e57f946..902b0fd7 100644 --- a/src/VBox/VMM/testcase/tstVMStruct.h +++ b/src/VBox/VMM/testcase/tstVMStruct.h @@ -7,7 +7,7 @@ */ /* - * Copyright (C) 2006-2012 Oracle Corporation + * Copyright (C) 2006-2013 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -31,11 +31,8 @@ GEN_CHECK_OFF(CPUM, CPUFeatures); GEN_CHECK_OFF(CPUM, CPUFeaturesExt); GEN_CHECK_OFF(CPUM, CPUFeaturesExt); - GEN_CHECK_OFF(CPUM, enmHostCpuVendor); - GEN_CHECK_OFF(CPUM, enmGuestCpuVendor); GEN_CHECK_OFF(CPUM, CR4); #ifndef VBOX_FOR_DTRACE_LIB - GEN_CHECK_OFF(CPUM, fSyntheticCpu); GEN_CHECK_OFF(CPUM, u8PortableCpuIdLevel); GEN_CHECK_OFF(CPUM, fPendingRestore); #endif @@ -44,10 +41,6 @@ GEN_CHECK_OFF(CPUM, aGuestCpuIdCentaur); GEN_CHECK_OFF(CPUM, aGuestCpuIdHyper); GEN_CHECK_OFF(CPUM, GuestCpuIdDef); -#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI - GEN_CHECK_OFF(CPUM, pvApicBase); - GEN_CHECK_OFF(CPUM, fApicDisVectors); -#endif GEN_CHECK_SIZE(CPUMCPU); // has .mac GEN_CHECK_OFF(CPUMCPU, Hyper); @@ -62,6 +55,11 @@ GEN_CHECK_OFF(CPUMCPU, fChanged); GEN_CHECK_OFF(CPUMCPU, offCPUM); GEN_CHECK_OFF(CPUMCPU, u32RetCode); +#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI + GEN_CHECK_OFF(CPUMCPU, pvApicBase); + GEN_CHECK_OFF(CPUMCPU, fApicDisVectors); + GEN_CHECK_OFF(CPUMCPU, fX2Apic); +#endif GEN_CHECK_OFF(CPUMCPU, fRawEntered); GEN_CHECK_OFF(CPUMCPU, fRemEntered); @@ -185,6 +183,7 @@ GEN_CHECK_OFF(CPUMCTX, msrCSTAR); GEN_CHECK_OFF(CPUMCTX, msrSFMASK); GEN_CHECK_OFF(CPUMCTX, msrKERNELGSBASE); + GEN_CHECK_OFF(CPUMCTX, msrApicBase); GEN_CHECK_OFF(CPUMCTX, ldtr); GEN_CHECK_OFF(CPUMCTX, tr); #ifndef VBOX_FOR_DTRACE_LIB @@ -217,26 +216,23 @@ GEN_CHECK_OFF(DBGF, DbgEvent); GEN_CHECK_OFF(DBGF, enmVMMCmd); GEN_CHECK_OFF(DBGF, VMMCmdData); - GEN_CHECK_OFF(DBGF, pInfoFirst); - GEN_CHECK_OFF(DBGF, InfoCritSect); - GEN_CHECK_OFF(DBGF, SymbolTree); - GEN_CHECK_OFF(DBGF, pSymbolSpace); - GEN_CHECK_OFF(DBGF, fSymInited); + //GEN_CHECK_OFF(DBGF, pInfoFirst); + //GEN_CHECK_OFF(DBGF, InfoCritSect); GEN_CHECK_OFF(DBGF, cHwBreakpoints); GEN_CHECK_OFF(DBGF, cBreakpoints); GEN_CHECK_OFF(DBGF, aHwBreakpoints); GEN_CHECK_OFF(DBGF, aBreakpoints); - GEN_CHECK_OFF(DBGF, hAsDbLock); - GEN_CHECK_OFF(DBGF, hRegDbLock); - GEN_CHECK_OFF(DBGF, RegSetSpace); - GEN_CHECK_OFF(DBGF, pCurOS); + //GEN_CHECK_OFF(DBGF, hAsDbLock); + //GEN_CHECK_OFF(DBGF, hRegDbLock); + //GEN_CHECK_OFF(DBGF, RegSetSpace); + //GEN_CHECK_OFF(DBGF, pCurOS); GEN_CHECK_SIZE(DBGFEVENT); GEN_CHECK_SIZE(DBGFCPU); GEN_CHECK_OFF(DBGFCPU, iActiveBp); GEN_CHECK_OFF(DBGFCPU, fSingleSteppingRaw); - GEN_CHECK_OFF(DBGFCPU, pGuestRegSet); - GEN_CHECK_OFF(DBGFCPU, pHyperRegSet); + //GEN_CHECK_OFF(DBGFCPU, pGuestRegSet); + //GEN_CHECK_OFF(DBGFCPU, pHyperRegSet); GEN_CHECK_SIZE(EM); GEN_CHECK_OFF(EM, offVM); @@ -274,17 +270,17 @@ GEN_CHECK_OFF(IOM, pTreesRC); GEN_CHECK_OFF(IOM, pTreesR3); GEN_CHECK_OFF(IOM, pTreesR0); - GEN_CHECK_OFF(IOM, pMMIORangeLastR3); - GEN_CHECK_OFF(IOM, pMMIOStatsLastR3); - GEN_CHECK_OFF(IOM, pMMIORangeLastR0); - GEN_CHECK_OFF(IOM, pMMIOStatsLastR0); - GEN_CHECK_OFF(IOM, pMMIORangeLastRC); - GEN_CHECK_OFF(IOM, pMMIOStatsLastRC); - GEN_CHECK_OFF(IOM, pRangeLastReadR0); - GEN_CHECK_OFF(IOM, pRangeLastReadRC); GEN_CHECK_SIZE(IOMCPU); GEN_CHECK_OFF(IOMCPU, DisState); + GEN_CHECK_OFF(IOMCPU, pMMIORangeLastR3); + GEN_CHECK_OFF(IOMCPU, pMMIOStatsLastR3); + GEN_CHECK_OFF(IOMCPU, pMMIORangeLastR0); + GEN_CHECK_OFF(IOMCPU, pMMIOStatsLastR0); + GEN_CHECK_OFF(IOMCPU, pMMIORangeLastRC); + GEN_CHECK_OFF(IOMCPU, pMMIOStatsLastRC); + GEN_CHECK_OFF(IOMCPU, pRangeLastReadR0); + GEN_CHECK_OFF(IOMCPU, pRangeLastReadRC); GEN_CHECK_SIZE(IOMMMIORANGE); GEN_CHECK_OFF(IOMMMIORANGE, GCPhys); @@ -404,8 +400,6 @@ GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnSetIrqR3); GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnRegisterR3); GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnIORegionRegisterR3); - GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnSaveExecR3); - GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnLoadExecR3); GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnFakePCIBIOSR3); GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pDevInsR0); GEN_CHECK_OFF_DOT(PDM, aPciBuses[0].pfnSetIrqR0); @@ -463,7 +457,11 @@ GEN_CHECK_OFF(PDM, pDevHlpQueueR0); GEN_CHECK_OFF(PDM, pDevHlpQueueRC); GEN_CHECK_OFF(PDMCPU, cQueuedCritSectLeaves); - GEN_CHECK_OFF(PDMCPU, apQueuedCritSectsLeaves); + GEN_CHECK_OFF(PDMCPU, apQueuedCritSectLeaves); + GEN_CHECK_OFF(PDMCPU, cQueuedCritSectRwExclLeaves); + GEN_CHECK_OFF(PDMCPU, apQueuedCritSectRwExclLeaves); + GEN_CHECK_OFF(PDMCPU, cQueuedCritSectRwShrdLeaves); + GEN_CHECK_OFF(PDMCPU, apQueuedCritSectRwShrdLeaves); GEN_CHECK_OFF(PDM, pQueueFlushR0); GEN_CHECK_OFF(PDM, pQueueFlushRC); GEN_CHECK_OFF(PDM, StatQueuedCritSectLeaves); @@ -537,6 +535,18 @@ GEN_CHECK_OFF(PDMCRITSECTINT, StatContentionRZUnlock); GEN_CHECK_OFF(PDMCRITSECTINT, StatContentionR3); GEN_CHECK_OFF(PDMCRITSECTINT, StatLocked); + GEN_CHECK_SIZE(PDMCRITSECT); + GEN_CHECK_SIZE(PDMCRITSECTRWINT); + GEN_CHECK_OFF(PDMCRITSECTRWINT, Core); + GEN_CHECK_OFF(PDMCRITSECTRWINT, pNext); + GEN_CHECK_OFF(PDMCRITSECTRWINT, pvKey); + GEN_CHECK_OFF(PDMCRITSECTRWINT, pVMR3); + GEN_CHECK_OFF(PDMCRITSECTRWINT, pVMR0); + GEN_CHECK_OFF(PDMCRITSECTRWINT, pVMRC); + GEN_CHECK_OFF(PDMCRITSECTRWINT, pszName); + GEN_CHECK_OFF(PDMCRITSECTRWINT, StatContentionRZEnterExcl); + GEN_CHECK_OFF(PDMCRITSECTRWINT, StatWriteLocked); + GEN_CHECK_SIZE(PDMCRITSECTRW); GEN_CHECK_SIZE(PDMQUEUE); GEN_CHECK_OFF(PDMQUEUE, pNext); GEN_CHECK_OFF(PDMQUEUE, enmType); @@ -680,7 +690,6 @@ GEN_CHECK_OFF(PGM, fFinalizedMappings); GEN_CHECK_OFF(PGM, fMappingsFixed); GEN_CHECK_OFF(PGM, fMappingsFixedRestored); - GEN_CHECK_OFF(PGM, fMappingsDisabled); GEN_CHECK_OFF(PGM, GCPtrMappingFixed); GEN_CHECK_OFF(PGM, cbMappingFixed); GEN_CHECK_OFF(PGM, pInterPD); @@ -1321,15 +1330,14 @@ GEN_CHECK_OFF(VM, cCpus); GEN_CHECK_OFF(VM, uCpuExecutionCap); GEN_CHECK_OFF(VM, cbSelf); - GEN_CHECK_OFF(VM, offVMCPU); GEN_CHECK_OFF(VM, pfnVMMRCToHostAsm); GEN_CHECK_OFF(VM, pfnVMMRCToHostAsmNoReturn); GEN_CHECK_OFF(VM, fRecompileUser); GEN_CHECK_OFF(VM, fRecompileSupervisor); GEN_CHECK_OFF(VM, fPATMEnabled); GEN_CHECK_OFF(VM, fCSAMEnabled); - GEN_CHECK_OFF(VM, fHWACCMEnabled); - GEN_CHECK_OFF(VM, fHwVirtExtForced); + GEN_CHECK_OFF(VM, fHMEnabled); + GEN_CHECK_OFF(VM, fHMEnabledFixed); GEN_CHECK_OFF(VM, fFaultTolerantMaster); GEN_CHECK_OFF(VM, fUseLargePages); GEN_CHECK_OFF(VM, hTraceBufRC); @@ -1355,7 +1363,7 @@ GEN_CHECK_OFF(VM, cpum); GEN_CHECK_OFF(VM, vmm); GEN_CHECK_OFF(VM, pgm); - GEN_CHECK_OFF(VM, hwaccm); + GEN_CHECK_OFF(VM, hm); GEN_CHECK_OFF(VM, trpm); GEN_CHECK_OFF(VM, selm); GEN_CHECK_OFF(VM, mm); @@ -1389,7 +1397,7 @@ GEN_CHECK_OFF(VMCPU, uAdHoc); GEN_CHECK_OFF(VMCPU, aStatAdHoc); GEN_CHECK_OFF(VMCPU, cpum); - GEN_CHECK_OFF(VMCPU, hwaccm); + GEN_CHECK_OFF(VMCPU, hm); GEN_CHECK_OFF(VMCPU, em); GEN_CHECK_OFF(VMCPU, iem); GEN_CHECK_OFF(VMCPU, trpm); diff --git a/src/VBox/VMM/testcase/tstVMStructDTrace.cpp b/src/VBox/VMM/testcase/tstVMStructDTrace.cpp index 9a508036..d30d9b70 100644 --- a/src/VBox/VMM/testcase/tstVMStructDTrace.cpp +++ b/src/VBox/VMM/testcase/tstVMStructDTrace.cpp @@ -41,15 +41,17 @@ #include "TMInternal.h" #include "IOMInternal.h" #include "REMInternal.h" -#include "HWACCMInternal.h" -#include "PATMInternal.h" +#include "HMInternal.h" #include "VMMInternal.h" #include "DBGFInternal.h" #include "STAMInternal.h" -#include "CSAMInternal.h" #include "EMInternal.h" #include "IEMInternal.h" #include "REMInternal.h" +#ifdef VBOX_WITH_RAW_MODE +# include "CSAMInternal.h" +# include "PATMInternal.h" +#endif #include <VBox/vmm/vm.h> #include <VBox/param.h> #include <iprt/x86.h> diff --git a/src/VBox/VMM/testcase/tstVMStructRC.cpp b/src/VBox/VMM/testcase/tstVMStructRC.cpp index 7f1d1794..3be4e268 100644 --- a/src/VBox/VMM/testcase/tstVMStructRC.cpp +++ b/src/VBox/VMM/testcase/tstVMStructRC.cpp @@ -8,7 +8,7 @@ */ /* - * Copyright (C) 2006-2010 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -69,7 +69,7 @@ AssertCompileSize(RTHCPHYS, 8); #include "TMInternal.h" #include "IOMInternal.h" #include "REMInternal.h" -#include "HWACCMInternal.h" +#include "HMInternal.h" #include "PATMInternal.h" #include "VMMInternal.h" #include "DBGFInternal.h" @@ -79,6 +79,7 @@ AssertCompileSize(RTHCPHYS, 8); #include "IEMInternal.h" #include "REMInternal.h" #include <VBox/vmm/vm.h> +#include <VBox/vmm/hm_vmx.h> #include <VBox/param.h> #include <iprt/x86.h> #include <iprt/assert.h> diff --git a/src/VBox/VMM/testcase/tstVMStructSize.cpp b/src/VBox/VMM/testcase/tstVMStructSize.cpp index 8bc677e0..133549eb 100644 --- a/src/VBox/VMM/testcase/tstVMStructSize.cpp +++ b/src/VBox/VMM/testcase/tstVMStructSize.cpp @@ -6,7 +6,7 @@ */ /* - * Copyright (C) 2006-2007 Oracle Corporation + * Copyright (C) 2006-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -40,18 +40,20 @@ #include "IOMInternal.h" #include "REMInternal.h" #include "SSMInternal.h" -#include "HWACCMInternal.h" -#include "PATMInternal.h" +#include "HMInternal.h" #include "VMMInternal.h" #include "DBGFInternal.h" #include "STAMInternal.h" #include "VMInternal.h" -#include "CSAMInternal.h" #include "EMInternal.h" #include "IEMInternal.h" #include "REMInternal.h" #include "../VMMR0/GMMR0Internal.h" #include "../VMMR0/GVMMR0Internal.h" +#ifdef VBOX_WITH_RAW_MODE +# include "CSAMInternal.h" +# include "PATMInternal.h" +#endif #include <VBox/vmm/vm.h> #include <VBox/vmm/uvm.h> #include <VBox/vmm/gvm.h> @@ -206,18 +208,22 @@ int main() PRINT_OFFSET(VM, pgm); PRINT_OFFSET(VM, pgm.s.CritSectX); CHECK_PADDING_VM(64, pgm); - PRINT_OFFSET(VM, hwaccm); - CHECK_PADDING_VM(64, hwaccm); + PRINT_OFFSET(VM, hm); + CHECK_PADDING_VM(64, hm); CHECK_PADDING_VM(64, trpm); CHECK_PADDING_VM(64, selm); CHECK_PADDING_VM(64, mm); CHECK_PADDING_VM(64, pdm); + PRINT_OFFSET(VM, pdm.s.CritSect); CHECK_PADDING_VM(64, iom); +#ifdef VBOX_WITH_RAW_MODE CHECK_PADDING_VM(64, patm); CHECK_PADDING_VM(64, csam); +#endif CHECK_PADDING_VM(64, em); /*CHECK_PADDING_VM(64, iem);*/ CHECK_PADDING_VM(64, tm); + PRINT_OFFSET(VM, tm.s.VirtualSyncLock); CHECK_PADDING_VM(64, dbgf); CHECK_PADDING_VM(64, ssm); CHECK_PADDING_VM(64, rem); @@ -226,7 +232,7 @@ int main() PRINT_OFFSET(VMCPU, cpum); CHECK_PADDING_VMCPU(64, cpum); - CHECK_PADDING_VMCPU(64, hwaccm); + CHECK_PADDING_VMCPU(64, hm); CHECK_PADDING_VMCPU(64, em); CHECK_PADDING_VMCPU(64, iem); CHECK_PADDING_VMCPU(64, trpm); @@ -268,7 +274,7 @@ int main() CHECK_MEMBER_ALIGNMENT(VM, aCpus[0].cpum.s.Hyper, 64); CHECK_MEMBER_ALIGNMENT(VM, aCpus[1].cpum.s.Hyper, 64); #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI - CHECK_MEMBER_ALIGNMENT(VM, cpum.s.pvApicBase, 8); + CHECK_MEMBER_ALIGNMENT(VM, aCpus[0].cpum.s.pvApicBase, 8); #endif CHECK_MEMBER_ALIGNMENT(VMCPU, vmm.s.u64CallRing3Arg, 8); @@ -347,6 +353,7 @@ int main() CHECK_PADDING(PDMDRVINS, Internal, 1); CHECK_PADDING2(PDMCRITSECT); + CHECK_PADDING2(PDMCRITSECTRW); /* pgm */ #if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE) @@ -378,7 +385,9 @@ int main() /* misc */ CHECK_PADDING3(EMCPU, u.FatalLongJump, u.achPaddingFatalLongJump); CHECK_SIZE_ALIGNMENT(VMMR0JMPBUF, 8); +#ifdef VBOX_WITH_RAW_MODE CHECK_SIZE_ALIGNMENT(PATCHINFO, 8); +#endif #if 0 PRINT_OFFSET(VM, fForcedActions); PRINT_OFFSET(VM, StatQemuToGC); @@ -393,15 +402,16 @@ int main() CHECK_MEMBER_ALIGNMENT(PDM, CritSect, sizeof(uintptr_t)); CHECK_MEMBER_ALIGNMENT(MMHYPERHEAP, Lock, sizeof(uintptr_t)); - /* hwaccm - 32-bit gcc won't align uint64_t naturally, so check. */ - CHECK_MEMBER_ALIGNMENT(HWACCM, u64RegisterMask, 8); - CHECK_MEMBER_ALIGNMENT(HWACCM, vmx.hostCR4, 8); - CHECK_MEMBER_ALIGNMENT(HWACCM, vmx.msr.feature_ctrl, 8); - CHECK_MEMBER_ALIGNMENT(HWACCM, StatTPRPatchSuccess, 8); - CHECK_MEMBER_ALIGNMENT(HWACCMCPU, StatEntry, 8); - CHECK_MEMBER_ALIGNMENT(HWACCMCPU, vmx.HCPhysVMCS, sizeof(RTHCPHYS)); - CHECK_MEMBER_ALIGNMENT(HWACCMCPU, vmx.proc_ctls, 8); - CHECK_MEMBER_ALIGNMENT(HWACCMCPU, Event.intInfo, 8); + /* hm - 32-bit gcc won't align uint64_t naturally, so check. */ + CHECK_MEMBER_ALIGNMENT(HM, uMaxAsid, 8); + CHECK_MEMBER_ALIGNMENT(HM, vmx.u64HostCr4, 8); + CHECK_MEMBER_ALIGNMENT(HM, vmx.Msrs.u64FeatureCtrl, 8); + CHECK_MEMBER_ALIGNMENT(HM, StatTprPatchSuccess, 8); + CHECK_MEMBER_ALIGNMENT(HMCPU, StatEntry, 8); + CHECK_MEMBER_ALIGNMENT(HMCPU, vmx.HCPhysVmcs, sizeof(RTHCPHYS)); + CHECK_MEMBER_ALIGNMENT(HMCPU, vmx.u32PinCtls, 8); + CHECK_MEMBER_ALIGNMENT(HMCPU, DisState, 8); + CHECK_MEMBER_ALIGNMENT(HMCPU, Event.u64IntInfo, 8); /* Make sure the set is large enough and has the correct size. */ CHECK_SIZE(VMCPUSET, 32); diff --git a/src/VBox/VMM/testcase/tstX86-1A.asm b/src/VBox/VMM/testcase/tstX86-1A.asm index 054f1ba1..176d3646 100644 --- a/src/VBox/VMM/testcase/tstX86-1A.asm +++ b/src/VBox/VMM/testcase/tstX86-1A.asm @@ -1521,7 +1521,7 @@ BEGINPROC x861_Test2 %endif .failed3: - add xSP, 20h + xS + add xSP, 20h + xCB jmp .return @@ -1941,7 +1941,7 @@ SaveFPUAndGRegsToStack: push xAX push xDI - lea xDI, [xSP + xS * 5] + lea xDI, [xSP + xCB * 5] mov xCX, 512 / 4 mov eax, 0cccccccch cld @@ -1953,69 +1953,69 @@ SaveFPUAndGRegsToStack: popf ; Save the FPU state. - mov dword [xSP + xS + X86FXSTATE.FPUIP], 0 - mov dword [xSP + xS + X86FXSTATE.FPUCS], 0 - mov dword [xSP + xS + X86FXSTATE.FPUDP], 0 - mov dword [xSP + xS + X86FXSTATE.FPUDS], 0 - arch_fxsave [xSP + xS] + mov dword [xSP + xCB + X86FXSTATE.FPUIP], 0 + mov dword [xSP + xCB + X86FXSTATE.FPUCS], 0 + mov dword [xSP + xCB + X86FXSTATE.FPUDP], 0 + mov dword [xSP + xCB + X86FXSTATE.FPUDS], 0 + arch_fxsave [xSP + xCB] ; Save GRegs (80h bytes). %ifdef RT_ARCH_AMD64 - mov [xSP + 512 + xS + 000h], xAX - mov [xSP + 512 + xS + 008h], xBX - mov [xSP + 512 + xS + 010h], xCX - mov [xSP + 512 + xS + 018h], xDX - mov [xSP + 512 + xS + 020h], xDI - mov [xSP + 512 + xS + 028h], xSI - mov [xSP + 512 + xS + 030h], xBP - mov [xSP + 512 + xS + 038h], r8 - mov [xSP + 512 + xS + 040h], r9 - mov [xSP + 512 + xS + 048h], r10 - mov [xSP + 512 + xS + 050h], r11 - mov [xSP + 512 + xS + 058h], r12 - mov [xSP + 512 + xS + 060h], r13 - mov [xSP + 512 + xS + 068h], r14 - mov [xSP + 512 + xS + 070h], r15 + mov [xSP + 512 + xCB + 000h], xAX + mov [xSP + 512 + xCB + 008h], xBX + mov [xSP + 512 + xCB + 010h], xCX + mov [xSP + 512 + xCB + 018h], xDX + mov [xSP + 512 + xCB + 020h], xDI + mov [xSP + 512 + xCB + 028h], xSI + mov [xSP + 512 + xCB + 030h], xBP + mov [xSP + 512 + xCB + 038h], r8 + mov [xSP + 512 + xCB + 040h], r9 + mov [xSP + 512 + xCB + 048h], r10 + mov [xSP + 512 + xCB + 050h], r11 + mov [xSP + 512 + xCB + 058h], r12 + mov [xSP + 512 + xCB + 060h], r13 + mov [xSP + 512 + xCB + 068h], r14 + mov [xSP + 512 + xCB + 070h], r15 pushf pop rax - mov [xSP + 512 + xS + 078h], rax - mov rax, [xSP + 512 + xS + 000h] + mov [xSP + 512 + xCB + 078h], rax + mov rax, [xSP + 512 + xCB + 000h] %else - mov [xSP + 512 + xS + 000h], eax - mov [xSP + 512 + xS + 004h], eax - mov [xSP + 512 + xS + 008h], ebx - mov [xSP + 512 + xS + 00ch], ebx - mov [xSP + 512 + xS + 010h], ecx - mov [xSP + 512 + xS + 014h], ecx - mov [xSP + 512 + xS + 018h], edx - mov [xSP + 512 + xS + 01ch], edx - mov [xSP + 512 + xS + 020h], edi - mov [xSP + 512 + xS + 024h], edi - mov [xSP + 512 + xS + 028h], esi - mov [xSP + 512 + xS + 02ch], esi - mov [xSP + 512 + xS + 030h], ebp - mov [xSP + 512 + xS + 034h], ebp - mov [xSP + 512 + xS + 038h], eax - mov [xSP + 512 + xS + 03ch], eax - mov [xSP + 512 + xS + 040h], eax - mov [xSP + 512 + xS + 044h], eax - mov [xSP + 512 + xS + 048h], eax - mov [xSP + 512 + xS + 04ch], eax - mov [xSP + 512 + xS + 050h], eax - mov [xSP + 512 + xS + 054h], eax - mov [xSP + 512 + xS + 058h], eax - mov [xSP + 512 + xS + 05ch], eax - mov [xSP + 512 + xS + 060h], eax - mov [xSP + 512 + xS + 064h], eax - mov [xSP + 512 + xS + 068h], eax - mov [xSP + 512 + xS + 06ch], eax - mov [xSP + 512 + xS + 070h], eax - mov [xSP + 512 + xS + 074h], eax + mov [xSP + 512 + xCB + 000h], eax + mov [xSP + 512 + xCB + 004h], eax + mov [xSP + 512 + xCB + 008h], ebx + mov [xSP + 512 + xCB + 00ch], ebx + mov [xSP + 512 + xCB + 010h], ecx + mov [xSP + 512 + xCB + 014h], ecx + mov [xSP + 512 + xCB + 018h], edx + mov [xSP + 512 + xCB + 01ch], edx + mov [xSP + 512 + xCB + 020h], edi + mov [xSP + 512 + xCB + 024h], edi + mov [xSP + 512 + xCB + 028h], esi + mov [xSP + 512 + xCB + 02ch], esi + mov [xSP + 512 + xCB + 030h], ebp + mov [xSP + 512 + xCB + 034h], ebp + mov [xSP + 512 + xCB + 038h], eax + mov [xSP + 512 + xCB + 03ch], eax + mov [xSP + 512 + xCB + 040h], eax + mov [xSP + 512 + xCB + 044h], eax + mov [xSP + 512 + xCB + 048h], eax + mov [xSP + 512 + xCB + 04ch], eax + mov [xSP + 512 + xCB + 050h], eax + mov [xSP + 512 + xCB + 054h], eax + mov [xSP + 512 + xCB + 058h], eax + mov [xSP + 512 + xCB + 05ch], eax + mov [xSP + 512 + xCB + 060h], eax + mov [xSP + 512 + xCB + 064h], eax + mov [xSP + 512 + xCB + 068h], eax + mov [xSP + 512 + xCB + 06ch], eax + mov [xSP + 512 + xCB + 070h], eax + mov [xSP + 512 + xCB + 074h], eax pushf pop eax - mov [xSP + 512 + xS + 078h], eax - mov [xSP + 512 + xS + 07ch], eax - mov eax, [xSP + 512 + xS + 000h] + mov [xSP + 512 + xCB + 078h], eax + mov [xSP + 512 + xCB + 07ch], eax + mov eax, [xSP + 512 + xCB + 000h] %endif ret @@ -2028,7 +2028,7 @@ SaveFPUAndGRegsToStack: ; ZF reflects the eax value to save a couple of instructions... ; CompareFPUAndGRegsOnStack: - lea xSP, [xSP - (1024 - xS)] + lea xSP, [xSP - (1024 - xCB)] call SaveFPUAndGRegsToStack push xSI @@ -2036,7 +2036,7 @@ CompareFPUAndGRegsOnStack: push xCX mov xCX, 640 - lea xSI, [xSP + xS*3] + lea xSI, [xSP + xCB*3] lea xDI, [xSI + 1024] cld @@ -2044,7 +2044,7 @@ CompareFPUAndGRegsOnStack: je .ok ;int3 - lea xAX, [xSP + xS*3] + lea xAX, [xSP + xCB*3] xchg xAX, xSI sub xAX, xSI @@ -2059,7 +2059,7 @@ CompareFPUAndGRegsOnStack: pop xCX pop xDI pop xSI - lea xSP, [xSP + (1024 - xS)] + lea xSP, [xSP + (1024 - xCB)] or eax, eax ret @@ -2072,7 +2072,7 @@ CompareFPUAndGRegsOnStack: ; ZF reflects the eax value to save a couple of instructions... ; CompareFPUAndGRegsOnStackIgnoreOpAndIp: - lea xSP, [xSP - (1024 - xS)] + lea xSP, [xSP - (1024 - xCB)] call SaveFPUAndGRegsToStack push xSI @@ -2080,7 +2080,7 @@ CompareFPUAndGRegsOnStackIgnoreOpAndIp: push xCX mov xCX, 640 - lea xSI, [xSP + xS*3] + lea xSI, [xSP + xCB*3] lea xDI, [xSI + 1024] mov word [xSI + X86FXSTATE.FOP], 0 ; ignore @@ -2093,7 +2093,7 @@ CompareFPUAndGRegsOnStackIgnoreOpAndIp: je .ok ;int3 - lea xAX, [xSP + xS*3] + lea xAX, [xSP + xCB*3] xchg xAX, xSI sub xAX, xSI @@ -2108,7 +2108,7 @@ CompareFPUAndGRegsOnStackIgnoreOpAndIp: pop xCX pop xDI pop xSI - lea xSP, [xSP + (1024 - xS)] + lea xSP, [xSP + (1024 - xCB)] or eax, eax ret @@ -2478,9 +2478,16 @@ extern NAME(RTTestISub) %endif call NAME(RTTestISub) %else + %ifdef RT_OS_DARWIN + sub esp, 12 + push %%s_szName + call NAME(RTTestISub) + add esp, 16 + %else push %%s_szName call NAME(RTTestISub) add esp, 4 + %endif %endif jmp %%done %%s_szName: @@ -2493,7 +2500,7 @@ extern NAME(RTTestISub) ; Checks the opcode and CS:IP FPU. ; ; @returns ZF=1 on success, ZF=0 on failure. -; @param xSP + xS fxsave image followed by fnstenv. +; @param xSP + xCB fxsave image followed by fnstenv. ; @param xCX Opcode address (no prefixes). ; CheckOpcodeCsIp: @@ -2503,15 +2510,15 @@ CheckOpcodeCsIp: ; Check the IP. %ifdef RT_ARCH_AMD64 - cmp rcx, [xBP + xS*2 + X86FXSTATE.FPUIP] + cmp rcx, [xBP + xCB*2 + X86FXSTATE.FPUIP] %else - cmp ecx, [xBP + xS*2 + X86FXSTATE.FPUIP] + cmp ecx, [xBP + xCB*2 + X86FXSTATE.FPUIP] %endif jne .failure1 .check_fpucs: mov ax, cs - cmp ax, [xBP + xS*2 + 512 + X86FSTENV32P.FPUCS] + cmp ax, [xBP + xCB*2 + 512 + X86FSTENV32P.FPUCS] jne .failure2 ; Check the opcode. This may be disabled. @@ -2519,13 +2526,13 @@ CheckOpcodeCsIp: mov al, [xCX + 1] and ax, 07ffh - cmp ax, [xBP + xS*2 + X86FXSTATE.FOP] + cmp ax, [xBP + xCB*2 + X86FXSTATE.FOP] je .success - cmp ax, [xBP + xS*2 + 512 + X86FSTENV32P.FOP] + cmp ax, [xBP + xCB*2 + 512 + X86FSTENV32P.FOP] je .success ; xor ax, ax -; cmp ax, [xBP + xS*2 + X86FXSTATE.FOP] +; cmp ax, [xBP + xCB*2 + X86FXSTATE.FOP] ; jne .failure3 .success: @@ -2539,11 +2546,11 @@ CheckOpcodeCsIp: ; AMD64 doesn't seem to store anything at IP and DP, so use the ; fnstenv image instead even if that only contains the lower 32-bit. xor eax, eax - cmp xAX, [xBP + xS*2 + X86FXSTATE.FPUIP] + cmp xAX, [xBP + xCB*2 + X86FXSTATE.FPUIP] jne .failure1_for_real - cmp xAX, [xBP + xS*2 + X86FXSTATE.FPUDP] + cmp xAX, [xBP + xCB*2 + X86FXSTATE.FPUDP] jne .failure1_for_real - cmp ecx, [xBP + xS*2 + 512 + X86FSTENV32P.FPUIP] + cmp ecx, [xBP + xCB*2 + 512 + X86FSTENV32P.FPUIP] je .check_fpucs .failure1_for_real: mov eax, 10000000 @@ -2637,7 +2644,7 @@ BEGINCODE ; Checks the opcode, CS:IP and DS:DP of the FPU. ; ; @returns ZF=1 on success, ZF=0+EAX on failure. -; @param xSP + xS fxsave image followed by fnstenv. +; @param xSP + xCB fxsave image followed by fnstenv. ; @param xCX Opcode address (no prefixes). ; @param xDX Memory address (DS relative). ; @@ -2648,15 +2655,15 @@ CheckOpcodeCsIpDsDp: ; Check the memory operand. %ifdef RT_ARCH_AMD64 - cmp rdx, [xBP + xS*2 + X86FXSTATE.FPUDP] + cmp rdx, [xBP + xCB*2 + X86FXSTATE.FPUDP] %else - cmp edx, [xBP + xS*2 + X86FXSTATE.FPUDP] + cmp edx, [xBP + xCB*2 + X86FXSTATE.FPUDP] %endif jne .failure1 .check_fpuds: mov ax, ds - cmp ax, [xBP + xS*2 + 512 + X86FSTENV32P.FPUDS] + cmp ax, [xBP + xCB*2 + 512 + X86FSTENV32P.FPUDS] jne .failure2 .success: @@ -2669,11 +2676,11 @@ CheckOpcodeCsIpDsDp: ; AMD may leave all fields as ZERO in the FXSAVE image - figure ; if there is a flag controlling this anywhere... xor eax, eax - cmp xAX, [xBP + xS*2 + X86FXSTATE.FPUDP] + cmp xAX, [xBP + xCB*2 + X86FXSTATE.FPUDP] jne .failure1_for_real - cmp xAX, [xBP + xS*2 + X86FXSTATE.FPUIP] + cmp xAX, [xBP + xCB*2 + X86FXSTATE.FPUIP] jne .failure1_for_real - cmp edx, [xBP + xS*2 + 512 + X86FSTENV32P.FPUDP] + cmp edx, [xBP + xCB*2 + 512 + X86FSTENV32P.FPUDP] je .check_fpuds .failure1_for_real: mov eax, 60000000 |