diff options
Diffstat (limited to 'src/VBox/VMM/testcase/tstIEMCheckMc.cpp')
| -rw-r--r-- | src/VBox/VMM/testcase/tstIEMCheckMc.cpp | 124 |
1 files changed, 103 insertions, 21 deletions
diff --git a/src/VBox/VMM/testcase/tstIEMCheckMc.cpp b/src/VBox/VMM/testcase/tstIEMCheckMc.cpp index bee7fae7..1ae3e8b0 100644 --- a/src/VBox/VMM/testcase/tstIEMCheckMc.cpp +++ b/src/VBox/VMM/testcase/tstIEMCheckMc.cpp @@ -4,7 +4,7 @@ */ /* - * Copyright (C) 2011 Oracle Corporation + * Copyright (C) 2011-2012 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; @@ -33,6 +33,7 @@ *******************************************************************************/ bool volatile g_fRandom; uint8_t volatile g_bRandom; +uint128_t g_u128Zero; /** For hacks. */ @@ -63,6 +64,9 @@ uint8_t volatile g_bRandom; uint8_t iMySeg = (a_iSeg); NOREF(iMySeg); /** @todo const or variable. grr. */ \ } while (0) +#define CHK_CALL_ARG(a_Name, a_iArg) \ + do { RT_CONCAT3(iArgCheck_,a_iArg,a_Name) = 1; } while (0) + /** @name Other stubs. * @{ */ @@ -97,10 +101,14 @@ typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu); #define IEMOP_HLP_NO_REAL_OR_V86_MODE() do { } while (0) #define IEMOP_HLP_NO_LOCK_PREFIX() do { } while (0) #define IEMOP_HLP_NO_64BIT() do { } while (0) +#define IEMOP_HLP_ONLY_64BIT() do { } while (0) #define IEMOP_HLP_64BIT_OP_SIZE() do { } while (0) #define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0) +#define IEMOP_HLP_CLEAR_REX_NOT_BEFORE_OPCODE(a_szPrf) do { } while (0) #define IEMOP_HLP_DONE_DECODING() do { } while (0) #define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0) +#define IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) do { } while (0) +#define IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) do { } while (0) #define IEMOP_RAISE_DIVIDE_ERROR() VERR_TRPM_ACTIVE_TRAP #define IEMOP_RAISE_INVALID_OPCODE() VERR_TRPM_ACTIVE_TRAP #define IEMOP_RAISE_INVALID_LOCK_PREFIX() VERR_TRPM_ACTIVE_TRAP @@ -133,6 +141,10 @@ typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu); #define IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX(a_fEdx) (g_fRandom) #define IEM_IS_AMD_CPUID_FEATURES_ANY_PRESENT(a_fEdx, a_fEcx) (g_fRandom) #define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(a_fEdx) (g_fRandom) +#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_ECX(a_fEcx) (g_fRandom) +#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX_ON_HOST(a_fEdx) (g_fRandom) +#define IEM_IS_GUEST_CPU_AMD(a_pIemCpu) (g_fRandom) +#define IEM_IS_GUEST_CPU_INTEL(a_pIemCpu) (g_fRandom) #define iemRecalEffOpSize(a_pIemCpu) do { } while (0) @@ -170,6 +182,18 @@ IEMOPMULDIVSIZES g_iemAImpl_div; IEMOPMULDIVSIZES g_iemAImpl_idiv; IEMOPSHIFTDBLSIZES g_iemAImpl_shld; IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; +IEMOPMEDIAF1L1 g_iemAImpl_punpcklbw; +IEMOPMEDIAF1L1 g_iemAImpl_punpcklwd; +IEMOPMEDIAF1L1 g_iemAImpl_punpckldq; +IEMOPMEDIAF1L1 g_iemAImpl_punpcklqdq; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhbw; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhwd; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhdq; +IEMOPMEDIAF1H1 g_iemAImpl_punpckhqdq; +IEMOPMEDIAF2 g_iemAImpl_pxor; +IEMOPMEDIAF2 g_iemAImpl_pcmpeqb; +IEMOPMEDIAF2 g_iemAImpl_pcmpeqw; +IEMOPMEDIAF2 g_iemAImpl_pcmpeqd; #define iemAImpl_idiv_u8 ((PFNIEMAIMPLMULDIVU8)0) @@ -250,6 +274,10 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define iemCImpl_callf NULL #define iemCImpl_FarJmp NULL +#define iemAImpl_pshufhw NULL +#define iemAImpl_pshuflw NULL +#define iemAImpl_pshufd NULL + /** @} */ @@ -292,6 +320,9 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_RAISE_DIVIDE_ERROR() return VERR_TRPM_ACTIVE_TRAP #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() do {} while (0) #define IEM_MC_MAYBE_RAISE_FPU_XCPT() do {} while (0) +#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() do {} while (0) +#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() do {} while (0) +#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() do {} while (0) #define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() do {} while (0) #define IEM_MC_LOCAL(a_Type, a_Name) \ @@ -322,7 +353,7 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; NOREF(a_Name) #define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \ RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \ - int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \ + int RT_CONCAT3(iArgCheck_,a_iArg,a_pName); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_pName)); \ AssertCompile((a_iArg) < cArgs); \ uint32_t a_Name; \ uint32_t *a_pName = &a_Name; \ @@ -436,6 +467,25 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FLIP_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0) #define IEM_MC_CLEAR_FSW_EX() do { } while (0) + +#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); } while (0) +#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); } while (0) +#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) do { (a_pu32Dst) = (uint32_t const *)((uintptr_t)0); CHK_PTYPE(uint32_t const *, a_pu32Dst); } while (0) + +#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(uint128_t, a_u128Value); } while (0) +#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(uint128_t, a_u128Value); } while (0) +#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); } while (0) +#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) do { CHK_TYPE(uint32_t, a_u32Value); } while (0) +#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t *)((uintptr_t)0); CHK_PTYPE(uint128_t *, a_pu128Dst); } while (0) +#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) do { (a_pu128Dst) = (uint128_t const *)((uintptr_t)0); CHK_PTYPE(uint128_t const *, a_pu128Dst); } while (0) +#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) do { (a_pu64Dst) = (uint64_t const *)((uintptr_t)0); CHK_PTYPE(uint64_t const *, a_pu64Dst); } while (0) + #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) do { CHK_TYPE(uint16_t, a_GCPtrMem16); } while (0) #define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) do { CHK_TYPE(uint32_t, a_GCPtrMem32); } while (0) @@ -445,6 +495,7 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); } while (0) #define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) +#define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U8_DISP(a_u8Dst, a_iSeg, a_GCPtrMem, a_offDisp) \ do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint8_t, a_u8Dst); } while (0) @@ -455,10 +506,6 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \ do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint64_t, a_u64Dst); } while (0) -#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst);} while (0) -#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst);} while (0) -#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst);} while (0) - #define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) @@ -471,7 +518,13 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) #define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) -#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0) +#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst);} while (0) +#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst);} while (0) +#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst);} while (0) +#define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst);} while (0) +#define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst);} while (0) + +#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0) #define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); } while (0) #define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); } while (0) #define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); } while (0) @@ -486,9 +539,12 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); } while (0) #define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); } while (0) #define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); } while (0) +#define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Dst) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst); CHK_SEG_IDX(a_iSeg);} while (0) +#define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Dst) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint128_t, a_u128Dst); CHK_SEG_IDX(a_iSeg);} while (0) #define IEM_MC_PUSH_U16(a_u16Value) do {} while (0) #define IEM_MC_PUSH_U32(a_u32Value) do {} while (0) +#define IEM_MC_PUSH_U32_SREG(a_u32Value) do {} while (0) #define IEM_MC_PUSH_U64(a_u64Value) do {} while (0) #define IEM_MC_POP_U16(a_pu16Value) do {} while (0) #define IEM_MC_POP_U32(a_pu32Value) do {} while (0) @@ -497,25 +553,42 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) do {} while (0) #define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do {} while (0) #define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do {} while (0) -#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0) -#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) do {} while (0) -#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) do {} while (0) -#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) do {} while (0) -#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) do {} while (0) -#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) do { (a_rc) = VINF_SUCCESS; } while (0) -#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return VINF_SUCCESS -#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return VINF_SUCCESS +#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) do {} while (0) +#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) \ + do { CHK_CALL_ARG(a0, 0); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) +#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); } while (0) +#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); (a_rc) = VINF_SUCCESS; } while (0) +#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (a_rc) = VINF_SUCCESS; } while (0) +#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) do { } while (0) +#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) \ + do { CHK_CALL_ARG(a0, 0); } while (0) +#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) +#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); } while (0) +#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); CHK_CALL_ARG(a4, 4); } while (0) #define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (VINF_SUCCESS) #define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (VINF_SUCCESS) #define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (VINF_SUCCESS) #define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (VINF_SUCCESS) -#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) do { } while (0) -#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) do { } while (0) -#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a3) do { } while (0) +#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \ + do { CHK_CALL_ARG(a0, 0); } while (0) +#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); } while (0) #define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { } while (0) #define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { } while (0) #define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { } while (0) @@ -545,6 +618,15 @@ IEMOPSHIFTDBLSIZES g_iemAImpl_shrd; #define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { } while (0) #define IEM_MC_USED_FPU() do { } while (0) +#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0) +#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); } while (0) +#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \ + do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);} while (0) + #define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (g_fRandom) { #define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) { #define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (g_fRandom) { |