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| author | Peter Meerwald-Stadler <pmeerw@pmeerw.net> | 2023-05-13 06:17:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-05-12 21:17:09 -0700 |
| commit | f2f9f157dfbf3d43dadfdd73d03dd8c56ec84c1c (patch) | |
| tree | c1af030cfbfdf2ca0697ab28c3731a4c0ac3b3ea | |
| parent | 468014643d7a7c481ff67b9c87364d16eedc317a (diff) | |
| download | yasm-f2f9f157dfbf3d43dadfdd73d03dd8c56ec84c1c.tar.gz | |
Allow sha256rnds2 to have memory as 2nd operand (#108)
| -rwxr-xr-x | modules/arch/x86/gen_x86_insn.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py index 09d64c7f..0a798fea 100755 --- a/modules/arch/x86/gen_x86_insn.py +++ b/modules/arch/x86/gen_x86_insn.py @@ -8096,7 +8096,7 @@ add_group("intel_SHA256RNDS2", cpu=["SHA"], opcode=[0x0F, 0x38, 0xCB], operands=[Operand(type="SIMDReg", size=128, dest="Spare"), - Operand(type="SIMDReg", size=128, dest="EA")]) + Operand(type="SIMDRM", size=128, dest="EA")]) add_insn("SHA1MSG1", "intel_SHA1MSG1") add_insn("SHA1MSG2", "intel_SHA1MSG2") |