blob: d21a9b9383ad4ff2b1cd1d3ddfc7a4761fec7d5c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Stefan Roese <sr@denx.de>
*/
#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
#define __CONFIG_GARDENA_SMART_GATEWAY_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
/* Dummy value */
#define CONFIG_SYS_UBOOT_BASE 0
/* Serial SPL */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_NS16550_CLK 40000000
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0xb0000c00
#endif
/* UART */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 460800, 921600 }
/* RAM */
/* Environment settings */
#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */
|
