1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Renesas RZ/A1 R7S72100 OSTM Timer driver
*
* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <dm.h>
#include <clk.h>
#include <timer.h>
#include <linux/bitops.h>
#define OSTM_CMP 0x00
#define OSTM_CNT 0x04
#define OSTM_TE 0x10
#define OSTM_TS 0x14
#define OSTM_TT 0x18
#define OSTM_CTL 0x20
#define OSTM_CTL_D BIT(1)
DECLARE_GLOBAL_DATA_PTR;
struct ostm_priv {
fdt_addr_t regs;
};
static u64 ostm_get_count(struct udevice *dev)
{
struct ostm_priv *priv = dev_get_priv(dev);
return timer_conv_64(readl(priv->regs + OSTM_CNT));
}
static int ostm_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ostm_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
int ret;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
uc_priv->clock_rate = clk_get_rate(&clk);
clk_free(&clk);
#else
uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
#endif
readb(priv->regs + OSTM_CTL);
writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
setbits_8(priv->regs + OSTM_TT, BIT(0));
writel(0xffffffff, priv->regs + OSTM_CMP);
setbits_8(priv->regs + OSTM_TS, BIT(0));
return 0;
}
static int ostm_ofdata_to_platdata(struct udevice *dev)
{
struct ostm_priv *priv = dev_get_priv(dev);
priv->regs = dev_read_addr(dev);
return 0;
}
static const struct timer_ops ostm_ops = {
.get_count = ostm_get_count,
};
static const struct udevice_id ostm_ids[] = {
{ .compatible = "renesas,ostm" },
{}
};
U_BOOT_DRIVER(ostm_timer) = {
.name = "ostm-timer",
.id = UCLASS_TIMER,
.ops = &ostm_ops,
.probe = ostm_probe,
.of_match = ostm_ids,
.ofdata_to_platdata = ostm_ofdata_to_platdata,
.priv_auto = sizeof(struct ostm_priv),
};
|
