summaryrefslogtreecommitdiff
path: root/drivers/spi/cf_spi.c
blob: 1a841b5dcefca9e2f6ae5ef7e4ea73d09b5f5631 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * Support for DM and DT, non-DM code removed.
 * Copyright (C) 2018 Angelo Dureghello <angelo@sysam.it>
 *
 * TODO: fsl_dspi.c should work as a driver for the DSPI module.
 */

#include <common.h>
#include <dm.h>
#include <log.h>
#include <asm/global_data.h>
#include <dm/platform_data/spi_coldfire.h>
#include <spi.h>
#include <malloc.h>
#include <asm/coldfire/dspi.h>
#include <asm/io.h>

struct coldfire_spi_priv {
	struct dspi *regs;
	uint baudrate;
	int mode;
	int charbit;
};

DECLARE_GLOBAL_DATA_PTR;

#ifndef SPI_IDLE_VAL
#if defined(CONFIG_SPI_MMC)
#define SPI_IDLE_VAL	0xFFFF
#else
#define SPI_IDLE_VAL	0x0
#endif
#endif

/*
 * DSPI specific mode
 *
 * bit 31 - 28: Transfer size 3 to 16 bits
 *     27 - 26: PCS to SCK delay prescaler
 *     25 - 24: After SCK delay prescaler
 *     23 - 22: Delay after transfer prescaler
 *     21     : Allow overwrite for bit 31-22 and bit 20-8
 *     20     : Double baud rate
 *     19 - 16: PCS to SCK delay scaler
 *     15 - 12: After SCK delay scaler
 *     11 -  8: Delay after transfer scaler
 *      7 -  0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST
 */
#define SPI_MODE_MOD			0x00200000
#define SPI_MODE_DBLRATE		0x00100000

#define SPI_MODE_XFER_SZ_MASK		0xf0000000
#define SPI_MODE_DLY_PRE_MASK		0x0fc00000
#define SPI_MODE_DLY_SCA_MASK		0x000fff00

#define MCF_FRM_SZ_16BIT		DSPI_CTAR_TRSZ(0xf)
#define MCF_DSPI_SPEED_BESTMATCH	0x7FFFFFFF
#define MCF_DSPI_MAX_CTAR_REGS		8

/* Default values */
#define MCF_DSPI_DEFAULT_SCK_FREQ	10000000
#define MCF_DSPI_DEFAULT_MAX_CS		4
#define MCF_DSPI_DEFAULT_MODE		0

#define MCF_DSPI_DEFAULT_CTAR		(DSPI_CTAR_TRSZ(7) | \
					DSPI_CTAR_PCSSCK_1CLK | \
					DSPI_CTAR_PASC(0) | \
					DSPI_CTAR_PDT(0) | \
					DSPI_CTAR_CSSCK(0) | \
					DSPI_CTAR_ASC(0) | \
					DSPI_CTAR_DT(1) | \
					DSPI_CTAR_BR(6))

#define MCF_CTAR_MODE_MASK		(MCF_FRM_SZ_16BIT | \
					DSPI_CTAR_PCSSCK(3) | \
					DSPI_CTAR_PASC_7CLK | \
					DSPI_CTAR_PDT(3) | \
					DSPI_CTAR_CSSCK(0x0f) | \
					DSPI_CTAR_ASC(0x0f) | \
					DSPI_CTAR_DT(0x0f))

#define setup_ctrl(ctrl, cs)	((ctrl & 0xFF000000) | ((1 << cs) << 16))

static inline void cfspi_tx(struct coldfire_spi_priv *cfspi,
			    u32 ctrl, u16 data)
{
	/*
	 * Need to check fifo level here
	 */
	while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 0x4000)
		;

	writel(ctrl | data, &cfspi->regs->tfr);
}

static inline u16 cfspi_rx(struct coldfire_spi_priv *cfspi)
{

	while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0)
		;

	return readw(&cfspi->regs->rfr);
}

static int coldfire_spi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
		return -1;

	/* Clear FIFO and resume transfer */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	dspi_chip_select(slave_plat->cs);

	return 0;
}

static int coldfire_spi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	/* Clear FIFO */
	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	dspi_chip_unselect(slave_plat->cs);

	return 0;
}

static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
			     const void *dout, void *din,
			     unsigned long flags)
{
	struct udevice *bus = dev_get_parent(dev);
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
	u8 *spi_rd = NULL, *spi_wr = NULL;
	static u32 ctrl;
	uint len = bitlen >> 3;

	if (cfspi->charbit == 16) {
		bitlen >>= 1;
		spi_wr16 = (u16 *)dout;
		spi_rd16 = (u16 *)din;
	} else {
		spi_wr = (u8 *)dout;
		spi_rd = (u8 *)din;
	}

	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
		ctrl |= DSPI_TFR_CONT;

	ctrl = setup_ctrl(ctrl, slave_plat->cs);

	if (len > 1) {
		int tmp_len = len - 1;

		while (tmp_len--) {
			if (dout) {
				if (cfspi->charbit == 16)
					cfspi_tx(cfspi, ctrl, *spi_wr16++);
				else
					cfspi_tx(cfspi, ctrl, *spi_wr++);
				cfspi_rx(cfspi);
			}

			if (din) {
				cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
				if (cfspi->charbit == 16)
					*spi_rd16++ = cfspi_rx(cfspi);
				else
					*spi_rd++ = cfspi_rx(cfspi);
			}
		}

		len = 1;	/* remaining byte */
	}

	if (flags & SPI_XFER_END)
		ctrl &= ~DSPI_TFR_CONT;

	if (len) {
		if (dout) {
			if (cfspi->charbit == 16)
				cfspi_tx(cfspi, ctrl, *spi_wr16);
			else
				cfspi_tx(cfspi, ctrl, *spi_wr);
			cfspi_rx(cfspi);
		}

		if (din) {
			cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
			if (cfspi->charbit == 16)
				*spi_rd16 = cfspi_rx(cfspi);
			else
				*spi_rd = cfspi_rx(cfspi);
		}
	} else {
		/* dummy read */
		cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL);
		cfspi_rx(cfspi);
	}

	return 0;
}

static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
{
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	int prescaler[] = { 2, 3, 5, 7 };
	int scaler[] = {
		2, 4, 6, 8,
		16, 32, 64, 128,
		256, 512, 1024, 2048,
		4096, 8192, 16384, 32768
	};
	int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0;
	int best_i, best_j, bestmatch = MCF_DSPI_SPEED_BESTMATCH, baud_speed;
	u32 bus_setup;

	cfspi->baudrate = max_hz;

	/* Read current setup */
	bus_setup = readl(&dspi->ctar[dev_seq(bus)]);

	tmp = (prescaler[3] * scaler[15]);
	/* Maximum and minimum baudrate it can handle */
	if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||
	    (cfspi->baudrate < (gd->bus_clk / tmp))) {
		printf("Exceed baudrate limitation: Max %d - Min %d\n",
		       (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
		return -1;
	}

	/* Activate Double Baud when it exceed 1/4 the bus clk */
	if ((bus_setup & DSPI_CTAR_DBR) ||
	    (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
		bus_setup |= DSPI_CTAR_DBR;
		dbr = 1;
	}

	/* Overwrite default value set in platform configuration file */
	if (cfspi->mode & SPI_MODE_MOD) {
		/*
		 * Check to see if it is enabled by default in platform
		 * config, or manual setting passed by mode parameter
		 */
		if (cfspi->mode & SPI_MODE_DBLRATE) {
			bus_setup |= DSPI_CTAR_DBR;
			dbr = 1;
		}
	}

	pbrcnt = sizeof(prescaler) / sizeof(int);
	brcnt = sizeof(scaler) / sizeof(int);

	/* baudrate calculation - to closer value, may not be exact match */
	for (best_i = 0, best_j = 0, i = 0; i < pbrcnt; i++) {
		baud_speed = gd->bus_clk / prescaler[i];
		for (j = 0; j < brcnt; j++) {
			tmp = (baud_speed / scaler[j]) * (1 + dbr);

			if (tmp > cfspi->baudrate)
				diff = tmp - cfspi->baudrate;
			else
				diff = cfspi->baudrate - tmp;

			if (diff < bestmatch) {
				bestmatch = diff;
				best_i = i;
				best_j = j;
			}
		}
	}

	bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
	bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
	writel(bus_setup, &dspi->ctar[dev_seq(bus)]);

	return 0;
}

static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
{
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	u32 bus_setup = 0;

	cfspi->mode = mode;

	if (cfspi->mode & SPI_CPOL)
		bus_setup |= DSPI_CTAR_CPOL;
	if (cfspi->mode & SPI_CPHA)
		bus_setup |= DSPI_CTAR_CPHA;
	if (cfspi->mode & SPI_LSB_FIRST)
		bus_setup |= DSPI_CTAR_LSBFE;

	/* Overwrite default value set in platform configuration file */
	if (cfspi->mode & SPI_MODE_MOD) {
		if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
			bus_setup |=
			    readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
		else
			bus_setup |=
			    ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);

		/* PSCSCK, PASC, PDT */
		bus_setup |= (cfspi->mode & SPI_MODE_DLY_PRE_MASK) >> 4;
		/* CSSCK, ASC, DT */
		bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
	} else {
		bus_setup |=
			(readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
	}

	cfspi->charbit =
		((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
			MCF_FRM_SZ_16BIT) ? 16 : 8;

	setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);

	return 0;
}

static int coldfire_spi_probe(struct udevice *bus)
{
	struct coldfire_spi_plat *plat = dev_get_plat(bus);
	struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
	struct dspi *dspi = cfspi->regs;
	int i;

	cfspi->regs = (struct dspi *)plat->regs_addr;

	cfspi->baudrate = plat->speed_hz;
	cfspi->mode = plat->mode;

	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {
		unsigned int ctar = 0;

		if (plat->ctar[i][0] == 0)
			break;

		ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |
			DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |
			DSPI_CTAR_PASC(plat->ctar[i][2]) |
			DSPI_CTAR_PDT(plat->ctar[i][3]) |
			DSPI_CTAR_CSSCK(plat->ctar[i][4]) |
			DSPI_CTAR_ASC(plat->ctar[i][5]) |
			DSPI_CTAR_DT(plat->ctar[i][6]) |
			DSPI_CTAR_BR(plat->ctar[i][7]);

		writel(ctar, &cfspi->regs->ctar[i]);
	}

	/* Default CTARs */
	for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)
		writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);

	dspi->mcr = DSPI_MCR_MSTR | DSPI_MCR_CSIS7 | DSPI_MCR_CSIS6 |
	    DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 |
	    DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 |
	    DSPI_MCR_CRXF | DSPI_MCR_CTXF;

	return 0;
}

#if CONFIG_IS_ENABLED(OF_REAL)
static int coldfire_dspi_of_to_plat(struct udevice *bus)
{
	fdt_addr_t addr;
	struct coldfire_spi_plat *plat = dev_get_plat(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);
	int *ctar, len;

	addr = dev_read_addr(bus);
	if (addr == FDT_ADDR_T_NONE)
		return -ENOMEM;

	plat->regs_addr = addr;

	plat->num_cs = fdtdec_get_int(blob, node, "num-cs",
				      MCF_DSPI_DEFAULT_MAX_CS);

	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
					MCF_DSPI_DEFAULT_SCK_FREQ);

	plat->mode = fdtdec_get_int(blob, node, "spi-mode",
				    MCF_DSPI_DEFAULT_MODE);

	memset(plat->ctar, 0, sizeof(plat->ctar));

	ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);

	if (ctar && len) {
		int i, q, ctar_regs;

		ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;

		if (ctar_regs > MAX_CTAR_REGS)
			ctar_regs = MAX_CTAR_REGS;

		for (i = 0; i < ctar_regs; i++) {
			for (q = 0; q < MAX_CTAR_FIELDS; q++)
				plat->ctar[i][q] = *ctar++;
		}
	}

	debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",
	      (void *)plat->regs_addr,
	       plat->speed_hz, plat->num_cs, plat->mode);

	return 0;
}

static const struct udevice_id coldfire_spi_ids[] = {
	{ .compatible = "fsl,mcf-dspi" },
	{ }
};
#endif

static const struct dm_spi_ops coldfire_spi_ops = {
	.claim_bus	= coldfire_spi_claim_bus,
	.release_bus	= coldfire_spi_release_bus,
	.xfer		= coldfire_spi_xfer,
	.set_speed	= coldfire_spi_set_speed,
	.set_mode	= coldfire_spi_set_mode,
};

U_BOOT_DRIVER(coldfire_spi) = {
	.name = "spi_coldfire",
	.id = UCLASS_SPI,
#if CONFIG_IS_ENABLED(OF_REAL)
	.of_match = coldfire_spi_ids,
	.of_to_plat = coldfire_dspi_of_to_plat,
	.plat_auto	= sizeof(struct coldfire_spi_plat),
#endif
	.probe = coldfire_spi_probe,
	.ops = &coldfire_spi_ops,
	.priv_auto	= sizeof(struct coldfire_spi_priv),
};