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path: root/drivers/fpga
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* Merge branch 'next'Tom Rini2022-07-111-0/+6
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| * Convert CONFIG_FPGA_STRATIX_V to KconfigTom Rini2022-06-281-0/+6
* | socfpga: arria10: Wait for fifo empty after writing bitstreamPaweł Anikiel2022-07-011-0/+8
* | socfpga: arria10: Improve bitstream loading speedPaweł Anikiel2022-07-011-2/+18
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* arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee2021-12-171-1/+2
* WS cleanup: remove trailing empty linesWolfgang Denk2021-09-301-1/+0
* arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2021-03-081-1/+1
* Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodia...Tom Rini2021-02-231-1/+1
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| * fpga: zynqpl: fix buffer alignmentMichael Walle2021-02-231-1/+1
* | image: Adjust the workings of fit_check_format()Simon Glass2021-02-151-3/+3
* | common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-022-0/+2
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* arm: socfpga: soc64: Add ATF support for FPGA reconfig driverChee Hong Ang2021-01-151-0/+139
* arm: socfpga: agilex: Enable FPGA Full Reconfiguration supportChee Hong Ang2020-10-091-1/+1
* fpga: intel_sdm_mb: Add watchdog resetChee Hong Ang2020-10-091-0/+3
* fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM MailboxChee Hong Ang2020-10-094-11/+12
* fpga: zynqmp: Protect zynqmp_loads() for SPLMichal Simek2020-09-231-1/+1
* fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macrosMichal Simek2020-09-231-4/+4
* xilinx: zynqmp: synchronize firmware call return payloadIbai Erkiaga2020-08-201-1/+1
* fs: fs-loader: Drop dm.h header fileSimon Glass2020-08-031-0/+1
* arm64: xilinx: Print fpga error value in hexT Karthik Reddy2020-06-242-2/+2
* fpga: zynqpl: Flush dcache only for non-bitstream dataT Karthik Reddy2020-06-241-2/+3
* fpga: zynqpl: Check if aes engine is enabledIbai Erkiaga2020-06-241-0/+8
* fpga: zynqpl: Check fpga config completionT Karthik Reddy2020-06-241-2/+17
* fpga: zynqpl: Correct PL bitstream loading sequence for zynqaesSiva Durga Prasad Paladugu2020-06-241-3/+4
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-182-0/+2
* common: Drop linux/delay.h from common headerSimon Glass2020-05-189-0/+9
* Fix some checkpatch warnings in calls to udelay()Simon Glass2020-05-181-3/+3
* common: Drop log.h from common headerSimon Glass2020-05-1811-0/+11
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
* common: Drop image.h from common headerSimon Glass2020-05-181-0/+1
* common: Drop net.h from common headerSimon Glass2020-05-183-0/+3
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-051-0/+1
* arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-072-8/+3
* common: Move ARM cache operations out of common.hSimon Glass2019-12-022-0/+2
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-021-0/+1
* arm64: zynqmp: Convert invoke_smc() to xilinx_pm_request()Michal Simek2019-10-241-7/+9
* arm64: versal: Rename versal_pm_request to xilinx_pm_requestMichal Simek2019-10-241-1/+1
* arm64: xilinx: Move firmware functions from platform to driverMichal Simek2019-10-241-0/+1
* arm64: zynqmp: use firmware driver to get versionIbai Erkiaga2019-10-081-2/+2
* firmware: zynqmp: create firmware headerIbai Erkiaga2019-10-081-0/+1
* fpga: zynqmp: Fix second local variable declarationMichal Simek2019-10-081-1/+1
* arm64: versal: fpga: Add PL bit stream load supportSiva Durga Prasad Paladugu2019-10-084-1/+68
* fpga: altera: cyclon2: Check function pointer before callingAlexander Dahl2019-07-301-1/+5
* fpga: altera: cyclon2: Fix indentationAlexander Dahl2019-07-301-16/+16
* fpga: altera: cyclon2: Fix most checkpatch warningsAlexander Dahl2019-07-301-42/+39
* fpga: virtex2: Add slave serial programming supportRobert Hancock2019-07-301-13/+83
* fpga: virtex2: Add additional clock cycles after DONE assertionRobert Hancock2019-07-301-4/+16
* fpga: virtex2: Split out image writing from pre/post operationsRobert Hancock2019-07-301-157/+174
* fpga: virtex2: added Kconfig optionRobert Hancock2019-07-301-0/+8
* fpga: virtex2: cosmetic: Cleanup code styleRobert Hancock2019-07-301-134/+136
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