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path: root/arch/x86/cpu/coreboot/coreboot.c
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* Correct SPL uses of USB_KEYBOARDSimon Glass2023-02-101-1/+1
* treewide: fdt: Move fdt_get_config_... to ofnode_conf_read...Simon Glass2021-09-251-3/+2
* x86: Make coreboot sysinfo available to any x86 boardSimon Glass2021-03-271-1/+1
* common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-021-0/+1
* x86: Rename board_final_cleanup() to board_final_init()Simon Glass2020-07-171-2/+2
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
* x86: coreboot: Allow building an SPL imageSimon Glass2020-05-041-1/+2
* common: Move checkcpu() out of common.hSimon Glass2019-12-021-0/+1
* x86: Remove x86 specific GD flags as they are not referenced at allStefan Roese2019-08-181-3/+0
* coreboot: only init usb if necessaryThomas RIENOESSL2018-12-101-1/+2
* x86: Update mtrr functions to allow leaving cache aloneSimon Glass2018-10-091-2/+2
* x86: coreboot: Add generic coreboot payload supportBin Meng2018-08-201-5/+4
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
* x86: kconfig: Select ARCH_MISC_INIT in the platform KconfigBin Meng2017-08-011-5/+0
* x86: kconfig: Let board select BOARD_EARLY_INIT_FBin Meng2017-08-011-5/+0
* board_f: x86: Use checkcpu() for CPU initSimon Glass2017-04-051-0/+5
* x86: Call board_final_cleanup() in last_stage_init()Bin Meng2016-05-231-9/+11
* x86: coreboot: Convert to use more dm driversBin Meng2015-09-091-6/+0
* x86: qemu: Implement PIRQ routingBin Meng2015-06-041-0/+5
* x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-041-3/+9
* x86: coreboot: Fix cosmetic issuesBin Meng2015-06-041-24/+3
* x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-241-0/+5
* x86: Add support for MTRRsSimon Glass2015-01-131-12/+10
* x86: Remove board_early_init_r()Simon Glass2014-11-251-11/+0
* x86: Make show_boot_progress() commonSimon Glass2014-11-211-24/+0
* x86: Tidy up coreboot header usageSimon Glass2014-11-211-2/+2
* x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-211-1/+2
* x86: Add chromebook_link boardSimon Glass2014-11-211-0/+1
* x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-211-0/+5
* x86: Fix up some missing prototypesSimon Glass2014-11-211-3/+1
* x86: Use the standard arch_cpu_init() functionSimon Glass2014-11-211-6/+5
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-141-1/+1
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
* x86: Add coreboot timestampsSimon Glass2013-05-131-0/+3
* x86: Implement panic output for corebootSimon Glass2013-05-131-0/+10
* x86: Permit bootstage and timer data to be used prior to relocationSimon Glass2013-03-041-9/+6
* x86: drop unused code in coreboot.cStefan Reinauer2012-12-061-7/+0
* x86: Provide a way to throttle port80 accessesVadim Bendebury2012-12-061-0/+21
* x86: Issue SMI to finalize Coreboot in final stageDuncan Laurie2012-12-061-0/+4
* x86: Fix MTRR clear to detect which MTRR to useDuncan Laurie2012-12-061-4/+15
* x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-061-0/+2
* x86: Clean up MTRR 7 right before jumping to the kernelStefan Reinauer2012-12-061-0/+18
* x86: Enable coreboot timestamp facility support in u-boot.Vadim Bendebury2012-12-061-0/+4
* x86: coreboot: Move non-board specific files to coreboot arch directoryStefan Reinauer2012-11-281-0/+87
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