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* Fix some checkpatch warnings in calls to udelay()Simon Glass2020-05-181-1/+1
| | | | | | | Fix up some incorrect code style in calls to functions in the linux/time.h header, mostly udelay(). Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/stringify.h from common headerSimon Glass2020-05-182-0/+2
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/ptrace.h from common headerSimon Glass2020-05-187-0/+7
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-1823-0/+23
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-187-8/+15
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-1834-0/+34
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop image.h from common headerSimon Glass2020-05-184-0/+5
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop bootstage.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop net.h from common headerSimon Glass2020-05-1832-0/+34
| | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Don't include common.h in header filesSimon Glass2020-05-181-0/+1
| | | | | | | | | | | It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org>
* efi_loader: round the memory area in efi_add_memory_map()Michael Walle2020-05-172-10/+5
| | | | | | | | | | | | | | | | | Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by: Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRATrevor Woerner2020-05-152-2/+2
| | | | | | Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* arm: orion5x: finish moving SoC to mach-orion5xTrevor Woerner2020-05-151-60/+0
| | | | | | | | The SPL linker script had been left in arch/$(ARCH)/cpu/$(CPU)/$(SOC); therefore move it to the already-established arch/$(ARCH)/mach-$(SOC) location. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* arm: lpc32xx: move SoC to mach-lpc32xxTrevor Woerner2020-05-159-588/+0
| | | | | | | | | | | | | | | | | | Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC) move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpc32xx. Following the checklist from commit 01f14456306c ("ARM: prepare for moving SoC sources into mach-*"): [1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx [2] add machine entry to arch/arm/Makefile [3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile [4] fix the Kconfig file path in arch/arm/Kconfig [5] (no MAINTAINERS update) Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* imx: imx8qm/qxp: Recover SPL data section for partition rebootPeng Fan2020-05-104-0/+47
| | | | | | | | | | | | | | | | | | | | | When doing partition reboot, the boot image won't be reloaded by ROM, it is just CPU reset to boot entry. The SW has to keep the boot image inside the RAM unchanged. It includes both the TEXT section and DATA section. For SPL, the problem is DATA section will be updated at runtime, so in next partition reboot the data is not same as the initial value from cold boot. If any code depends on the initial value, then it will have problem. This patch introduces a mechanism to recover the data section for partition reboot. It adds a new section in image for saving data section. When from cold boot, the data section will be saved to that new section at SPL early phase. When from partition reboot, the data section will be restored from the new section. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* driver: net: fm: add DM ETH supportMadalin Bucur2020-04-291-0/+2
| | | | | | | | | | | | | | Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Move GIC RD tables init to soc.cHou Zhiqiang2020-04-282-0/+48
| | | | | | | | | | | | | Move GIC redistributor tables initialization to CPU setup function. This patch introduces a GIC redistributor tables init function, and moves the function of reserving memory for GIC redistributor tables to soc.c and adds a argument for the memory size to reserve, BTW rename the function so that it is more readable. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Kconfig: Select RESV_RAM if GIC_V3_ITSHou Zhiqiang2020-04-281-0/+4
| | | | | | | | | The GIC redistributor tables initialization depends on RESV_RAM config, so select RESV_RAM if GIC_V3_ITS is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl-layerscape: Add RESV_RAM check in resv_ram addrHou Zhiqiang2020-04-281-4/+4
| | | | | | | | | The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* phy: add support for backplane kr modeFlorinel Iordache2020-04-201-0/+9
| | | | | | | | | | Add generic support for backplane kr modes currently available: 10gbase-kr, 40gbase-kr4. Remove platform generic fixups (armv8/layerscape and powerpc) for ethernet interfaces specified in device tree as supported backplane modes. Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* t210: do not enable PLLE and UPHY PLL HW PWRSEQJC Kuo2020-04-021-0/+5
| | | | | | | | | | | | | This commit removes the programming sequence that enables PLLE and UPHY PLL hardware power sequencers. Per TRM, boot software should enable PLLE and UPHY PLLs in software controlled power-on state and should power down PLL before jumping into kernel or the next stage boot software. Adds call to board_cleanup_before_linux to facilitate this. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* dm: arm64: ls1046a: add i2c DM supportBiwen Li2020-03-301-5/+5
| | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* dm: arm64: ls1043a: add i2c DM supportBiwen Li2020-03-301-5/+5
| | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1043A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Revert "sunxi: psci: avoid error address-of-packed-member"Tomasz Duszynski2020-03-181-11/+5
| | | | | | | | | | | | | | | | | | | Using memcpy() for some MMIO access is generally frowned upon and might break things on some platforms. Allwinner H3, which fails to boot, being an example here. Moreover, fields being accessed are naturally aligned and warnings produced by GCC have been quiesced for some time already by: 53dc8ae ("gcc-9: silence 'address-of-packed-member' warning") That said, it should be okay to revert this commit. This reverts commit 9bd34a69a453d409792e08c00953ce8862145e65. Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Tomasz Duszynski <tduszyns@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* dm: arm64: ls1012a: add i2c DM supportBiwen Li2020-02-041-2/+2
| | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-layerscape: spl: fix build error when DM_I2C is enabledBiwen Li2020-02-041-0/+2
| | | | | | | | | | | | | | | | | | | Fix below SPL build error when DM_I2C is enabled, - arch/arm/cpu/armv8/built-in.o: In function `board_init_f: arch/arm/cpu/armv8/fsl-layerscape/spl.c:74: undefined reference to `i2c_init_all' arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:(.text.board_init_f+0x30): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `i2c_init_all' make[2]: *** [spl/u-boot-spl] Error 1 make[1]: *** [spl/u-boot-spl] Error 2 make: *** [sub-make] Error 2 arch/arm/cpu/armv8/fsl-layerscape/spl.c: In function 'board_init_f': arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:2: warning: implicit declaration of function 'i2c_init_all'; did you mean 'misc_init_r'? [-Wimplicit-function-declaration]` Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arch: armv8: fsl-layerscape: export serdes config to environmentAlex Marginean2020-01-243-0/+74
| | | | | | | | | | | | | Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a_serdes: Add few missing serdes protocolsAlex Marginean2020-01-241-0/+4
| | | | | | | | | Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-layerscape: LS1044A/1048A: enable Only 1x 10GE portPramod Kumar2020-01-241-2/+21
| | | | | | | | | | | LS1088A has four personalities, LS1088A, LS1084A, LS1048A and LS1044A. LS1044A, LS1048A are LS1088A personalities, which support only one 1x 10GE port. MAC1 and MAC2 are associated with 1G SGMII, 2.5G SGMII, and XFI. Disable MAC1 to have only one 1x 10GE port for LS1044A, LS1048A. Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* ARM: LS1021A: remove redundant "depends on ARCH_LS1021A"Masahiro Yamada2020-01-241-3/+0
| | | | | | | | | | | These config entries are inside the menu block, which already depends on ARCH_LS1021A: menu "LS102xA architecture" depends on ARCH_LS1021A Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1012a: Make USB masters snoopableRan Wang2020-01-241-0/+5
| | | | | | | | | Program register bit of SCFG_SNPCNFGCR_USBRDSNP and SCFG_SNPCNFGCR_USBWRSNP to drive USB read/write snoop signal on LS1012A. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* common: Move hang() to the same header as panic()Simon Glass2020-01-174-0/+4
| | | | | | | | | | At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Move RAM-sizing functions to init.hSimon Glass2020-01-173-0/+3
| | | | | | | These functions relate to memory init so move them into the init header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move reset_cpu() to the CPU headerSimon Glass2020-01-1712-2/+14
| | | | | | Move this function out of common.h and into a relevant header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move get_tbclk() to time.hSimon Glass2020-01-173-3/+3
| | | | | | | This function related to timer and most of the timer functions are in time.h, so move this function there. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move clock functions into a new fileSimon Glass2020-01-1712-0/+12
| | | | | | | These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
* Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usageYangbo Lu2020-01-162-31/+20
| | | | | | | | | | | | | | The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* armv7m: cache: add mmu_set_region_dcache_behaviour() stub for compatibilityGiulio Benetti2020-01-141-0/+6
| | | | | | | Since some driver requires this function add it as an empty stub when DCACHE is OFF. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* arm: cpu: armv8: add support for arm psci reset2.Rajesh Ravi2020-01-101-0/+16
| | | | | | | | | | Current U-Boot has only support for psci reset. Adding support for arm psci reset2 allows passing of reset level and other platform sepcific parameters like strap settings to lowlevel psci implementation. Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
* Merge tag 'u-boot-imx-20200107' of ↵WIP/07Jan2020Tom Rini2020-01-072-8/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx New for 2020.04 --------------- - New boards Embedded Artists COM board Xea Board - Switch to DM: Aristainetos boards Toradex colibri (DM_ETH) iCubox GE bx50v3 mx7dsabre (DM_ETH) cx9020 - New features: Bootaux with elf files Default SYS_THUMB_BUILD for i.MX6/7 - Fixes: DHCOM i.MX6 PDK Engicam i.MX8M tools (imx8m_image) Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
| * ARM: mxs: spl_boot.c: make early_delay more robustRasmus Villemoes2020-01-071-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's true that booting normally doesn't take long enough for the register to roll (which actually happens in a little over an hour, not just a few seconds). However, the counter starts at power-on, and if the board is held in reset to be booted over USB, one actually risks hitting wrap-around during boot, which can both result in too short delays (if the "st += delay" calculation makes st small) and theoretically also unbound delays (if st ends up being UINT_MAX and one just misses sampling digctl_microseconds at that point). It doesn't take more code to DTRT, and once bitten, twice shy. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
| * arm: mxs: be more careful when enabling gpmi_clkRasmus Villemoes2020-01-071-1/+4
| | | | | | | | | | | | | | | | | | The data sheet says that the DIV field cannot change while the CLKGATE bit is set or modified. So do it a little more carefully, by first clearing the bit, waiting for that to appear, then setting the DIV field. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
| * arm: mxs: fix comments in arch_cpu_init to match the codeRasmus Villemoes2020-01-071-2/+2
| | | | | | | | | | | | | | | | The comment says to clear the bypass bit, but in fact it sets it, thus selecting ref_xtal. And the next line of code does not set the divider to 12, but to (the reset value of) 1. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* | Merge branch 'next'WIP/06Jan2020Tom Rini2020-01-067-24/+185
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in the following merges: commit 8fbbec12f7d2c18f8883f3371cfca74a98b5dd87 Merge: 87f69f467a83 63618e71e89b Author: Tom Rini <trini@konsulko.com> Date: Fri Jan 3 09:48:47 2020 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next - updates and fixes on ls1028a, lx2, ls1046a, MC-DPSPARSER support commit 87f69f467a8335b171c71bf217d2625d515acd7c Merge: c0912f9bbfb2 4466b9970319 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 24 08:18:19 2019 -0500 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards commit c0912f9bbfb26dd03d189953678691b799d35b6e Merge: 533c9f5714bd a1d6dc3f8407 Author: Tom Rini <trini@konsulko.com> Date: Wed Dec 18 07:20:19 2019 -0500 Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral commit 533c9f5714bdba79dc6f2629284d4c1a08a611d1 Merge: 553cb0688782 033e18b47bd0 Author: Tom Rini <trini@konsulko.com> Date: Tue Dec 17 07:53:08 2019 -0500 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next i2c: for next - misc: i2c_eeprom: Add partition support and add ability to query size of eeprom device and partitions - i2c common: add support for offset overflow in to address and add sandbox tests for it. commit 553cb06887825314e74a9bdac337467c77d1db88 Merge: f39abbbc531e b4f98b3b16ec Author: Tom Rini <trini@konsulko.com> Date: Thu Dec 12 08:18:59 2019 -0500 Merge tag 'dm-next-13dec19' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm into next buildman improvements including toolchain environment feature sandbox unicode support in serial
| * pci: layerscape: move PCIE related CONFIG to PCI KconfigPankaj Bansal2020-01-022-22/+0
| | | | | | | | | | | | | | | | | | move the PCIE related config from arch Kconfig to PCI Kconfig. As the PCI_LAYERSCAPE driver is being used in platform other than fsl-layerscape platforms like ls102xa. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * fsl-lsch3: soc: Enable AHB read support for Flexspi controllerKuldeep Singh2019-12-262-0/+53
| | | | | | | | | | | | | | | | | | | | | | Enable AHB support for Flexspi controller interface meaning memory can be accessed via md command using absolute addresses Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ls1028a: Configure stream IDs for integrated PCI and fix up Linux DTAlex Marginean2019-12-263-0/+111
| | | | | | | | | | | | | | | | | | | | | | Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: Add workaround for USB erratum A-050106Ran Wang2019-12-262-1/+20
| | | | | | | | | | | | | | | | | | | | USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: layerscape: fix SPL multi DTB loadingMichael Walle2019-12-261-1/+1
| | | | | | | | | | | | | | | | Mark board_fit_config_name_match() as weak so a board can overwrite the empty function. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | sunxi: psci: avoid error address-of-packed-memberHeinrich Schuchardt2019-12-181-5/+11
|/ | | | | | | | | | | | | | | | | | | | | | Compiling with GCC 9.2.1 leads to build errors: arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~ arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~ Use memcpy() and void* pointers to resolve the problem caused by packing the struct sunxi_cpucfg_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
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