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* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellWIP/29Oct2020Tom Rini2020-10-299-1254/+238
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| * mtd: nand: pxa3xx: enable NAND controller if the SoC needs itShmuel Hazan2020-10-292-10/+44
| * mtd: pxa3xx_nand: remove dead codeBaruch Siach2020-10-291-9/+3
| * mtd: pxa3xx_nand: port to use driver modelShmuel Hazan2020-10-292-63/+54
| * arm: dts: armada-cp110-master: update nand-controllerBaruch Siach2020-10-291-6/+9
| * arm: dts: armada-cp110-slave: add missing cps_nandShmuel Hazan2020-10-291-0/+16
| * arm: octeontx: Enable network support in supported boardsStefan Roese2020-10-294-0/+8
| * phy: marvell: cp110: update mode parameter for pcie power on callsIgal Liberman2020-10-291-2/+5
| * phy: marvell: cp110: let the firmware configure comphy for PCIeGrzegorz Jaszczyk2020-10-291-439/+12
| * phy: marvell: cp110: let the firmware configure the comphyGrzegorz Jaszczyk2020-10-291-727/+89
* | Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodian...Tom Rini2020-10-2974-561/+2987
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| * | xilinx: Enable SPI driver for VersalMichal Simek2020-10-291-0/+1
| * | xilinx: Consolidate board_fit_config_name_match() for Xilinx platformsMichal Simek2020-10-293-24/+11
| * | mmc: zynq_sdhci: Add common function to set input/output tapdelaysAshok Reddy Soma2020-10-292-159/+36
| * | mmc: zynq_sdhci: Extend UHS timings till hs200Ashok Reddy Soma2020-10-291-1/+1
| * | mmc: zynq_sdhci: Add clock phase delays for VersalAshok Reddy Soma2020-10-271-4/+156
| * | mmc: zynq_sdhci: Set tapdelays based on clk phase delaysAshok Reddy Soma2020-10-271-5/+123
| * | mmc: zynq_sdhci: Read clock phase delays from dtMichal Simek2020-10-271-0/+85
| * | mmc: zynq_sdhci: Move macro to the topMichal Simek2020-10-271-2/+2
| * | mmc: Define timing macro'sAshok Reddy Soma2020-10-273-22/+25
| * | Revert "mmc: zynq: parse dt when probing"Ashok Reddy Soma2020-10-273-1/+8
| * | spi: zynq_qspi: Add function descriptionAshok Reddy Soma2020-10-271-12/+36
| * | mtd: spi: Fix incorrect indentationMichal Simek2020-10-271-1/+1
| * | microblaze: Enable board_late_init()Michal Simek2020-10-271-0/+1
| * | microblaze: Wire generic xilinx board_late_init_xilinx()Michal Simek2020-10-272-14/+5
| * | xilinx: Merge together BOOT_SCRIPT_OFFSET between MB and ARMMichal Simek2020-10-273-8/+4
| * | xilinx: Remove additional newline in config filesMichal Simek2020-10-273-3/+0
| * | xilinx: Enable SF_TEST command for all ARM based platformsMichal Simek2020-10-273-0/+3
| * | xilinx: zynq: Enable AES commandMichal Simek2020-10-271-0/+1
| * | xilinx: zynq: Change types from u32 to uint32_tMichal Simek2020-10-272-2/+2
| * | xilinx: Enable FRU command for all ARM based platformsMichal Simek2020-10-273-0/+3
| * | xilinx: Add DDR base address to bootscript addressT Karthik Reddy2020-10-271-0/+9
| * | arm64: zynqmp: Fix zynqmp mini qspi max frequencyT Karthik Reddy2020-10-271-1/+1
| * | xilinx: zynqmp: Use tab for macro indentationMichal Simek2020-10-271-6/+6
| * | xilinx: zynqmp: Do not check 0 as invalid return from snprintfMichal Simek2020-10-271-1/+1
| * | xilinx: zynqmp: Fix debug message in zynqmp_get_silicon_idcode_name()Michal Simek2020-10-271-1/+1
| * | xilinx: zynqmp: Check return value from xilinx_pm_request()Michal Simek2020-10-271-1/+5
| * | xilinx: board: Add FRU decoder supportMichal Simek2020-10-271-1/+82
| * | xilinx: cmd: Add basic fru format generatorMichal Simek2020-10-273-2/+136
| * | xilinx: cmd: Add support for FRU commandsSiva Durga Prasad Paladugu2020-10-276-0/+414
| * | xilinx: common: Add Makefile to common folderMichal Simek2020-10-274-3/+7
| * | microblaze: Enable i2c DM by defaultMichal Simek2020-10-271-0/+1
| * | xilinx: common: Protect board_late_init_xilinx()Michal Simek2020-10-271-0/+2
| * | xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board KconfigMichal Simek2020-10-275-10/+23
| * | spl: fdt: Record load/entry fit-images entries in 64bit formatMichal Simek2020-10-272-12/+8
| * | spl: Use standard FIT entriesMichal Simek2020-10-275-11/+100
| * | spi: zynq_qspi: Use clk subsystem to get reference qspi clkT Karthik Reddy2020-10-271-8/+28
| * | spi: zynq_spi: Use clk subsystem to get reference spi clkT Karthik Reddy2020-10-271-7/+28
| * | serial: pl01x: Add error value checkingMichal Simek2020-10-271-1/+12
| * | xilinx: board: Add support for additional card detectionMichal Simek2020-10-271-24/+61
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