4 files changed, 78 insertions, 0 deletions
diff --git a/board/schneider/rzn1-snarc/Kconfig b/board/schneider/rzn1-snarc/Kconfig
new file mode 100644
index 0000000000..1c1c235f00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SCHNEIDER_RZN1
+
+config TEXT_BASE
+	default 0x20040000
+
+config SYS_MONITOR_LEN
+	default 524288
+
+config SYS_BOARD
+	default "rzn1-snarc"
+
+config SYS_VENDOR
+	default "schneider"
+
+config SYS_CONFIG_NAME
+	default "rzn1-snarc"
+
+endif
diff --git a/board/schneider/rzn1-snarc/Makefile b/board/schneider/rzn1-snarc/Makefile
new file mode 100644
index 0000000000..e197ca8cb4
--- /dev/null
+++ b/board/schneider/rzn1-snarc/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	:= rzn1.o
diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c
new file mode 100644
index 0000000000..09241c3a95
--- /dev/null
+++ b/board/schneider/rzn1-snarc/rzn1.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = gd->ram_base + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	struct udevice *dev;
+	int err;
+
+	/*
+	 * This will end up calling cadence_ddr_probe(),
+	 * and will also update gd->ram_size.
+	 */
+	err = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (err)
+		debug("DRAM init failed: %d\n", err);
+
+	return err;
+}
diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg b/board/schneider/rzn1-snarc/spkgimage.cfg
new file mode 100644
index 0000000000..b5faf96b00
--- /dev/null
+++ b/board/schneider/rzn1-snarc/spkgimage.cfg
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Schneider Electric
+#
+# SPKG image header, for booting on RZ/N1
+
+# b[35:32] SPKG version
+VERSION			1
+
+# b[42:41]  ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes
+NAND_ECC_BLOCK_SIZE	1
+
+# b[45]     NAND enable (boolean)
+NAND_ECC_ENABLE		1
+
+# b[50:48]  ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32
+NAND_ECC_SCHEME		3
+
+# b[63:56]  ECC bytes per block
+NAND_BYTES_PER_ECC_BLOCK 28
+
+# Provide dummy BLp header (boolean)
+ADD_DUMMY_BLP		1
+
+# Pad the image to a multiple of
+PADDING			64K