3 files changed, 48 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
new file mode 100644
index 0000000000..bfe54698b3
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN			BIT(16)
+#define PWR_CR1_ODSWEN			BIT(17)
+#define PWR_CSR1_ODRDY			BIT(16)
+#define PWR_CSR1_ODSWRDY		BIT(17)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index d6412a00cc..0117039cf2 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -95,13 +95,6 @@ struct stm32_rcc_regs {
 };
 #define STM32_RCC		((struct stm32_rcc_regs *)RCC_BASE)
 
-struct stm32_pwr_regs {
-	u32 cr1;   /* power control register 1 */
-	u32 csr1;  /* power control/status register 2 */
-	u32 cr2;   /* power control register 2 */
-	u32 csr2;  /* power control/status register 2 */
-};
-#define STM32_PWR		((struct stm32_pwr_regs *)PWR_BASE)
 
 void stm32_flash_latency_cfg(int latency);
 
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
new file mode 100644
index 0000000000..917dd46d98
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN			BIT(16)
+#define PWR_CR1_ODSWEN			BIT(17)
+#define PWR_CSR1_ODRDY			BIT(16)
+#define PWR_CSR1_ODSWRDY		BIT(17)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+	u32 cr2;   /* power control register 2 */
+	u32 csr2;  /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */