diff options
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/clock.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 1d80d9e946..6586015fd2 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -70,7 +70,7 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, * @param pllout pll output id * @param rate desired output rate * - * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) + * Return: 0 if ok, -1 on error (invalid clock id or no suitable divider) */ int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate); @@ -193,7 +193,7 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, * specific knowledge of system-level clock tree structure. * * @param periph_id peripheral to query - * @return clock ID of the peripheral's current parent clock + * Return: clock ID of the peripheral's current parent clock */ enum clock_id clock_get_periph_parent(enum periph_id periph_id); @@ -204,7 +204,7 @@ enum clock_id clock_get_periph_parent(enum periph_id periph_id); * @param periph_id peripheral to start * @param parent PLL id of required parent clock * @param rate Required clock rate in Hz - * @return rate selected in Hz, or -1U if something went wrong + * Return: rate selected in Hz, or -1U if something went wrong */ unsigned clock_start_periph_pll(enum periph_id periph_id, enum clock_id parent, unsigned rate); @@ -217,7 +217,7 @@ unsigned clock_start_periph_pll(enum periph_id periph_id, * @param periph_id peripheral to start * @param parent PLL id of parent clock (used to calculate rate, you * must know this!) - * @return clock rate of peripheral in Hz + * Return: clock rate of peripheral in Hz */ unsigned long clock_get_periph_rate(enum periph_id periph_id, enum clock_id parent); @@ -233,7 +233,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id, * @param rate Required clock rate in Hz * @param extra_div value for the second-stage divisor (NULL if one is not available) - * @return rate selected in Hz, or -1U if something went wrong + * Return: rate selected in Hz, or -1U if something went wrong */ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, enum clock_id parent, unsigned rate, int *extra_div); @@ -242,7 +242,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, * Returns the clock rate of a specified clock, in Hz. * * @param parent PLL id of clock to check - * @return rate of clock in Hz + * Return: rate of clock in Hz */ unsigned clock_get_rate(enum clock_id clkid); @@ -265,21 +265,21 @@ void clock_ll_start_uart(enum periph_id periph_id); * * @param blob FDT blob to use * @param node Node to look at - * @return peripheral ID, or PERIPH_ID_NONE if none + * Return: peripheral ID, or PERIPH_ID_NONE if none */ int clock_decode_periph_id(struct udevice *dev); /** * Checks if the oscillator bypass is enabled (XOBP bit) * - * @return 1 if bypass is enabled, 0 if not + * Return: 1 if bypass is enabled, 0 if not */ int clock_get_osc_bypass(void); /* * Checks that clocks are valid and prints a warning if not * - * @return 0 if ok, -1 on error + * Return: 0 if ok, -1 on error */ int clock_verify(void); @@ -310,7 +310,7 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); * @param mux_bits Set to number of bits in mux register * @param divider_bits Set to the relevant MASK_BITS_* value * @param type Set to the SoC-specific clock type - * @return 0 on success, -1 on error + * Return: 0 on success, -1 on error */ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, int *divider_bits, int *type); @@ -324,7 +324,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, * * @param periph_id peripheral to query * @param source raw clock source mux value - * @return the CLOCK_ID_* value @source represents + * Return: the CLOCK_ID_* value @source represents */ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); @@ -338,7 +338,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); * @param source PLL id of required parent clock * @param mux_bits Set to number of bits in mux register: 2 or 4 * @param divider_bits Set to number of divider bits (8 or 16) - * @return mux value (0-4, or -1 if not found) + * Return: mux value (0-4, or -1 if not found) */ int get_periph_clock_source(enum periph_id periph_id, enum clock_id parent, int *mux_bits, int *divider_bits); @@ -349,7 +349,7 @@ int get_periph_clock_source(enum periph_id periph_id, * provided. * * @param clk_id Clock ID according to tegra30 device tree binding - * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid + * Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid */ enum periph_id clk_id_to_periph_id(int clk_id); @@ -367,7 +367,7 @@ enum periph_id clk_id_to_periph_id(int clk_id); * @param m PLL input divider(DIVN) * @param p post divider(DIVP) * @param cpcon base PLL charge pump(CPCON) - * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot + * Return: 0 if ok, -1 on error (the requested PLL is incorrect and cannot * be overridden), 1 if PLL is already correct */ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); @@ -416,7 +416,7 @@ extern struct periph_clk_init periph_clk_init_table[]; * Enable output clock for external peripherals * * @param clk_id Clock ID to output (1, 2 or 3) - * @return 0 if OK. -ve on error + * Return: 0 if OK. -ve on error */ int clock_external_output(int clk_id); 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