diff options
Diffstat (limited to 'arch/arm/dts/r9a06g032-rzn1-snarc.dts')
-rw-r--r-- | arch/arm/dts/r9a06g032-rzn1-snarc.dts | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts b/arch/arm/dts/r9a06g032-rzn1-snarc.dts new file mode 100644 index 0000000000..7de8ee15ef --- /dev/null +++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Schneider RZ/N1 Board + * + * Based on r9a06g032-rzn1d400-db.dts + */ + +/dts-v1/; + +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> +#include "r9a06g032.dtsi" + +/ { + model = "Schneider RZ/N1 Board"; + compatible = "schneider,rzn1", "renesas,r9a06g032"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + soc { + plat_regs: syscon@4000c000 { + compatible = "syscon"; + reg = <0x4000c000 0x1000>; + }; + + system-controller@4000c000 { + regmap = <&plat_regs>; + }; + + ddrctrl: memory-controller@4000d000 { + compatible = "cadence,ddr-ctrl"; + reg = <0x4000d000 0x1000>, <0x4000e000 0x100>; + reg-names = "ddrc", "phy"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>; + clock-names = "clk_ddrc", "hclk_ddrc"; + syscon = <&plat_regs>; + status = "disabled"; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&plat_regs>; + offset = <0x198>; /* sysctrl.RSTEN */ + mask = <0x40>; /* bit 6 = SWRST_REQ */ + value = <0x40>; + }; +}; + +&ddrctrl { + status = "okay"; + + conf-1 { + size = <0x40000000>; /* 1 GB */ + #include "renesas/is43tr16256a_125k_CTL.h" + #include "r9a06g032-ddr.dtsi" + }; + conf-2 { + size = <0x10000000>; /* 256 MB */ + #include "renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h" + #include "r9a06g032-ddr.dtsi" + }; +}; + +&pinctrl { + status = "okay"; + + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + bias-disable; + }; +}; + +&uart0 { + pinctrl-0 = <&pins_uart0>; + pinctrl-names = "default"; + status = "okay"; +}; |