diff options
| -rw-r--r-- | arch/sh/Kconfig | 5 | ||||
| -rw-r--r-- | board/renesas/r0p7734/Kconfig | 12 | ||||
| -rw-r--r-- | board/renesas/r0p7734/MAINTAINERS | 7 | ||||
| -rw-r--r-- | board/renesas/r0p7734/Makefile | 7 | ||||
| -rw-r--r-- | board/renesas/r0p7734/lowlevel_init.S | 591 | ||||
| -rw-r--r-- | board/renesas/r0p7734/r0p7734.c | 58 | ||||
| -rw-r--r-- | configs/r0p7734_defconfig | 34 | ||||
| -rw-r--r-- | include/configs/r0p7734.h | 100 |
8 files changed, 0 insertions, 814 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index da4bfd2cc3..91002a9be0 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -25,10 +25,6 @@ config TARGET_MIGOR bool "Migo-R" select CPU_SH4 -config TARGET_R0P7734 - bool "Support r0p7734" - select CPU_SH4A - config TARGET_R2DPLUS bool "Renesas R2D-PLUS" select CPU_SH4 @@ -64,7 +60,6 @@ config SYS_CPU source "arch/sh/lib/Kconfig" source "board/renesas/MigoR/Kconfig" -source "board/renesas/r0p7734/Kconfig" source "board/renesas/r2dplus/Kconfig" source "board/renesas/r7780mp/Kconfig" source "board/renesas/sh7752evb/Kconfig" diff --git a/board/renesas/r0p7734/Kconfig b/board/renesas/r0p7734/Kconfig deleted file mode 100644 index 7f24f41b8f..0000000000 --- a/board/renesas/r0p7734/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_R0P7734 - -config SYS_BOARD - default "r0p7734" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "r0p7734" - -endif diff --git a/board/renesas/r0p7734/MAINTAINERS b/board/renesas/r0p7734/MAINTAINERS deleted file mode 100644 index c169ad7ecc..0000000000 --- a/board/renesas/r0p7734/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -R0P7734 BOARD -M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> -M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> -S: Maintained -F: board/renesas/r0p7734/ -F: include/configs/r0p7734.h -F: configs/r0p7734_defconfig diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile deleted file mode 100644 index 8d98016cbe..0000000000 --- a/board/renesas/r0p7734/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> -# - -obj-y := r0p7734.o -extra-y += lowlevel_init.o diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S deleted file mode 100644 index feb92f0cf4..0000000000 --- a/board/renesas/r0p7734/lowlevel_init.S +++ /dev/null @@ -1,591 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2011 Renesas Solutions Corp. - */ -#include <config.h> -#include <asm/processor.h> -#include <asm/macro.h> - -#include <asm/processor.h> - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - - /* WDT */ - write32 WDTCSR_A, WDTCSR_D - - /* MMU */ - write32 MMUCR_A, MMUCR_D - - write32 FRQCR2_A, FRQCR2_D - write32 FRQCR0_A, FRQCR0_D - - write32 CS0CTRL_A, CS0CTRL_D - write32 CS1CTRL_A, CS1CTRL_D - write32 CS0CTRL2_A, CS0CTRL2_D - - write32 CSPWCR0_A, CSPWCR0_D - write32 CSPWCR1_A, CSPWCR1_D - write32 CS1GDST_A, CS1GDST_D - - # clock mode check - mov.l MODEMR, r1 - mov.l @r1, r0 - and #6, r0 /* Check 1 and 2 bit.*/ - cmp/eq #2, r0 /* 0x02 is 533Mhz mode */ - bt init_lbsc_533 - -init_lbsc_400: - - write32 CSWCR0_A, CSWCR0_D_400 - write32 CSWCR1_A, CSWCR1_D - - bra init_dbsc3_400_pad - nop - - .align 2 - -MODEMR: .long 0xFFCC0020 -WDTCSR_A: .long 0xFFCC0004 -WDTCSR_D: .long 0xA5000000 -MMUCR_A: .long 0xFF000010 -MMUCR_D: .long 0x00000004 - -FRQCR2_A: .long 0xFFC80008 -FRQCR2_D: .long 0x00000000 -FRQCR0_A: .long 0xFFC80000 -FRQCR0_D: .long 0xCF000001 - -CS0CTRL_A: .long 0xFF800200 -CS0CTRL_D: .long 0x00000020 -CS1CTRL_A: .long 0xFF800204 -CS1CTRL_D: .long 0x00000020 - -CS0CTRL2_A: .long 0xFF800220 -CS0CTRL2_D: .long 0x00004000 - -CSPWCR0_A: .long 0xFF800280 -CSPWCR0_D: .long 0x00000000 -CSPWCR1_A: .long 0xFF800284 -CSPWCR1_D: .long 0x00000000 -CS1GDST_A: .long 0xFF8002C0 -CS1GDST_D: .long 0x00000011 - -init_lbsc_533: - - write32 CSWCR0_A, CSWCR0_D_533 - write32 CSWCR1_A, CSWCR1_D - - bra init_dbsc3_533_pad - nop - - .align 2 - -CSWCR0_A: .long 0xFF800230 -CSWCR0_D_533: .long 0x01120104 -CSWCR0_D_400: .long 0x02120114 -/* CSWCR0_D_400: .long 0x01160116 */ -CSWCR1_A: .long 0xFF800234 -CSWCR1_D: .long 0x077F077F -/* CSWCR1_D_400: .long 0x00120012 */ - -init_dbsc3_400_pad: - - write32 DBPDCNT3_A, DBPDCNT3_D - wait_timer WAIT_200US_400 - - write32 DBPDCNT0_A, DBPDCNT0_D_400 - write32 DBPDCNT3_A, DBPDCNT3_D0 - write32 DBPDCNT1_A, DBPDCNT1_D - - write32 DBPDCNT3_A, DBPDCNT3_D1 - wait_timer WAIT_32MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D2 - wait_timer WAIT_100US_400 - - write32 DBPDCNT3_A, DBPDCNT3_D3 - wait_timer WAIT_16MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D4 - wait_timer WAIT_200US_400 - - write32 DBPDCNT3_A, DBPDCNT3_D5 - wait_timer WAIT_1MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D6 - wait_timer WAIT_10KMCLK - - bra init_dbsc3_ctrl_400 - nop - - .align 2 - -init_dbsc3_533_pad: - - write32 DBPDCNT3_A, DBPDCNT3_D - wait_timer WAIT_200US_533 - - write32 DBPDCNT0_A, DBPDCNT0_D_533 - write32 DBPDCNT3_A, DBPDCNT3_D0 - write32 DBPDCNT1_A, DBPDCNT1_D - - write32 DBPDCNT3_A, DBPDCNT3_D1 - wait_timer WAIT_32MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D2 - wait_timer WAIT_100US_533 - - write32 DBPDCNT3_A, DBPDCNT3_D3 - wait_timer WAIT_16MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D4 - wait_timer WAIT_200US_533 - - write32 DBPDCNT3_A, DBPDCNT3_D5 - wait_timer WAIT_1MCLK - - write32 DBPDCNT3_A, DBPDCNT3_D6 - wait_timer WAIT_10KMCLK - - bra init_dbsc3_ctrl_533 - nop - - .align 2 - -WAIT_200US_400: .long 40000 -WAIT_200US_533: .long 53300 -WAIT_100US_400: .long 20000 -WAIT_100US_533: .long 26650 -WAIT_32MCLK: .long 32 -WAIT_16MCLK: .long 16 -WAIT_1MCLK: .long 1 -WAIT_10KMCLK: .long 10000 - -DBPDCNT0_A: .long 0xFE800200 -DBPDCNT0_D_533: .long 0x00010245 -DBPDCNT0_D_400: .long 0x00010235 -DBPDCNT1_A: .long 0xFE800204 -DBPDCNT1_D: .long 0x00000014 -DBPDCNT3_A: .long 0xFE80020C -DBPDCNT3_D: .long 0x80000000 -DBPDCNT3_D0: .long 0x800F0000 -DBPDCNT3_D1: .long 0x800F1000 -DBPDCNT3_D2: .long 0x820F1000 -DBPDCNT3_D3: .long 0x860F1000 -DBPDCNT3_D4: .long 0x870F1000 -DBPDCNT3_D5: .long 0x870F3000 -DBPDCNT3_D6: .long 0x870F7000 - -init_dbsc3_ctrl_400: - - write32 DBKIND_A, DBKIND_D - write32 DBCONF_A, DBCONF_D - - write32 DBTR0_A, DBTR0_D_400 - write32 DBTR1_A, DBTR1_D_400 - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D_400 - write32 DBTR4_A, DBTR4_D_400 - write32 DBTR5_A, DBTR5_D_400 - write32 DBTR6_A, DBTR6_D_400 - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D_400 - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D_400 - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D_400 - write32 DBTR13_A, DBTR13_D_400 - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D_400 - write32 DBTR17_A, DBTR17_D_400 - write32 DBTR18_A, DBTR18_D_400 - - write32 DBBL_A, DBBL_D - write32 DBRNK0_A, DBRNK0_D - - write32 DBCMD_A, DBCMD_D0_400 - write32 DBCMD_A, DBCMD_D1 - write32 DBCMD_A, DBCMD_D2 - write32 DBCMD_A, DBCMD_D3 - write32 DBCMD_A, DBCMD_D4 - write32 DBCMD_A, DBCMD_D5_400 - write32 DBCMD_A, DBCMD_D6 - write32 DBCMD_A, DBCMD_D7 - write32 DBCMD_A, DBCMD_D8 - write32 DBCMD_A, DBCMD_D9_400 - write32 DBCMD_A, DBCMD_D10 - write32 DBCMD_A, DBCMD_D11 - write32 DBCMD_A, DBCMD_D12 - - write32 DBBS0CNT1_A, DBBS0CNT1_D - write32 DBPDNCNF_A, DBPDNCNF_D - - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D_400 - write32 DBRFCNF2_A, DBRFCNF2_D - write32 DBRFEN_A, DBRFEN_D - write32 DBACEN_A, DBACEN_D - write32 DBACEN_A, DBACEN_D - - /* Dummy read */ - mov.l DBWAIT_A, r1 - synco - mov.l @r1, r0 - synco - - /* Dummy read */ - mov.l SDRAM_A, r1 - synco - mov.l @r1, r0 - synco - - /* need sleep 186A0 */ - - bra init_pfc_sh7734 - nop - - .align 2 - -init_dbsc3_ctrl_533: - - write32 DBKIND_A, DBKIND_D - write32 DBCONF_A, DBCONF_D - - write32 DBTR0_A, DBTR0_D_533 - write32 DBTR1_A, DBTR1_D_533 - write32 DBTR2_A, DBTR2_D - write32 DBTR3_A, DBTR3_D_533 - write32 DBTR4_A, DBTR4_D_533 - write32 DBTR5_A, DBTR5_D_533 - write32 DBTR6_A, DBTR6_D_533 - write32 DBTR7_A, DBTR7_D - write32 DBTR8_A, DBTR8_D_533 - write32 DBTR9_A, DBTR9_D - write32 DBTR10_A, DBTR10_D_533 - write32 DBTR11_A, DBTR11_D - write32 DBTR12_A, DBTR12_D_533 - write32 DBTR13_A, DBTR13_D_533 - write32 DBTR14_A, DBTR14_D - write32 DBTR15_A, DBTR15_D - write32 DBTR16_A, DBTR16_D_533 - write32 DBTR17_A, DBTR17_D_533 - write32 DBTR18_A, DBTR18_D_533 - - write32 DBBL_A, DBBL_D - write32 DBRNK0_A, DBRNK0_D - - write32 DBCMD_A, DBCMD_D0_533 - write32 DBCMD_A, DBCMD_D1 - write32 DBCMD_A, DBCMD_D2 - write32 DBCMD_A, DBCMD_D3 - write32 DBCMD_A, DBCMD_D4 - write32 DBCMD_A, DBCMD_D5_533 - write32 DBCMD_A, DBCMD_D6 - write32 DBCMD_A, DBCMD_D7 - write32 DBCMD_A, DBCMD_D8 - write32 DBCMD_A, DBCMD_D9_533 - write32 DBCMD_A, DBCMD_D10 - write32 DBCMD_A, DBCMD_D11 - write32 DBCMD_A, DBCMD_D12 - - write32 DBBS0CNT1_A, DBBS0CNT1_D - write32 DBPDNCNF_A, DBPDNCNF_D - - write32 DBRFCNF0_A, DBRFCNF0_D - write32 DBRFCNF1_A, DBRFCNF1_D_533 - write32 DBRFCNF2_A, DBRFCNF2_D - write32 DBRFEN_A, DBRFEN_D - write32 DBACEN_A, DBACEN_D - write32 DBACEN_A, DBACEN_D - - /* Dummy read */ - mov.l DBWAIT_A, r1 - synco - mov.l @r1, r0 - synco - - /* Dummy read */ - mov.l SDRAM_A, r1 - synco - mov.l @r1, r0 - synco - - /* need sleep 186A0 */ - - bra init_pfc_sh7734 - nop - - .align 2 - -DBKIND_A: .long 0xFE800020 -DBKIND_D: .long 0x00000005 -DBCONF_A: .long 0xFE800024 -DBCONF_D: .long 0x0D030A01 - -DBTR0_A: .long 0xFE800040 -DBTR0_D_533:.long 0x00000004 -DBTR0_D_400:.long 0x00000003 -DBTR1_A: .long 0xFE800044 -DBTR1_D_533:.long 0x00000003 -DBTR1_D_400:.long 0x00000002 -DBTR2_A: .long 0xFE800048 -DBTR2_D: .long 0x00000000 -DBTR3_A: .long 0xFE800050 -DBTR3_D_533:.long 0x00000004 -DBTR3_D_400:.long 0x00000003 - -DBTR4_A: .long 0xFE800054 -DBTR4_D_533:.long 0x00050004 -DBTR4_D_400:.long 0x00050003 - -DBTR5_A: .long 0xFE800058 -DBTR5_D_533:.long 0x0000000F -DBTR5_D_400:.long 0x0000000B - -DBTR6_A: .long 0xFE80005C -DBTR6_D_533:.long 0x0000000B -DBTR6_D_400:.long 0x00000008 - -DBTR7_A: .long 0xFE800060 -DBTR7_D: .long 0x00000002 /* common value */ - -DBTR8_A: .long 0xFE800064 -DBTR8_D_533:.long 0x0000000D -DBTR8_D_400:.long 0x0000000A - -DBTR9_A: .long 0xFE800068 -DBTR9_D: .long 0x00000002 /* common value */ - -DBTR10_A: .long 0xFE80006C -DBTR10_D_533:.long 0x00000004 -DBTR10_D_400:.long 0x00000003 - -DBTR11_A: .long 0xFE800070 -DBTR11_D: .long 0x00000008 /* common value */ - -DBTR12_A: .long 0xFE800074 -DBTR12_D_533:.long 0x00000009 -DBTR12_D_400:.long 0x00000008 - -DBTR13_A: .long 0xFE800078 -DBTR13_D_533:.long 0x00000022 -DBTR13_D_400:.long 0x0000001A - -DBTR14_A: .long 0xFE80007C -DBTR14_D: .long 0x00070002 /* common value */ - -DBTR15_A: .long 0xFE800080 -DBTR15_D: .long 0x00000003 /* common value */ - -DBTR16_A: .long 0xFE800084 -DBTR16_D_533:.long 0x120A1001 -DBTR16_D_400:.long 0x12091001 - -DBTR17_A: .long 0xFE800088 -DBTR17_D_533:.long 0x00040000 -DBTR17_D_400:.long 0x00030000 - -DBTR18_A: .long 0xFE80008C -DBTR18_D_533:.long 0x02010200 -DBTR18_D_400:.long 0x02000207 - -DBBL_A: .long 0xFE8000B0 -DBBL_D: .long 0x00000000 - -DBRNK0_A: .long 0xFE800100 -DBRNK0_D: .long 0x00000001 - -DBCMD_A: .long 0xFE800018 -DBCMD_D0_533: .long 0x1100006B -DBCMD_D0_400: .long 0x11000050 -DBCMD_D1: .long 0x0B000000 /* common value */ -DBCMD_D2: .long 0x2A004000 /* common value */ -DBCMD_D3: .long 0x2B006000 /* common value */ -DBCMD_D4: .long 0x29002004 /* common value */ -DBCMD_D5_533: .long 0x28000743 -DBCMD_D5_400: .long 0x28000533 -DBCMD_D6: .long 0x0B000000 /* common value */ -DBCMD_D7: .long 0x0C000000 /* common value */ -DBCMD_D8: .long 0x0C000000 /* common value */ -DBCMD_D9_533: .long 0x28000643 -DBCMD_D9_400: .long 0x28000433 -DBCMD_D10: .long 0x000000C8 /* common value */ -DBCMD_D11: .long 0x29002384 /* common value */ -DBCMD_D12: .long 0x29002004 /* common value */ - -DBBS0CNT1_A: .long 0xFE800304 -DBBS0CNT1_D: .long 0x00000000 -DBPDNCNF_A: .long 0xFE800180 -DBPDNCNF_D: .long 0x00000200 - -DBRFCNF0_A: .long 0xFE8000E0 -DBRFCNF0_D: .long 0x000001FF -DBRFCNF1_A: .long 0xFE8000E4 -DBRFCNF1_D_533: .long 0x00000805 -DBRFCNF1_D_400: .long 0x00000618 - -DBRFCNF2_A: .long 0xFE8000E8 -DBRFCNF2_D: .long 0x00000000 - -DBRFEN_A: .long 0xFE800014 -DBRFEN_D: .long 0x00000001 - -DBACEN_A: .long 0xFE800010 -DBACEN_D: .long 0x00000001 - -DBWAIT_A: .long 0xFE80001C -SDRAM_A: .long 0x0C000000 - -init_pfc_sh7734: - write32 PFC_PMMR_A, PFC_PMMR_MODESEL1 - write32 PFC_MODESEL1_A, PFC_MODESEL1_D - - write32 PFC_PMMR_A, PFC_PMMR_MODESEL2 - write32 PFC_MODESEL2_A, PFC_MODESEL2_D - - write32 PFC_PMMR_A, PFC_PMMR_IPSR3 - write32 PFC_IPSR3_A, PFC_IPSR3_D - - write32 PFC_PMMR_A, PFC_PMMR_IPSR4 - write32 PFC_IPSR4_A, PFC_IPSR4_D - - write32 PFC_PMMR_A, PFC_PMMR_IPSR11 - write32 PFC_IPSR11_A, PFC_IPSR11_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR0 - write32 PFC_GPSR0_A, PFC_GPSR0_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR1 - write32 PFC_GPSR1_A, PFC_GPSR1_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR2 - write32 PFC_GPSR2_A, PFC_GPSR2_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR3 - write32 PFC_GPSR3_A, PFC_GPSR3_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR4 - write32 PFC_GPSR4_A, PFC_GPSR4_D - - write32 PFC_PMMR_A, PFC_PMMR_GPSR5 - write32 PFC_GPSR5_A, PFC_GPSR5_D - - /* sleep 186A0 */ - - write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D - write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D - write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D - write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D - write32 GPIO4_INOUTSEL4_A, GPIO4_INOUTSEL4_D - write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D - - write32 CCR_A, CCR_D - - stc sr, r0 - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - nop - - .align 2 - -PFC_PMMR_A: .long 0xFFFC0000 - -/* MODESEL - * 28: Select IEBUS Group B - */ -PFC_MODESEL1_A: .long 0xFFFC004C -PFC_MODESEL1_D: .long 0x10000000 -PFC_PMMR_MODESEL1: .long 0xEFFFFFFF - -/* MODESEL - * 9: Select SCIF3 Group B - * 7: Select SCIF2 Group B - * 4: Select SCIF1 Group B - */ -PFC_MODESEL2_A: .long 0xFFFC0050 -PFC_MODESEL2_D: .long 0x00000290 -PFC_PMMR_MODESEL2: .long 0xFFFFFD6F - -# Enable functios -# SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A, -# EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A, -# SD1_CD_A, TX3_B, RX3_B, CS1, D15 -PFC_IPSR3_A: .long 0xFFFC0028 -PFC_IPSR3_D: .long 0x09209248 -PFC_PMMR_IPSR3: .long 0xF6DF6DB7 - -# Enable functios -# RMII0_MDIO_A , RMII0_MDC_A, -# RMII0_CRS_DV_A, RMII0_RX_ER_A, -# RMII0_TXD_EN_A, MII0_RXD1_A -PFC_IPSR4_A: .long 0xFFFC002C -PFC_IPSR4_D: .long 0x0001B6DB -PFC_PMMR_IPSR4: .long 0xFFFE4924 - -# Enable functios -# DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B, -# IETX_B, TX0_A, RMII0_TXD0_A, -# RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1 -PFC_IPSR11_A: .long 0xFFFC0048 -PFC_IPSR11_D: .long 0x002C89B0 -PFC_PMMR_IPSR11:.long 0xFFD3764F - -PFC_GPSR0_A: .long 0xFFFC0004 -PFC_GPSR0_D: .long 0xFFFFFFFF -PFC_PMMR_GPSR0: .long 0x00000000 - -PFC_GPSR1_A: .long 0xFFFC0008 -PFC_GPSR1_D: .long 0x7FBF7FFF -PFC_PMMR_GPSR1: .long 0x80408000 - -PFC_GPSR2_A: .long 0xFFFC000C -PFC_GPSR2_D: .long 0xBFC07EDF -PFC_PMMR_GPSR2: .long 0x403F8120 - -PFC_GPSR3_A: .long 0xFFFC0010 -PFC_GPSR3_D: .long 0xFFFFFFFF -PFC_PMMR_GPSR3: .long 0x00000000 - -PFC_GPSR4_A: .long 0xFFFC0014 -#if 0 /* orig */ -PFC_GPSR4_D: .long 0xFFFFFFFF -PFC_PMMR_GPSR4: .long 0x00000000 -#else -PFC_GPSR4_D: .long 0xFBFFFFFF -PFC_PMMR_GPSR4: .long 0x04000000 -#endif - -PFC_GPSR5_A: .long 0xFFFC0018 -PFC_GPSR5_D: .long 0x00000C01 -PFC_PMMR_GPSR5: .long 0xFFFFF3FE - -I2C_ICCR2_A: .long 0xFFC70001 -I2C_ICCR2_D: .long 0x00 -I2C_ICCR2_D1: .long 0x20 - -GPIO2_INOUTSEL1_A: .long 0xFFC41004 -GPIO2_INOUTSEL1_D: .long 0x80408000 -GPIO1_OUTDT1_A: .long 0xFFC41008 /* bit15: LED4, bit22: LED5 */ -GPIO1_OUTDT1_D: .long 0x80408000 -GPIO2_INOUTSEL2_A: .long 0xFFC42004 -GPIO2_INOUTSEL2_D: .long 0x40000120 -GPIO2_OUTDT2_A: .long 0xFFC42008 -GPIO2_OUTDT2_D: .long 0x40000120 -GPIO4_INOUTSEL4_A: .long 0xFFC44004 -GPIO4_INOUTSEL4_D: .long 0x04000000 -GPIO4_OUTDT4_A: .long 0xFFC44008 -GPIO4_OUTDT4_D: .long 0x04000000 - -CCR_A: .long 0xFF00001C -CCR_D: .long 0x0000090B -SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c deleted file mode 100644 index 7ebde48d29..0000000000 --- a/board/renesas/r0p7734/r0p7734.c +++ /dev/null @@ -1,58 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <netdev.h> -#include <i2c.h> - -#define MODEMR (0xFFCC0020) -#define MODEMR_MASK (0x6) -#define MODEMR_533MHZ (0x2) - -int checkboard(void) -{ - u32 r = readl(MODEMR); - if ((r & MODEMR_MASK) & MODEMR_533MHZ) - puts("CPU Clock: 533MHz\n"); - else - puts("CPU Clock: 400MHz\n"); - - puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n"); - return 0; -} - -#define MSTPSR1 (0xFFC80044) -#define MSTPCR1 (0xFFC80034) -#define MSTPSR1_GETHER (1 << 14) - -int board_init(void) -{ -#if defined(CONFIG_SH_ETHER) - u32 r = readl(MSTPSR1); - if (r & MSTPSR1_GETHER) - writel((r & ~MSTPSR1_GETHER), MSTPCR1); -#endif - - return 0; -} - -int board_late_init(void) -{ - printf("Cannot get MAC address from I2C\n"); - - return 0; -} - -#ifdef CONFIG_SMC911X -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); - return rc; -} -#endif diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig deleted file mode 100644 index 111cb5da90..0000000000 --- a/configs/r0p7734_defconfig +++ /dev/null @@ -1,34 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8FFC0000 -CONFIG_TARGET_R0P7734=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC3,115200" -CONFIG_VERSION_VARIABLE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_MISC is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SH_ETHER=y -CONFIG_SCIF_CONSOLE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h deleted file mode 100644 index 3e4ef763c9..0000000000 --- a/include/configs/r0p7734.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas Solutions r0p7734 board - * - * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - */ - -#ifndef __R0P7734_H -#define __R0P7734_H - -#define CONFIG_CPU_SH7734 1 -#define CONFIG_400MHZ_MODE 1 - -#define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT (0) -#define CONFIG_SH_ETHER_PHY_ADDR (0x0) -#define CONFIG_PHY_SMSC 1 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -/* undef to save memory */ -/* List of legal baudrate settings for this board */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_SCIF 1 -#define CONFIG_CONS_SCIF3 1 - -/* Suppress display of console information at boot */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE (0x88000000) -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) -/* Enable alternate, more extensive, memory test */ -/* Scratch address used by the alternate memory test */ -#undef CONFIG_SYS_MEMTEST_SCRATCH - -/* Enable temporary baudrate change while serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -/* - * Use hardware flash sectors protection instead - * of U-Boot software protection - */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -/* Monitor size */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) - -/* Board Clock */ -#if defined(CONFIG_400MHZ_MODE) -#define CONFIG_SYS_CLK_FREQ 50000000 -#else -#define CONFIG_SYS_CLK_FREQ 44444444 -#endif -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __R0P7734_H */ |