diff options
55 files changed, 4249 insertions, 183 deletions
@@ -2,11 +2,32 @@ Changes since U-Boot 0.2.2: ====================================================================== +* Patch by Josef Wagner, 12 Mar 2003: + - 16/32 MB and 50/80 MHz support with auto-detection for IP860 + - ETH05 and BEDBUG support for CU824 + - added support for MicroSys CPC45 + - new BOOTROM/FLASH0 and DOC base for PM826 + +* Patch by Robert Schwebel, 12 Mar 2003: + Fix the chpart command on innokom board + +* Name cleanup: + mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h + s/PPCBoot/U-Boot/ in some files + s/pImage/uImage/ in some files + +* Patch by Detlev Zundel, 15 Jan 2003: + Fix '' command line quoting + +* Patch by The LEOX team, 19 Jan 2003: + - add support for the ELPT860 board + - add support for Dallas ds164x RTC + * Patches by David Müller, 31 Jan 2003: - minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - - add support for MPL's VCMA9 (Samsung s3c2410 based) board + - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 @@ -166,6 +166,11 @@ N: Thomas Lange E: thomas@corelatus.com D: Support for GTH board; lots of PCMCIA fixes +N: The LEOX team +E: team@leox.org +D: Support for LEOX boards, DS164x RTC +W: http://www.leox.org + N: Raymond Lo E: lo@routefree.com D: Support for DOS partitions diff --git a/MAINTAINERS b/MAINTAINERS index a673cdcb64..292a290978 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -137,6 +137,10 @@ Thomas Lange <thomas@corelatus.com> GTH MPC860 +The LEOX team <team@leox.org> + + ELPT860 MPC860T + Eran Man <eran@nbase.co.il> EVB64260_750CX MPC750CX @@ -16,18 +16,18 @@ LIST="" LIST_8xx=" \ ADS860 AMX860 c2mon CCM \ - cogent_mpc8xx ESTEEM192E ETX094 FADS823 \ - FADS850SAR FADS860T FLAGADM FPS850L \ - GEN860T GENIETV GTH hermes \ - IAD210 ICU862_100MHz IP860 IVML24 \ - IVML24_128 IVML24_256 IVMS8 IVMS8_128 \ - IVMS8_256 KUP4K LANTEC lwmon \ - MBX MBX860T MHPC MVS1 \ - NETVIA NX823 pcu_e R360MPI \ - RPXClassic RPXlite RRvision SM850 \ - SPD823TS SXNI855T TOP860 TQM823L \ - TQM823L_LCD TQM850L TQM855L TQM860L \ - TQM860L_FEC TTTech v37 \ + cogent_mpc8xx ESTEEM192E ETX094 ELPT860 \ + FADS823 FADS850SAR FADS860T FLAGADM \ + FPS850L GEN860T GENIETV GTH \ + hermes IAD210 ICU862_100MHz IP860 \ + IVML24 IVML24_128 IVML24_256 IVMS8 \ + IVMS8_128 IVMS8_256 KUP4K LANTEC \ + lwmon MBX MBX860T MHPC \ + MVS1 NETVIA NX823 pcu_e \ + R360MPI RPXClassic RPXlite RRvision \ + SM850 SPD823TS SXNI855T TOP860 \ + TQM823L TQM823L_LCD TQM850L TQM855L \ + TQM860L TQM860L_FEC TTTech v37 \ " ######################################################################### @@ -48,9 +48,9 @@ LIST_4xx=" \ ######################################################################### LIST_824x=" \ - BMW CU824 MOUSSE MUSENKI \ - OXC PN62 Sandpoint8240 Sandpoint8245 \ - utx8245 \ + BMW CPC45 CU824 MOUSSE \ + MUSENKI OXC PN62 Sandpoint8240 \ + Sandpoint8245 utx8245 \ " ######################################################################### @@ -53,21 +53,6 @@ ifndef CROSS_COMPILE ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = else -## #ifeq ($(CPU),mpc8xx) -## CROSS_COMPILE = ppc_8xx- -## #endif -## #ifeq ($(CPU),ppc4xx) -## #CROSS_COMPILE = ppc_4xx- -## #endif -## #ifeq ($(CPU),mpc824x) -## #CROSS_COMPILE = ppc_82xx- -## #endif -## #ifeq ($(CPU),mpc8260) -## #CROSS_COMPILE = ppc_82xx- -## #endif -## #ifeq ($(CPU),74xx_7xx) -## #CROSS_COMPILE = ppc_74xx-) -## #endif ifeq ($(ARCH),ppc) CROSS_COMPILE = ppc_8xx- endif @@ -202,6 +187,9 @@ CCM_config: unconfig cogent_mpc8xx_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx cogent +ELPT860_config: unconfig + @./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX + ESTEEM192E_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx esteem192e @@ -457,9 +445,24 @@ WALNUT405_config:unconfig ######################################################################### ## MPC824x Systems ######################################################################### +xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))) + BMW_config: unconfig @./mkconfig $(@:_config=) ppc mpc824x bmw +CPC45_config \ +CPC45_ROMBOOT_config: unconfig + @./mkconfig $(call xtract_82xx,$@) ppc mpc824x cpc45 + @cd ./include ; \ + if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ + echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ + echo "... booting from 8-bit flash" ; \ + else \ + echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ + echo "... booting from 64-bit flash" ; \ + fi; \ + echo "export CONFIG_BOOT_ROM" >> config.mk; + CU824_config: unconfig @./mkconfig $(@:_config=) ppc mpc824x cu824 @@ -487,7 +490,6 @@ utx8245_config: unconfig ######################################################################### ## MPC8260 Systems ######################################################################### -xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))) cogent_mpc8260_config: unconfig @./mkconfig $(@:_config=) ppc mpc8260 cogent @@ -145,6 +145,8 @@ Directory Hierarchy: - cpu/mpc8260 Files specific to Motorola MPC8260 CPU - cpu/ppc4xx Files specific to IBM 4xx CPUs +- board/LEOX/ Files specific to boards manufactured by The LEOX team +- board/LEOX/elpt860 Files specific to ELPT860 boards - board/RPXClassic Files specific to RPXClassic boards - board/RPXlite Files specific to RPXlite boards @@ -338,7 +340,7 @@ The following options need to be configured: CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto, CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L, - CONFIG_V37 + CONFIG_V37, CONFIG_ELPT860 ARM based boards: ----------------- @@ -626,6 +628,7 @@ The following options need to be configured: CONFIG_RTC_MC146818 - use MC146818 RTC CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC + CONFIG_RTC_DS164x - use Dallas DS164x RTC - Timestamp Support: @@ -1716,6 +1719,7 @@ configurations; the following names are supported: FPS850L_config Sandpoint8240_config sbc8260_config GENIETV_config TQM823L_config PIP405_config GEN860T_config EBONY_config FPS860L_config + ELPT860_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile new file mode 100644 index 0000000000..abca765d72 --- /dev/null +++ b/board/LEOX/elpt860/Makefile @@ -0,0 +1,47 @@ +####################################################################### +# +# Copyright (C) 2000, 2001, 2002, 2003 +# The LEOX team <team@leox.org>, http://www.leox.org +# +# LEOX.org is about the development of free hardware and software resources +# for system on chip. +# +# Description: U-Boot port on the LEOX's ELPT860 CPU board +# ~~~~~~~~~~~ +# +####################################################################### +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +####################################################################### + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX new file mode 100644 index 0000000000..9ace97b3e8 --- /dev/null +++ b/board/LEOX/elpt860/README.LEOX @@ -0,0 +1,424 @@ +============================================================================= + + U-Boot port on the LEOX's ELPT860 CPU board + ------------------------------------------- + +LEOX.org is about the development of free hardware and software resources + for system on chip. + +For more information, contact The LEOX team <team@leox.org> + +References: +~~~~~~~~~~ + 1) Get the last stable release from denx.de: + o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2 + 2) Get the current CVS snapshot: + o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login + o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot + +============================================================================= + +The ELPT860 CPU board has the following features: + +Processor: - MPC860T @ 50MHz + - PowerPC Core + - 65 MIPS + - Caches: D->4KB, I->4KB + - CPM: 4 SCCs, 2 SMCs + - Ethernet 10/100 + - SPI, I2C, PCMCIA, Parallel + +CPU board: - DRAM: 16 MB + - FLASH: 512 KB + (2 * 4 MB) + - NVRAM: 128 KB + - 1 Serial link + - 2 Ethernet 10 BaseT Channels + +On power-up the processor jumps to the address of 0x02000100 + +Thus, U-Boot is configured to reside in flash starting at the address of +0x02001000. The environment space is located in NVRAM separately from +U-Boot, at the address of 0x03000000. + +============================================================================= + + U-Boot test results + +============================================================================= + + +################################################## +# Operation on the serial console (SMC1) +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: help +askenv - get environment variables from stdin +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootd - boot default, i.e., run 'bootcmd' +cmp - memory compare +coninfo - print console devices and informations +cp - memory copy +crc32 - checksum calculation +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +iminfo - print header information for application image +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loop - infinite loop on address range +md - memory display +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nm - memory modify (constant address) +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol + and env variables ipaddr and serverip +version - print monitor version +? - alias for 'help' + +################################################## +# Environment Variables (CFG_ENV_IS_IN_NVRAM) +############################## + +LEOX_elpt860: printenv +bootdelay=5 +loads_echo=1 +baudrate=9600 +stdin=serial +stdout=serial +stderr=serial +ethaddr=00:03:ca:00:64:df +ipaddr=192.168.0.30 +netmask=255.255.255.0 +serverip=192.168.0.1 +nfsserverip=192.168.0.1 +preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo +gatewayip=192.168.0.1 +ramargs=setenv bootargs root=/dev/ram rw +rootargs=setenv rootpath /tftp/$(ipaddr) +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsserverip):$(rootpath) +addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsserverip):$(gatewayip):$(netmask):$(hostname):eth0: +ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm +nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm +bootcmd=run ramboot +clocks_in_mhz=1 + +Environment size: 730/16380 bytes + +################################################## +# Flash Memory Information +############################## + +LEOX_elpt860: flinfo + +Bank # 1: AMD AM29F040 (4 Mbits) + Size: 512 KB in 8 Sectors + Sector Start Addresses: + 02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000 + 02050000 02060000 02070000 + +################################################## +# Board Information Structure +############################## + +LEOX_elpt860: bdinfo +memstart = 0x00000000 +memsize = 0x01000000 +flashstart = 0x02000000 +flashsize = 0x00080000 +flashoffset = 0x00030000 +sramstart = 0x00000000 +sramsize = 0x00000000 +immr_base = 0xFF000000 +bootflags = 0x00000001 +intfreq = 50 MHz +busfreq = 50 MHz +ethaddr = 00:03:ca:00:64:df +IP addr = 192.168.0.30 +baudrate = 9600 bps + +################################################## +# Image Download and run over serial port +# hello_world (S-Record image) +# ===> 1) Enter "loads" command into U-Boot monitor +# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...' +# Then select 'hello_world.srec' with the file browser +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: loads +## Ready for S-Record download ... +S804040004F3050154000501709905014C000501388D +## First Load Addr = 0x00040000 +## Last Load Addr = 0x0005018B +## Total Size = 0x0001018C = 65932 Bytes +## Start Addr = 0x00040004 +LEOX_elpt860: go 40004 This is a test !!! +## Starting application at 0x00040004 ... +Hello World +argc = 6 +argv[0] = "40004" +argv[1] = "This" +argv[2] = "is" +argv[3] = "a" +argv[4] = "test" +argv[5] = "!!!" +argv[6] = "<NULL>" +Hit any key to exit ... + +## Application terminated, rc = 0x0 + +################################################## +# Image download and run over ethernet interface +# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: run nfsboot +ARP broadcast 1 +TFTP from server 192.168.0.1; our IP address is 192.168.0.30 +Filename '/home/leox/uImage'. +Load address: 0x400000 +Loading: ################################################################# + ############################# +done +Bytes transferred = 477294 (7486e hex) +## Booting image at 00400000 ... + Image Name: Linux-2.4.4 + Image Type: PowerPC Linux Kernel Image (gzip compressed) + Data Size: 477230 Bytes = 466 kB = 0 MB + Load Address: 00000000 + Entry Point: 00000000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 +On node 0 totalpages: 4096 +zone(0): 4096 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0: +rtsched version <20010618.1050.24> +Decrementer Frequency: 3125000 +Warning: real time clock seems stuck! +Calibrating delay loop... 49.76 BogoMIPS +Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem) +Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) +Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) +Page-cache hash table entries: 4096 (order: 2, 16384 bytes) +Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) +POSIX conformance testing by UNIFIX +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Starting kswapd v1.8 +CPM UART driver version 0.03 +ttyS0 on SMC1 at 0x0280, BRG1 +block: queued sectors max/low 9701kB/3233kB, 64 slots per queue +RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP +IP: routing cache hash table of 512 buckets, 4Kbytes +TCP: Hash tables configured (established 1024 bind 1024) +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +Looking up port of RPC 100003/2 on 192.168.0.1 +Looking up port of RPC 100005/2 on 192.168.0.1 +VFS: Mounted root (nfs filesystem). +Freeing unused kernel memory: 44k init +INIT: version 2.78 booting + Welcome to DENX Embedded Linux Environment + Press 'I' to enter interactive startup. +Mounting proc filesystem: [ OK ] +Configuring kernel parameters: [ OK ] +Cannot access the Hardware Clock via any known method. +Use the --debug option to see the details of our search for an access method. +Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ] +Activating swap partitions: [ OK ] +Setting hostname 192.168.0.30: [ OK ] +Finding module dependencies: +[ OK ] +Checking filesystems +Checking all file systems. +[ OK ] +Mounting local filesystems: [ OK ] +Enabling swap space: [ OK ] +INIT: Entering runlevel: 3 +Entering non-interactive startup +Starting system logger: [ OK ] +Starting kernel logger: [ OK ] +Starting xinetd: [ OK ] + +192 login: root +Last login: Wed Dec 31 19:00:41 on ttyS0 +bash-2.04# + +################################################## +# Image download and run over ethernet interface +# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti) +############################## + +U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) + +CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present + *** Warning: CPU Core has Silicon Bugs -- Check the Errata *** +Board: ### No HW ID - assuming ELPT860 +DRAM: 16 MB +FLASH: 512 kB +In: serial +Out: serial +Err: serial +Net: SCC ETHERNET + +Type "run nfsboot" to mount root filesystem over NFS + +Hit any key to stop autoboot: 0 +LEOX_elpt860: run ramboot +ARP broadcast 1 +TFTP from server 192.168.0.1; our IP address is 192.168.0.30 +Filename '/home/leox/pMulti'. +Load address: 0x400000 +Loading: ################################################################# + ################################################################# + ################################################################# + ################################################################# + ################################################################# + ######################################################## +done +Bytes transferred = 1947816 (1db8a8 hex) +## Booting image at 00400000 ... + Image Name: linux-2.4.4-2002-03-21 Multiboot + Image Type: PowerPC Linux Multi-File Image (gzip compressed) + Data Size: 1947752 Bytes = 1902 kB = 1 MB + Load Address: 00000000 + Entry Point: 00000000 + Contents: + Image 0: 477230 Bytes = 466 kB = 0 MB + Image 1: 1470508 Bytes = 1436 kB = 1 MB + Verifying Checksum ... OK + Uncompressing Multi-File Image ... OK + Loading Ramdisk to 00e44000, end 00fab02c ... OK +Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 +On node 0 totalpages: 4096 +zone(0): 4096 pages. +zone(1): 0 pages. +zone(2): 0 pages. +Kernel command line: root=/dev/ram rw +rtsched version <20010618.1050.24> +Decrementer Frequency: 3125000 +Warning: real time clock seems stuck! +Calibrating delay loop... 49.76 BogoMIPS +Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem) +Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) +Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) +Page-cache hash table entries: 4096 (order: 2, 16384 bytes) +Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) +POSIX conformance testing by UNIFIX +Linux NET4.0 for Linux 2.4 +Based upon Swansea University Computer Society NET3.039 +Starting kswapd v1.8 +CPM UART driver version 0.03 +ttyS0 on SMC1 at 0x0280, BRG1 +block: queued sectors max/low 8741kB/2913kB, 64 slots per queue +RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df +RAMDISK: Compressed image found at block 0 +Freeing initrd memory: 1436k freed +NET4: Linux TCP/IP 1.0 for NET4.0 +IP Protocols: ICMP, UDP, TCP +IP: routing cache hash table of 512 buckets, 4Kbytes +TCP: Hash tables configured (established 1024 bind 1024) +IP-Config: Incomplete network configuration information. +NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. +VFS: Mounted root (ext2 filesystem). +Freeing unused kernel memory: 44k iné +init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname +Configuring lo... +Configuring eth0... +Configuring Gateway... + +Please press Enter to activate this console. + +ELPT860 login: root +Password: +Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz) + + a8888b. + d888888b. + 8P"YP"Y88 + _ _ 8|o||o|88 + | | |_| 8' .88 + | | _ ____ _ _ _ _ 8`._.' Y8. + | | | | _ \| | | |\ \/ / d/ `8b. + | |___ | | | | | |_| |/ \ .dP . Y8b. + |_____||_|_| |_|\____|\_/\_/ d8:' " `::88b. + d8" `Y88b + :8P ' :888 + 8a. : _a88P + ._/"Yaa_ : .| 88P| + \ YP" `| 8P `. + / \._____.d| .' + `--..__)888888P`._.' +login[21]: root login on `ttyS0' + + + +BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash) +Enter 'help' for a list of built-in commands. + +root@ELPT860:~ # diff --git a/board/LEOX/elpt860/config.mk b/board/LEOX/elpt860/config.mk new file mode 100644 index 0000000000..defc360800 --- /dev/null +++ b/board/LEOX/elpt860/config.mk @@ -0,0 +1,36 @@ +####################################################################### +# +# Copyright (C) 2000, 2001, 2002, 2003 +# The LEOX team <team@leox.org>, http://www.leox.org +# +# LEOX.org is about the development of free hardware and software resources +# for system on chip. +# +# Description: U-Boot port on the LEOX's ELPT860 CPU board +# ~~~~~~~~~~~ +# +####################################################################### +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +####################################################################### + +# +# ELPT860 board +# + +TEXT_BASE = 0x02000000 +#TEXT_BASE = 0x00FB0000 diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c new file mode 100644 index 0000000000..25645462ff --- /dev/null +++ b/board/LEOX/elpt860/elpt860.c @@ -0,0 +1,399 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team <team@leox.org>, http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +/* +** Note 1: In this file, you have to provide the following functions: +** ------ +** int board_pre_init(void) +** int checkboard(void) +** long int initdram(int board_type) +** called from 'board_init_f()' into 'common/board.c' +** +** void reset_phy(void) +** called from 'board_init_r()' into 'common/board.c' +*/ + +#include <common.h> +#include <mpc8xx.h> + +/* ------------------------------------------------------------------------- */ + +static long int dram_size (long int, long int *, long int); + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint init_sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, + 0xFFFFFC04, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */ + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, + 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */ + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34, + 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */ +}; + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, + 0xFF0FFC00, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04, + 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00, + 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, + 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00, + 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */ + _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00, + 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04, + 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04, + 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_, + 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */ +}; + +/* ------------------------------------------------------------------------- */ + +#define CFG_PC4 0x0800 + +#define CFG_DS1 CFG_PC4 + +/* + * Very early board init code (fpga boot, etc.) + */ +int +board_pre_init (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Light up the red led on ELPT860 pcb (DS1) (PCDAT) + */ + immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */ + immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */ + immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */ + + return ( 0 ); /* success */ +} + +/* + * Check Board Identity: + * + * Test ELPT860 ID string + * + * Return 1 if no second DRAM bank, otherwise returns 0 + */ + +int +checkboard (void) +{ + unsigned char *s = getenv("serial#"); + + if ( !s || strncmp(s, "ELPT860", 7) ) + printf ("### No HW ID - assuming ELPT860\n"); + + return ( 0 ); /* success */ +} + +/* ------------------------------------------------------------------------- */ + +long int +initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9; + long int size_b0 = 0; + + /* + * This sequence initializes SDRAM chips on ELPT860 board + */ + upmconfig(UPMA, (uint *)init_sdram_table, + sizeof(init_sdram_table)/sizeof(uint)); + + memctl->memc_mptpr = 0x0200; + memctl->memc_mamr = 0x18002111; + + memctl->memc_mar = 0x00000088; + memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */ + + upmconfig(UPMA, (uint *)sdram_table, + sizeof(sdram_table)/sizeof(uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + /* + * The following value is used as an address (i.e. opcode) for + * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If + * the port size is 32bit the SDRAM does NOT "see" the lower two + * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for + * MICRON SDRAMs: + * -> 0 00 010 0 010 + * | | | | +- Burst Length = 4 + * | | | +----- Burst Type = Sequential + * | | +------- CAS Latency = 2 + * | +----------- Operating Mode = Standard + * +-------------- Write Burst Mode = Programmed Burst Length + */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CFG_BR1_PRELIM; + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, + (ulong *) SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, + (ulong *) SDRAM_BASE1_PRELIM, + SDRAM_MAX_SIZE); + + if ( size8 < size9 ) /* leave configuration at 9 columns */ + { + size_b0 = size9; + /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ + } + else /* back to 8 columns */ + { + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); + /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ + } + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ( size_b0 < 0x02000000 ) + { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + { + unsigned long reg; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + udelay(10000); + + return (size_b0); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int +dram_size (long int mamr_value, + long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) + { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ( (val = *addr) != 0 ) + { + *addr = save[i]; + + return (0); + } + + for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) + { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if ( val != (~cnt) ) + { + return (cnt * sizeof(long)); + } + } + + return (maxsize); +} + +/* ------------------------------------------------------------------------- */ + +#define CFG_PA1 0x4000 +#define CFG_PA2 0x2000 + +#define CFG_LBKs (CFG_PA2 | CFG_PA1) + +void +reset_phy (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* + * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect + * and no AUI loopback + */ + immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */ + immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */ + immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */ +} diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c new file mode 100644 index 0000000000..a9238e16cf --- /dev/null +++ b/board/LEOX/elpt860/flash.c @@ -0,0 +1,615 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team <team@leox.org>, http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +/* +** Note 1: In this file, you have to provide the following variable: +** ------ +** flash_info_t flash_info[CFG_MAX_FLASH_BANKS] +** 'flash_info_t' structure is defined into 'include/flash.h' +** and defined as extern into 'common/cmd_flash.c' +** +** Note 2: In this file, you have to provide the following functions: +** ------ +** unsigned long flash_init(void) +** called from 'board_init_r()' into 'common/board.c' +** +** void flash_print_info(flash_info_t *info) +** called from 'do_flinfo()' into 'common/cmd_flash.c' +** +** int flash_erase(flash_info_t *info, +** int s_first, +** int s_last) +** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c' +** +** int write_buff (flash_info_t *info, +** uchar *src, +** ulong addr, +** ulong cnt) +** called from 'flash_write()' into 'common/cmd_flash.c' +*/ + +#include <common.h> +#include <mpc8xx.h> + + +#ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Internal Functions + */ +static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info); + +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int write_byte (flash_info_t *info, ulong dest, uchar data); + +/*----------------------------------------------------------------------- + */ + +unsigned long +flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0; + int i; + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM, + &flash_info[0]); + + if ( flash_info[0].flash_id == FLASH_UNKNOWN ) + { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0<<20); + } + + /* Remap FLASH according to real size */ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, + &flash_info[0]); + + flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE-1, + &flash_info[0]); +#endif + + flash_info[0].size = size_b0; + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +static void +flash_get_offsets (ulong base, + flash_info_t *info) +{ + int i; + +#define SECTOR_64KB 0x00010000 + + /* set up sector start adress table */ + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = base + (i * SECTOR_64KB); + } +} + +/*----------------------------------------------------------------------- + */ +void +flash_print_info (flash_info_t *info) +{ + int i; + + if ( info->flash_id == FLASH_UNKNOWN ) + { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch ( info->flash_id & FLASH_VENDMASK ) + { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_STM: printf ("STM (Thomson) "); break; + default: printf ("Unknown Vendor "); break; + } + + switch ( info->flash_id & FLASH_TYPEMASK ) + { + case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) + { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong +flash_get_size (volatile unsigned char *addr, + flash_info_t *info) +{ + short i; + uchar value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x90; + + value = addr[0]; + + switch ( value ) + { + /* case AMD_MANUFACT: */ + case 0x01: + info->flash_id = FLASH_MAN_AMD; + break; + /* case FUJ_MANUFACT: */ + case 0x04: + info->flash_id = FLASH_MAN_FUJ; + break; + /* case STM_MANUFACT: */ + case 0x20: + info->flash_id = FLASH_MAN_STM; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch ( value ) + { + case STM_ID_F040B: + case AMD_ID_F040B: + info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */ + info->sector_count = 8; + info->size = 0x00080000; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start adress table */ + for (i = 0; i < info->sector_count; i++) + { + info->start[i] = base + (i * 0x00010000); + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) + { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned char *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if ( info->flash_id != FLASH_UNKNOWN ) + { + addr = (volatile unsigned char *)info->start[0]; + + *addr = 0xF0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int +flash_erase (flash_info_t *info, + int s_first, + int s_last) +{ + volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ( (s_first < 0) || (s_first > s_last) ) + { + if ( info->flash_id == FLASH_UNKNOWN ) + { + printf ("- missing\n"); + } + else + { + printf ("- no sectors to erase\n"); + } + return ( 1 ); + } + + if ( (info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP) ) + { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return ( 1 ); + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) + { + if ( info->protect[sect] ) + { + prot++; + } + } + + if ( prot ) + { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } + else + { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0x80; + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) + { + if (info->protect[sect] == 0) /* not protected */ + { + addr = (volatile unsigned char *)(info->start[sect]); + addr[0] = 0x30; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if ( flag ) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if ( l_sect < 0 ) + goto DONE; + + start = get_timer (0); + last = start; + addr = (volatile unsigned char *)(info->start[l_sect]); + while ( (addr[0] & 0x80) != 0x80 ) + { + if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) + { + printf ("Timeout\n"); + return ( 1 ); + } + /* show that we're waiting */ + if ( (now - last) > 1000 ) /* every second */ + { + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned char *)info->start[0]; + addr[0] = 0xF0; /* reset bank */ + + printf (" done\n"); + + return ( 0 ); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int +write_buff (flash_info_t *info, + uchar *src, + ulong addr, + ulong cnt) +{ + ulong cp, wp, data; + uchar bdata; + int i, l, rc; + + if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 ) + { + /* Width of the data bus: 8 bits */ + + wp = addr; + + while ( cnt ) + { + bdata = *src++; + + if ( (rc = write_byte(info, wp, bdata)) != 0 ) + { + return (rc); + } + + ++wp; + --cnt; + } + + return ( 0 ); + } + else + { + /* Width of the data bus: 32 bits */ + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ( (l = addr - wp) != 0 ) + { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) + { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) + { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) + { + data = (data << 8) | (*(uchar *)cp); + } + + if ( (rc = write_word(info, wp, data)) != 0 ) + { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while ( cnt >= 4 ) + { + data = 0; + for (i=0; i<4; ++i) + { + data = (data << 8) | *src++; + } + if ( (rc = write_word(info, wp, data)) != 0 ) + { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if ( cnt == 0 ) + { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) + { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) + { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); + } +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_word (flash_info_t *info, + ulong dest, + ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ( (*((vu_long *)dest) & data) != data ) + { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if ( flag ) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) + { + if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + { + return (1); + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a byte to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int +write_byte (flash_info_t *info, + ulong dest, + uchar data) +{ + volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ( (*((volatile unsigned char *)dest) & data) != data ) + { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0xAA; + addr[0x02AA] = 0x55; + addr[0x0555] = 0xA0; + + *((volatile unsigned char *)dest) = data; + + /* re-enable interrupts if necessary */ + if ( flag ) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) + { + if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + { + return (1); + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds new file mode 100644 index 0000000000..77945d0dd2 --- /dev/null +++ b/board/LEOX/elpt860/u-boot.lds @@ -0,0 +1,146 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team <team@leox.org>, http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_generic/string.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/extable.o (.text) + lib_ppc/time.o (.text) + lib_ppc/ticks.o (.text) + + . = env_offset; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug new file mode 100644 index 0000000000..b81235fd4b --- /dev/null +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -0,0 +1,140 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team <team@leox.org>, http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile new file mode 100644 index 0000000000..cc66e32e2f --- /dev/null +++ b/board/cpc45/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o plx9030.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $^ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/cpc45/config.mk b/board/cpc45/config.mk new file mode 100644 index 0000000000..bf9d9debc6 --- /dev/null +++ b/board/cpc45/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# CPC45 board +# + + +ifeq ($(CONFIG_BOOT_ROM),y) + TEXT_BASE := 0xFFF00000 + PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM +else + TEXT_BASE := 0xFFF00000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c new file mode 100644 index 0000000000..01067f53e6 --- /dev/null +++ b/board/cpc45/cpc45.c @@ -0,0 +1,173 @@ +/* + * (C) Copyright 2001 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc824x.h> +#include <asm/processor.h> +#include <pci.h> + +int sysControlDisplay(int digit, uchar ascii_code); +extern void Plx9030Init(void); + + /* We have to clear the initial data area here. Couldn't have done it + * earlier because DRAM had not been initialized. + */ +int board_pre_init(void) +{ + + /* enable DUAL UART Mode on CPC45 */ + *(uchar*)DUART_DCR |= 0x1; /* set DCM bit */ + + return 0; +} + +int checkboard(void) +{ +/* + char revision = BOARD_REV; +*/ + ulong busfreq = get_bus_freq(0); + char buf[32]; + + printf("CPC45 "); +/* + printf("Revision %d ", revision); +*/ + printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); + + return 0; +} + +long int initdram(int board_type) +{ + int i, cnt; + volatile uchar * base = CFG_SDRAM_BASE; + volatile ulong * addr; + ulong save[32]; + ulong val, ret = 0; + + for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { + + addr = (volatile ulong *)base + cnt; + save[i++] = *addr; + *addr = ~cnt; + } + + addr = (volatile ulong *)base; + save[i] = *addr; + *addr = 0; + + if (*addr != 0) { + *addr = save[i]; + goto Done; + } + + for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) { + addr = (volatile ulong *)base + cnt; + val = *addr; + *addr = save[--i]; + if (val != ~cnt) { + ulong new_bank0_end = cnt * sizeof(long) - 1; + ulong mear1 = mpc824x_mpc107_getreg(MEAR1); + ulong emear1 = mpc824x_mpc107_getreg(EMEAR1); + mear1 = (mear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); + emear1 = (emear1 & 0xFFFFFF00) | + ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); + mpc824x_mpc107_setreg(MEAR1, mear1); + mpc824x_mpc107_setreg(EMEAR1, emear1); + + ret = cnt * sizeof(long); + goto Done; + } + } + + ret = CFG_MAX_RAM_SIZE; +Done: + return ret; +} + +/* + * Initialize PCI Devices, report devices found. + */ +#ifndef CONFIG_PCI_PNP + +static struct pci_config_table pci_sandpoint_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } +}; +#endif + + +struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_sandpoint_config_table, +#endif +}; + +void pci_init_board(void) +{ + pci_mpc824x_init(&hose); + + /* init PCI_to_LOCAL Bus BRIDGE */ + Plx9030Init(); + + sysControlDisplay(0,' '); + sysControlDisplay(1,'C'); + sysControlDisplay(2,'P'); + sysControlDisplay(3,'C'); + sysControlDisplay(4,' '); + sysControlDisplay(5,'4'); + sysControlDisplay(6,'5'); + sysControlDisplay(7,' '); + +} + +/************************************************************************** +* +* sysControlDisplay - controls one of the Alphanum. Display digits. +* +* This routine will write an ASCII character to the display digit requested. +* +* SEE ALSO: +* +* RETURNS: NA +*/ + +int sysControlDisplay + ( + int digit, /* number of digit 0..7 */ + uchar ascii_code /* ASCII code */ + ) +{ + if ((digit < 0) || (digit > 7)) + return (-1); + + *((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code; + + return (0); +} + diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c new file mode 100644 index 0000000000..6e81b9c335 --- /dev/null +++ b/board/cpc45/flash.c @@ -0,0 +1,493 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc824x.h> +#include <asm/processor.h> + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +#define FLASH_BANK_SIZE 0x800000 +#define MAIN_SECT_SIZE 0x40000 +#define PARAM_SECT_SIZE 0x8000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static int write_data (flash_info_t *info, ulong dest, ulong *data); +static void write_via_fpu(vu_long *addr, ulong *data); +static __inline__ unsigned long get_msr(void); +static __inline__ void set_msr(unsigned long msr); + +/*---------------------------------------------------------------------*/ +#undef DEBUG_FLASH + +/*---------------------------------------------------------------------*/ +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf(fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif +/*---------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + int i, j; + ulong size = 0; + uchar tempChar; + + /* Enable flash writes on CPC45 */ + + tempChar = BOARD_CTRL; + + tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1); + + tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0); + + BOARD_CTRL = tempChar; + + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + + addr[0] = 0x00900090; + + DEBUGF ("Flash bank # %d:\n" + "\tManuf. ID @ 0x%08lX: 0x%08lX\n" + "\tDevice ID @ 0x%08lX: 0x%08lX\n", + i, + (ulong)(&addr[0]), addr[0], + (ulong)(&addr[2]), addr[2]); + + + if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && + (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) + { + + flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) | + (INTEL_ID_28F160F3T & FLASH_TYPEMASK); + + } else { + flash_info[i].flash_id = FLASH_UNKNOWN; + addr[0] = 0xFFFFFFFF; + goto Done; + } + + DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); + + addr[0] = 0xFFFFFFFF; + + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j > 30) { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + + (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE; + } else { + flash_info[i].start[j] = CFG_FLASH_BASE + + i * FLASH_BANK_SIZE + + j * MAIN_SECT_SIZE; + } + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[1]); +#else + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#endif +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[1]); +#else + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); +#endif +#endif + +Done: + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch ((i = info->flash_id & FLASH_VENDMASK)) { + case (FLASH_MAN_INTEL & FLASH_VENDMASK): + printf ("Intel: "); + break; + default: + printf ("Unknown Vendor 0x%04x ", i); + break; + } + + switch ((i = info->flash_id & FLASH_TYPEMASK)) { + case (INTEL_ID_28F160F3T & FLASH_TYPEMASK): + printf ("28F160F3T (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type 0x%04x\n", i); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: + return; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + DEBUGF ("Erase flash bank %d sect %d ... %d\n", + info - &flash_info[0], s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (FLASH_MAN_INTEL & FLASH_VENDMASK)) { + printf ("Can erase only Intel flash types - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + DEBUGF ("Erase sect %d @ 0x%08lX\n", + sect, (ulong)addr); + + /* Disable interrupts which might cause a timeout + * here. + */ + flag = disable_interrupts(); + + addr[0] = 0x00500050; /* clear status register */ + addr[0] = 0x00200020; /* erase setup */ + addr[0] = 0x00D000D0; /* erase confirm */ + + addr[1] = 0x00500050; /* clear status register */ + addr[1] = 0x00200020; /* erase setup */ + addr[1] = 0x00D000D0; /* erase confirm */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080) ) { + if ((now=get_timer(start)) > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + addr[0] = 0x00B000B0; /* suspend erase */ + addr[0] = 0x00FF00FF; /* to read mode */ + return 1; + } + + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + addr[0] = 0x00FF00FF; + } + } + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +#define FLASH_WIDTH 8 /* flash bus width in bytes */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp, cp, msr; + int l, rc, i; + ulong data[2]; + ulong *datah = &data[0]; + ulong *datal = &data[1]; + + DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", + addr, (ulong)src, cnt); + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + msr = get_msr(); + set_msr(msr | MSR_FP); + + wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + *datah = *datal = 0; + + for (i = 0, cp = wp; i < l; i++, cp++) { + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *)cp); + } + for (; i < FLASH_WIDTH && cnt > 0; ++i) { + char tmp; + + tmp = *src; + + src++; + + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + + --cnt; ++cp; + } + + for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | + ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datah << 8) | (*(uchar *)cp); + } + + if ((rc = write_data(info, wp, data)) != 0) { + set_msr(msr); + return (rc); + } + + wp += FLASH_WIDTH; + } + + /* + * handle FLASH_WIDTH aligned part + */ + while (cnt >= FLASH_WIDTH) { + *datah = *(ulong *)src; + *datal = *(ulong *)(src + 4); + if ((rc = write_data(info, wp, data)) != 0) { + set_msr(msr); + return (rc); + } + wp += FLASH_WIDTH; + cnt -= FLASH_WIDTH; + src += FLASH_WIDTH; + } + + if (cnt == 0) { + set_msr(msr); + return (0); + } + + /* + * handle unaligned tail bytes + */ + *datah = *datal = 0; + for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { + char tmp; + + tmp = *src; + + src++; + + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | tmp; + + --cnt; + } + + for (; i < FLASH_WIDTH; ++i, ++cp) { + if (i >= 4) { + *datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); + } + + *datal = (*datal << 8) | (*(uchar *)cp); + } + + rc = write_data(info, wp, data); + set_msr(msr); + + return (rc); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t *info, ulong dest, ulong *data) +{ + vu_long *addr = (vu_long *)dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if (((addr[0] & data[0]) != data[0]) || + ((addr[1] & data[1]) != data[1]) ) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0] = 0x00400040; /* write setup */ + write_via_fpu(addr, data); + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + while (((addr[0] & 0x00800080) != 0x00800080) || + ((addr[1] & 0x00800080) != 0x00800080) ) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + addr[0] = 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + addr[0] = 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + */ +static void write_via_fpu(vu_long *addr, ulong *data) +{ + __asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); + __asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); +} +/*----------------------------------------------------------------------- + */ +static __inline__ unsigned long get_msr(void) +{ + unsigned long msr; + + __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); + return msr; +} + +static __inline__ void set_msr(unsigned long msr) +{ + __asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); +} diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c new file mode 100644 index 0000000000..e337bd200b --- /dev/null +++ b/board/cpc45/plx9030.c @@ -0,0 +1,174 @@ +/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */ +/* + * (C) Copyright 2002-2003 + * Josef Wagner, MicroSys GmbH, wagner@microsys.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Date Modification by + * ------- ---------------------------------------------- --- + * 30sep02 converted from VxWorks to LINUX wa +*/ + + +/* +DESCRIPTION + +This is the configuration module for the PLX9030 PCI to Local Bus Bridge. +It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local +registers (CS3) on CPC45. +*/ + +/* includes */ + +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> +#include <pci.h> + +/* imports */ + + +/* defines */ +#define PLX9030_VENDOR_ID 0x10B5 +#define PLX9030_DEVICE_ID 0x9030 + +#undef PLX_DEBUG + +/* PLX9030 register offsets */ +#define P9030_LAS0RR 0x00 +#define P9030_LAS1RR 0x04 +#define P9030_LAS2RR 0x08 +#define P9030_LAS3RR 0x0c +#define P9030_EROMRR 0x10 +#define P9030_LAS0BA 0x14 +#define P9030_LAS1BA 0x18 +#define P9030_LAS2BA 0x1c +#define P9030_LAS3BA 0x20 +#define P9030_EROMBA 0x24 +#define P9030_LAS0BRD 0x28 +#define P9030_LAS1BRD 0x2c +#define P9030_LAS2BRD 0x30 +#define P9030_LAS3BRD 0x34 +#define P9030_EROMBRD 0x38 +#define P9030_CS0BASE 0x3C +#define P9030_CS1BASE 0x40 +#define P9030_CS2BASE 0x44 +#define P9030_CS3BASE 0x48 +#define P9030_INTCSR 0x4c +#define P9030_CNTRL 0x50 +#define P9030_GPIOC 0x54 + +/* typedefs */ + + +/* locals */ + +static struct pci_device_id supported[] = { + { PLX9030_VENDOR_ID, PLX9030_DEVICE_ID }, + { } +}; + +/* forward declarations */ +void sysOutLong(ulong address, ulong value); + + +/*************************************************************************** +* +* Plx9030Init - init CS0..CS3 for CPC45 +* +* +* RETURNS: N/A +*/ + +void Plx9030Init (void) +{ + pci_dev_t devno; + ulong membaseCsr; /* base address of device memory space */ + int idx = 0; /* general index */ + + + /* find plx9030 device */ + + if ((devno = pci_find_devices(supported, idx++)) < 0) + { + printf("No PLX9030 device found !!\n"); + return; + } + + +#ifdef PLX_DEBUG + printf("PLX 9030 device found ! devno = 0x%x\n",devno); +#endif + + membaseCsr = PCI_PLX9030_MEMADDR; + + /* set base address */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr); + + /* enable mapped memory and IO addresses */ + pci_write_config_dword(devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + + /* configure GBIOC */ + sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */ + + /* configure CS0 (SRAM) */ + sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */ + sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */ + sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */ + /* remap CS0 (SRAM) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE); + + /* configure CS1 (ST16552 / CHAN A) */ + sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */ + sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */ + sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */ + /* remap CS1 (ST16552 / CHAN A) */ + /* remap CS1 (ST16552 / CHAN A) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE); + + /* configure CS2 (ST16552 / CHAN B) */ + sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */ + sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */ + sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */ + /* remap CS2 (ST16552 / CHAN B) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE); + + /* configure CS3 (BCSR) */ + sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */ + sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */ + sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */ + sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */ + /* remap CS3 (DISPLAY and BCSR) */ + pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE); +} + +void sysOutLong(ulong address, ulong value) +{ + *(ulong*)address = cpu_to_le32(value); +} + diff --git a/board/cpc45/u-boot.lds b/board/cpc45/u-boot.lds new file mode 100644 index 0000000000..611ac0a063 --- /dev/null +++ b/board/cpc45/u-boot.lds @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} + diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c index a7c583cc38..f960ce51ea 100644 --- a/board/cu824/cu824.c +++ b/board/cu824/cu824.c @@ -98,11 +98,11 @@ Done: */ #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_sandpoint_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, { CFG_ETH_IOBASE, - 0, - PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, + { } }; #endif diff --git a/board/emk/top860/config.mk b/board/emk/top860/config.mk new file mode 100644 index 0000000000..95917a18b6 --- /dev/null +++ b/board/emk/top860/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x80000000 diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 5505bb549b..b56707d232 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -86,81 +86,79 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; */ static struct part_info part; +static int current_part = -1; #ifdef CONFIG_MTD_INNOKOM_16MB #ifdef CONFIG_MTD_INNOKOM_64MB #error Please define only one CONFIG_MTD_INNOKOM_XXMB option. #endif struct part_info* jffs2_part_info(int part_num) { + void *jffs2_priv_saved = part.jffs2_priv; PRINTK2("jffs2_part_info: part_num=%i\n",part_num); + if (current_part == part_num) + return ∂ + /* u-boot partition */ if(part_num==0){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x00000000; part.size=256*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - return ∂ } /* primary OS+firmware partition */ if(part_num==1){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x00040000; part.size=768*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - return ∂ } - + /* secondary OS+firmware partition */ if(part_num==2){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x00100000; part.size=8*1024*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - return ∂ } /* data partition */ if(part_num==3){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x00900000; part.size=7*1024*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - + } + + if (current_part == part_num) { + part.usr_priv = ¤t_part; + part.jffs2_priv = jffs2_priv_saved; return ∂ } @@ -174,75 +172,72 @@ struct part_info* jffs2_part_info(int part_num) { #error Please define only one CONFIG_MTD_INNOKOM_XXMB option. #endif struct part_info* jffs2_part_info(int part_num) { + void *jffs2_priv_saved = part.jffs2_priv; PRINTK2("jffs2_part_info: part_num=%i\n",part_num); + if (current_part == part_num) + return ∂ + /* u-boot partition */ if(part_num==0){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x00000000; part.size=256*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - return ∂ } /* primary OS+firmware partition */ if(part_num==1){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x00040000; part.size=16*1024*1024-128*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - return ∂ } - + /* secondary OS+firmware partition */ if(part_num==2){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x01020000; part.size=16*1024*1024-128*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - return ∂ } /* data partition */ if(part_num==3){ - if(part.usr_priv==(void*)1) return ∂ - memset(&part, 0, sizeof(part)); - + part.offset=(char*)0x02000000; part.size=32*1024*1024; - + /* Mark the struct as ready */ - part.usr_priv=(void*)1; + current_part = part_num; PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - + } + + if (current_part == part_num) { + part.usr_priv = ¤t_part; + part.jffs2_priv = jffs2_priv_saved; return ∂ } @@ -336,13 +331,13 @@ void flash_print_info (flash_info_t *info) return; } - printf(" Size: %ld MB in %d Sectors\n", + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); printf(" Sector Start Addresses:"); for (i = 0; i < info->sector_count; i++) { if ((i % 5) == 0) printf ("\n "); - + printf (" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " "); } @@ -371,7 +366,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) return ERR_UNKNOWN_FLASH_VENDOR; - + prot = 0; for (sect=s_first; sect<=s_last; ++sect) { if (info->protect[sect]) prot++; @@ -421,13 +416,13 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) goto outahere; } } - + PRINTK("clearing status register\n"); - *addr = 0x0050; + *addr = 0x0050; PRINTK("resetting to read mode"); - *addr = 0x00FF; + *addr = 0x00FF; } - + printf("ok.\n"); } diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c index 11f33279ee..a20c211055 100644 --- a/board/ip860/ip860.c +++ b/board/ip860/ip860.c @@ -28,7 +28,8 @@ /* ------------------------------------------------------------------------- */ static long int dram_size (long int, long int *, long int); - +unsigned long ip860_get_dram_size(void); +unsigned long ip860_get_clk_freq (void); /* ------------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF @@ -82,8 +83,22 @@ const uint sdram_table[] = { _NOT_USED_, _NOT_USED_, _NOT_USED_, }; + /* ------------------------------------------------------------------------- */ +int board_pre_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + +/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; + return 0; +} + + +/* ------------------------------------------------------------------------- */ /* * Check Board Identity: @@ -127,6 +142,7 @@ long int initdram (int board_type) volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; + ulong refresh_val; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); @@ -134,7 +150,17 @@ long int initdram (int board_type) /* * Preliminary prescaler for refresh */ - memctl->memc_mptpr = 0x0400; + if (ip860_get_clk_freq() == 50000000) + { + memctl->memc_mptpr = 0x0400; + refresh_val = 0xC3000000; + } + else + { + memctl->memc_mptpr = 0x0200; + refresh_val = 0x9C000000; + } + memctl->memc_mar = 0x00000088; @@ -151,18 +177,22 @@ long int initdram (int board_type) /* perform SDRAM initializsation sequence */ - memctl->memc_mamr = 0xC3804114; - memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */ - udelay (1); - memctl->memc_mamr = 0xC3804118; - memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */ + memctl->memc_mamr = 0x00804114 | refresh_val; + memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */ + udelay(1); + memctl->memc_mamr = 0x00804118 | refresh_val; + memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */ + udelay (1000); /* * Check SDRAM Memory Size */ - size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE, SDRAM_MAX_SIZE); + if (ip860_get_dram_size() == 16) + size = dram_size (refresh_val | 0x00804114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE); + else + size = dram_size (refresh_val | 0x00906114, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE); udelay (1000); @@ -291,3 +321,68 @@ void reset_phy (void) } /* ------------------------------------------------------------------------- */ + +unsigned long ip860_get_clk_freq(void) +{ + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; + ulong temp; + uchar sysclk; + + if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ + sysclk = (bcsr->bd_rev & 0x18) >> 3; + else + sysclk = 0x00; + + switch (sysclk) + { + case 0x00: + temp = 50000000; + break; + + case 0x01: + temp = 80000000; + break; + + default: + temp = 50000000; + break; + } + + return (temp); + +} + + +/* ------------------------------------------------------------------------- */ + +unsigned long ip860_get_dram_size(void) +{ + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; + ulong temp; + uchar dram_size; + + if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */ + dram_size = (bcsr->bd_rev & 0xE0) >> 5; + else + dram_size = 0x00; /* default is 16 MB */ + + switch (dram_size) + { + case 0x00: + temp = 16; + break; + + case 0x01: + temp = 32; + break; + + default: + temp = 16; + break; + } + + return (temp); + +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/pm826/config.mk b/board/pm826/config.mk index 8502e3f107..d2ab4fe985 100644 --- a/board/pm826/config.mk +++ b/board/pm826/config.mk @@ -33,10 +33,10 @@ # ifeq ($(CONFIG_BOOT_ROM),y) - TEXT_BASE := 0x60000000 + TEXT_BASE := 0xFF800000 PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM else - TEXT_BASE := 0x40000000 + TEXT_BASE := 0xFF000000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/trab/flash.c b/board/trab/flash.c index d86c4bf770..27c2a5b490 100644 --- a/board/trab/flash.c +++ b/board/trab/flash.c @@ -185,9 +185,12 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) return ERR_INVAL; } - if ((info->flash_id & FLASH_VENDMASK) != - (FLASH_MAN_AMD & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; + switch (info->flash_id & FLASH_VENDMASK) { + case (FLASH_MAN_AMD & FLASH_VENDMASK): break; /* OK */ + case (FLASH_MAN_FUJ & FLASH_VENDMASK): break; /* OK */ + default: + debug ("## flash_erase: unknown manufacturer\n"); + return (ERR_UNKNOWN_FLASH_VENDOR); } prot = 0; diff --git a/board/trab/vfd.c b/board/trab/vfd.c index 5e601ef794..894e3157d6 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -55,7 +55,8 @@ #define BLAU 0x0C #define VIOLETT 0X0D -ulong frame_buf_size; +/* MAGIC */ +#define FRAME_BUF_SIZE ((256*4*56)/8) #define frame_buf_offs 4 /* Supported VFD Types */ @@ -75,19 +76,13 @@ void init_grid_ctrl(void) ulong adr, grid_cycle; unsigned int bit, display; unsigned char temp, bit_nr; - ulong val; /* * clear frame buffer (logical clear => set to "black") */ - if (gd->vfd_inv_data == 0) - val = 0; - else - val = ~0; - - for (adr = gd->fb_base; adr <= (gd->fb_base+7168); adr += 4) { - (*(volatile ulong*)(adr)) = val; - } + memset ((void *)(gd->fb_base), + gd->vfd_inv_data ? 0xFF : 0, + FRAME_BUF_SIZE); switch (gd->vfd_type) { case VFD_TYPE_T119C: @@ -97,8 +92,8 @@ void init_grid_ctrl(void) (grid_cycle + 200) * 4 + frame_buf_offs + display; /* wrap arround if offset (see manual S3C2400) */ - if (bit>=frame_buf_size*8) - bit = bit - (frame_buf_size * 8); + if (bit>=FRAME_BUF_SIZE*8) + bit = bit - (FRAME_BUF_SIZE * 8); adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); bit_nr = bit % 8; bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; @@ -114,8 +109,8 @@ void init_grid_ctrl(void) else bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; /* grid nr. 0 */ /* wrap arround if offset (see manual S3C2400) */ - if (bit>=frame_buf_size*8) - bit = bit-(frame_buf_size*8); + if (bit>=FRAME_BUF_SIZE*8) + bit = bit-(FRAME_BUF_SIZE*8); adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); bit_nr = bit%8; bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; @@ -135,8 +130,8 @@ void init_grid_ctrl(void) (253 - grid_cycle) * 4 + frame_buf_offs + display; /* wrap arround if offset (see manual S3C2400) */ - if (bit>=frame_buf_size*8) - bit = bit - (frame_buf_size * 8); + if (bit>=FRAME_BUF_SIZE*8) + bit = bit - (FRAME_BUF_SIZE * 8); adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); bit_nr = bit % 8; bit_nr = (bit_nr > 3) ? bit_nr-4 : bit_nr+4; @@ -151,8 +146,8 @@ void init_grid_ctrl(void) bit = grid_cycle*256*4+(252-grid_cycle)*4+frame_buf_offs+display; /* wrap arround if offset (see manual S3C2400) */ - if (bit>=frame_buf_size*8) - bit = bit-(frame_buf_size*8); + if (bit>=FRAME_BUF_SIZE*8) + bit = bit-(FRAME_BUF_SIZE*8); adr = gd->fb_base+(bit/32)*4+(3-(bit%32)/8); bit_nr = bit%8; bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; @@ -263,8 +258,8 @@ void create_vfd_table(void) * wrap arround if offset * (see manual S3C2400) */ - if (pixel>=frame_buf_size*8) - pixel = pixel-(frame_buf_size*8); + if (pixel>=FRAME_BUF_SIZE*8) + pixel = pixel-(FRAME_BUF_SIZE*8); adr = gd->fb_base+(pixel/32)*4+(3-(pixel%32)/8); bit_nr = pixel%8; bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4; @@ -466,7 +461,7 @@ int drv_vfd_init(void) /* frame buffer startadr */ rLCDSADDR1 = gd->fb_base >> 1; /* frame buffer endadr */ - rLCDSADDR2 = (gd->fb_base + frame_buf_size) >> 1; + rLCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; rLCDSADDR3 = ((256/4)); debug ("LCDSADDR1: %lX\n", rLCDSADDR1); @@ -490,11 +485,8 @@ ulong vfd_setmem (ulong addr) { ulong size; - /* MAGIC */ - frame_buf_size = (256*4*56)/8; - /* Round up to nearest full page */ - size = (frame_buf_size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); + size = (FRAME_BUF_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1); debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr); diff --git a/board/v37/flash.c b/board/v37/flash.c index 4de0e14757..cb0e676a13 100644 --- a/board/v37/flash.c +++ b/board/v37/flash.c @@ -23,7 +23,7 @@ /* * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * PPCboot port on RPXlite board + * U-Boot port on RPXlite board * * Some of flash control words are modified. (from 2x16bit device * to 4x8bit device) diff --git a/board/v37/v37.c b/board/v37/v37.c index 764aff7916..f463af8e12 100644 --- a/board/v37/v37.c +++ b/board/v37/v37.c @@ -23,7 +23,7 @@ /* * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * PPCboot port on RPXlite board + * U-Boot port on RPXlite board * * DRAM related UPMA register values are modified. * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c index 763f4181ac..4b411b3d37 100644 --- a/common/cmd_fdos.c +++ b/common/cmd_fdos.c @@ -53,7 +53,7 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* pre-set Boot file name */ if ((name = getenv("bootfile")) == NULL) { - name = "pImage"; + name = "uImage"; } switch (argc) { diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index fc1d9c40f2..8df80612a7 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -83,7 +83,7 @@ jffs2_part_info(int part_num) int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - char *filename = "pImage"; + char *filename = "uImage"; ulong offset = CFG_LOAD_ADDR; int size; struct part_info *part; diff --git a/common/main.c b/common/main.c index 401efcf854..9ee32a5804 100644 --- a/common/main.c +++ b/common/main.c @@ -640,8 +640,6 @@ static void process_macros (const char *input, char *output) case 0: /* Waiting for (unescaped) $ */ if ((c == '\'') && (prev != '\\')) { state = 3; - if (inputcnt) - inputcnt--; break; } if ((c == '$') && (prev != '\\')) { @@ -694,8 +692,6 @@ static void process_macros (const char *input, char *output) case 3: /* Waiting for ' */ if ((c == '\'') && (prev != '\\')) { state = 0; - if (inputcnt) - inputcnt--; } else { *(output++) = c; outputcnt--; diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index c0ee5de2e9..4bd91f98ca 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -42,8 +42,8 @@ void cpu_init_f (volatile immap_t * immr) { #ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; - ulong reg; #endif + ulong reg; /* SYPCR - contains watchdog control (11-9) */ diff --git a/doc/README-i386 b/doc/README-i386 index 99b3e198c4..862f3f7a3a 100644 --- a/doc/README-i386 +++ b/doc/README-i386 @@ -1,4 +1,4 @@ -This is my attempt to port PPCBoot to the i386 platform. This +This is my attempt to port U-Boot to the i386 platform. This work was sponsored by my emplyer, Omicron Ceti AB. http://www.omicron.se It is currently capable of booting a linux bzImage from flash on @@ -28,13 +28,13 @@ To use this code on the CDP: 2) Program it in to the CDP flashbank with remon - ppcboot.bin should be programmed att offset 0x7e000 and the kernel at + u-boot.bin should be programmed att offset 0x7e000 and the kernel at offset 0. If you want to use a jffs2 root file system (not included here), it should be programmed to offset 0x100000. remon> z remon> yi - remon> ns ppcboot.bin 7e0000 + remon> ns u-boot.bin 7e0000 remon> ns bzImage 0 remon> ns image.jffs2 100000 @@ -43,7 +43,7 @@ To use this code on the CDP: remon> z remon> g -4) PPCboot should output some message and a prompt on the terminal, to +4) U-Boot should output some message and a prompt on the terminal, to start the kernel issue the following command: BOOT> bootm diff --git a/doc/README.IPHASE4539 b/doc/README.IPHASE4539 index d3db38ef54..9302ff5ce4 100644 --- a/doc/README.IPHASE4539 +++ b/doc/README.IPHASE4539 @@ -332,10 +332,10 @@ Linux: $ make IPHASE4539_config $ make oldconfig $ make dep - $ make pImage - $ cp -p arch/ppc/mbxboot/pImage /tftpboot + $ make uImage + $ cp -p arch/ppc/mbxboot/uImage /tftpboot - Load pImage via tftp and boot it. + Load uImage via tftp and boot it. Flash organisation: diff --git a/include/asm-i386/ppcboot-i386.h b/include/asm-i386/u-boot-i386.h index 704526e2ff..6e5e059592 100644 --- a/include/asm-i386/ppcboot-i386.h +++ b/include/asm-i386/u-boot-i386.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef _PPCBOOT_I386_H_ -#define _PPCBOOT_I386_H_ 1 +#ifndef _U_BOOT_I386_H_ +#define _U_BOOT_I386_H_ 1 /* for the following variables, see start.S */ extern ulong i386boot_start; /* code start (in flash) */ @@ -50,4 +50,4 @@ int board_init(void); int dram_init (void); -#endif /* _PPCBOOT_I386_H_ */ +#endif /* _U_BOOT_I386_H_ */ diff --git a/include/common.h b/include/common.h index bce0132afc..ac2a57d9a3 100644 --- a/include/common.h +++ b/include/common.h @@ -149,7 +149,7 @@ void setenv (char *, char *); # include <asm/u-boot-arm.h> /* ARM version to be fixed! */ #endif /* CONFIG_ARM */ #ifdef CONFIG_I386 /* x86 version to be fixed! */ -# include <asm/ppcboot-i386.h> +# include <asm/u-boot-i386.h> #endif /* CONFIG_I386 */ void pci_init (void); diff --git a/include/commproc.h b/include/commproc.h index 159c294f84..5ff82b71a8 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -595,6 +595,32 @@ typedef struct scc_enet { #endif /* CONFIG_PCU_E, CONFIG_CCM */ +/*** ELPT860 *********************************************************/ + +#ifdef CONFIG_ELPT860 +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +# define PROFF_ENET PROFF_SCC1 +# define CPM_CR_ENET CPM_CR_CH_SCC1 +# define SCC_ENET 0 + +# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ +# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ +# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ + +# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ +# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ +# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +# define SICR_ENET_MASK ((uint)0x000000FF) +# define SICR_ENET_CLKRT ((uint)0x00000025) +#endif /* CONFIG_ELPT860 */ + /*** ESTEEM 192E **************************************************/ #ifdef CONFIG_ESTEEM192E /* ESTEEM192E diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h new file mode 100644 index 0000000000..ed843d40a4 --- /dev/null +++ b/include/configs/CPC45.h @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * + * Configuration settings for the CPC45 board. + * + */ + +/* ------------------------------------------------------------------------- */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC824X 1 +#define CONFIG_MPC8245 1 +#define CONFIG_CPC45 1 + + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + 0 /* CFG_CMD_DATE */ ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include <cmd_confdefs.h> + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#if 1 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* Print Buffer Size + */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) + +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ + +#define CFG_SDRAM_BASE 0x00000000 + +#if defined(CONFIG_BOOT_ROM) +#define CFG_FLASH_BASE 0xFF000000 +#else +#define CFG_FLASH_BASE 0xFF800000 +#endif + +#define CFG_RESET_ADDRESS 0xFFF00100 + +#define CFG_EUMB_ADDR 0xFCE00000 + +#define CFG_MONITOR_BASE TEXT_BASE + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ +#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ + + /* Maximum amount of RAM. + */ +#define CFG_MAX_RAM_SIZE 0x10000000 + + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#undef CFG_RAMBOOT +#else +#define CFG_RAMBOOT +#endif + + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area + */ + + /* Size in bytes reserved for initial data + */ +#define CFG_GBL_DATA_SIZE 128 + +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL + +#define CFG_NS16550_REG_SIZE 1 + +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) +#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) +#define DUART_DCR (CFG_EUMB_ADDR + 0x4511) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + * For the detail description refer to the MPC8240 user's manual. + */ + +#define CONFIG_SYS_CLK_FREQ 33000000 +#define CFG_HZ 1000 +/* + * SDRAM Configuration Settings + * Please note: currently only 64 and 128 MB SDRAM size supported + * set CFG_SDRAM_SIZE to 64 or 128 + * Memory configuration using SPD information stored on the SODIMMs + * not yet supported. + */ + +#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */ + + /* Bit-field values for MCCR1. + */ +#define CFG_ROMNAL 0 +#define CFG_ROMFAL 7 + +#if (CFG_SDRAM_SIZE == 64) /* 64 MB */ +#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ +#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */ +#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */ +#else +# error "SDRAM size not supported" +#endif +#define CFG_BANK1_ROW 0 +#define CFG_BANK2_ROW 0 +#define CFG_BANK3_ROW 0 +#define CFG_BANK4_ROW 0 +#define CFG_BANK5_ROW 0 +#define CFG_BANK6_ROW 0 +#define CFG_BANK7_ROW 0 + + /* Bit-field values for MCCR2. + */ +#define CFG_REFINT 430 /* Refresh interval */ + + /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. + */ +#define CFG_BSTOPRE 192 + + /* Bit-field values for MCCR3. + */ +#define CFG_REFREC 2 /* Refresh to activate interval */ +#define CFG_RDLAT 3 /* Data latancy from read command */ + + /* Bit-field values for MCCR4. + */ +#define CFG_PRETOACT 2 /* Precharge to activate interval */ +#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ +#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ +#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ +#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ +#define CFG_ACTORW 2 +#define CFG_REGISTERD_TYPE_BUFFER 1 +#define CFG_EXTROM 1 +#define CFG_REGDIMM 0 + +/* Memory bank settings. + * Only bits 20-29 are actually used from these vales to set the + * start/end addresses. The upper two bits will always be 0, and the lower + * 20 bits will be 0x00000 for a start address, or 0xfffff for an end + * address. Refer to the MPC8240 book. + */ + +#define CFG_BANK0_START 0x00000000 +#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) +#define CFG_BANK0_ENABLE 1 +#define CFG_BANK1_START 0x3ff00000 +#define CFG_BANK1_END 0x3fffffff +#define CFG_BANK1_ENABLE 0 +#define CFG_BANK2_START 0x3ff00000 +#define CFG_BANK2_END 0x3fffffff +#define CFG_BANK2_ENABLE 0 +#define CFG_BANK3_START 0x3ff00000 +#define CFG_BANK3_END 0x3fffffff +#define CFG_BANK3_ENABLE 0 +#define CFG_BANK4_START 0x3ff00000 +#define CFG_BANK4_END 0x3fffffff +#define CFG_BANK4_ENABLE 0 +#define CFG_BANK5_START 0x3ff00000 +#define CFG_BANK5_END 0x3fffffff +#define CFG_BANK5_ENABLE 0 +#define CFG_BANK6_START 0x3ff00000 +#define CFG_BANK6_END 0x3fffffff +#define CFG_BANK6_ENABLE 0 +#define CFG_BANK7_START 0x3ff00000 +#define CFG_BANK7_END 0x3fffffff +#define CFG_BANK7_ENABLE 0 + +#define CFG_ODCR 0xff + +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) + +#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ +#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ +#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + + /* Warining: environment is not EMBEDDED in the ppcboot code. + * It's stored in flash separately. + */ +#define CFG_ENV_IS_IN_FLASH 1 + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000) +#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ +#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ +#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#define SRAM_BASE 0x80000000 /* SRAM base address */ +#define SRAM_END 0x801FFFFF + +/*---------------------------------------------------------------------*/ +/* CPC45 Memory Map */ +/*---------------------------------------------------------------------*/ +#define SRAM_BASE 0x80000000 /* SRAM base address */ +#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ +#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ +#define BCSR_BASE 0x80600000 /* board control / status registers */ +#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ +#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */ +#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ + + +/*---------------------------------------------------------------------*/ +/* CPC45 Control/Status Registers */ +/*---------------------------------------------------------------------*/ +#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) +#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) +#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) +#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) +#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) +#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) +#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) +#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) +#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) +#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) + +/* IRQ_ENA_1 bit definitions */ +#define I_ENA_1_IERA 0x80 /* INTA enable */ +#define I_ENA_1_IERB 0x40 /* INTB enable */ +#define I_ENA_1_IERC 0x20 /* INTC enable */ +#define I_ENA_1_IERD 0x10 /* INTD enable */ + +/* IRQ_STAT_1 bit definitions */ +#define I_STAT_1_INTA 0x80 /* INTA status */ +#define I_STAT_1_INTB 0x40 /* INTB status */ +#define I_STAT_1_INTC 0x20 /* INTC status */ +#define I_STAT_1_INTD 0x10 /* INTD status */ + +/* IRQ_ENA_2 bit definitions */ +#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ +#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ +#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ +#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ +#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ +#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ +#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ +#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ + +/* IRQ_STAT_2 bit definitions */ +#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ +#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ +#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ +#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ +#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ +#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ +#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ +#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ + +/* BOARD_CTRL bit definitions */ +#define USER_LEDS 2 /* 2 user LEDs */ + +#if (USER_LEDS == 4) +#define B_CTRL_WRSE 0x80 +#define B_CTRL_KRSE 0x40 +#define B_CTRL_FWRE 0x20 /* Flash write enable */ +#define B_CTRL_FWPT 0x10 /* Flash write protect */ +#define B_CTRL_LED3 0x08 /* LED 3 control */ +#define B_CTRL_LED2 0x04 /* LED 2 control */ +#define B_CTRL_LED1 0x02 /* LED 1 control */ +#define B_CTRL_LED0 0x01 /* LED 0 control */ +#else +#define B_CTRL_WRSE 0x80 +#define B_CTRL_KRSE 0x40 +#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ +#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ +#define B_CTRL_LED1 0x08 /* LED 1 control */ +#define B_CTRL_LED0 0x04 /* LED 0 control */ +#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ +#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ +#endif + +/* BOARD_STAT bit definitions */ +#define B_STAT_WDGE 0x80 +#define B_STAT_WDGS 0x40 +#define B_STAT_WRST 0x20 +#define B_STAT_KRST 0x10 +#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ +#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ +#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ +#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ + +/*---------------------------------------------------------------------*/ +/* Display addresses */ +/*---------------------------------------------------------------------*/ +#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ +#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ +#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ + +#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ +#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ + +#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ +#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ +#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ +#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ +#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ +#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ +#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ +#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP + +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ + +#define CONFIG_EEPRO100 + +#define PCI_ENET0_IOADDR 0x00104000 +#define PCI_ENET0_MEMADDR 0x82000000 +#define PCI_PLX9030_MEMADDR 0x82100000 +#endif /* __CONFIG_H */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index ae8525f9b9..9712d479c1 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -171,7 +171,7 @@ CFG_CMD_EEPROM | \ CFG_CMD_DATE | \ CFG_CMD_I2C | \ - CFG_CMD_DOC) + CFG_CMD_DOC ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -329,8 +329,8 @@ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 #define CFG_EEPROM_PAGE_WRITE_BITS 4 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (2048 - 512) #endif /* diff --git a/include/configs/CU824.h b/include/configs/CU824.h index ed38ef6446..40ba25a62c 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -60,9 +60,10 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ CFG_CMD_DHCP | \ CFG_CMD_PCI | \ - 0/* CFG_CMD_DATE */ ) + 0 /* CFG_CMD_DATE */ ) /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ @@ -302,4 +303,7 @@ #define CFG_ETH_DEV_FN 0x7800 #define CFG_ETH_IOBASE 0x00104000 +#define CONFIG_EEPRO100 +#define PCI_ENET0_IOADDR 0x00104000 +#define PCI_ENET0_MEMADDR 0x80000000 #endif /* __CONFIG_H */ diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h new file mode 100644 index 0000000000..e9561b9eb4 --- /dev/null +++ b/include/configs/ELPT860.h @@ -0,0 +1,390 @@ +/* +**===================================================================== +** +** Copyright (C) 2000, 2001, 2002, 2003 +** The LEOX team <team@leox.org>, http://www.leox.org +** +** LEOX.org is about the development of free hardware and software resources +** for system on chip. +** +** Description: U-Boot port on the LEOX's ELPT860 CPU board +** ~~~~~~~~~~~ +** +**===================================================================== +** +** This program is free software; you can redistribute it and/or +** modify it under the terms of the GNU General Public License as +** published by the Free Software Foundation; either version 2 of +** the License, or (at your option) any later version. +** +** This program is distributed in the hope that it will be useful, +** but WITHOUT ANY WARRANTY; without even the implied warranty of +** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +** GNU General Public License for more details. +** +** You should have received a copy of the GNU General Public License +** along with this program; if not, write to the Free Software +** Foundation, Inc., 59 Temple Place, Suite 330, Boston, +** MA 02111-1307 USA +** +**===================================================================== +*/ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ +#define CONFIG_MPC860T 1 +#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#undef CONFIG_8xx_CONS_SMC2 +#undef CONFIG_8xx_CONS_NONE + +#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ +#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ + +/* BOOT arguments */ +#define CONFIG_PREBOOT \ + "echo;" \ + "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "rootargs=setenv rootpath /tftp/$(ipaddr)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off panic=1\0" \ + "ramboot=tftp 400000 /home/paugaml/pMulti;" \ + "run ramargs;bootm\0" \ + "nfsboot=tftp 400000 /home/paugaml/uImage;" \ + "run rootargs;run nfsargs;run addip;bootm\0" \ + "" +#define CONFIG_BOOTCOMMAND "run ramboot" + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ +#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ +#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x00100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Environment Variables and Storages + */ +#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ + +#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ +#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ + +#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_ETHADDR 00:01:77:00:60:40 +#define CONFIG_IPADDR 192.168.0.30 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_GATEWAYIP 192.168.0.1 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFF000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x02000000 +#define CFG_NVRAM_BASE 0x03000000 + +#if defined(CFG_ENV_IS_IN_FLASH) +# if defined(DEBUG) +# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ +# else +# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +# endif +#else +# if defined(DEBUG) +# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +# else +# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +# endif +#endif + +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ +#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ + /* 8 top NVRAM locations */ + +#if defined(CFG_ENV_IS_IN_NVRAM) +# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ +# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) +#else +# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#define CFG_SIUMCR (SIUMCR_DBGC11) + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * RTCSC - Real-Time Clock Status and Control Register 11-27 + *----------------------------------------------------------------------- + * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC + * enabled + */ +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 + *----------------------------------------------------------------------- + * Reset PLL lock status sticky bit, timer expired status bit and timer + * interrupt status bit - leave PLL multiplication factor unchanged ! + */ +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_TBS | \ + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler + *----------------------------------------------------------------------- + * + */ +#ifdef DEBUG +# define CFG_DER 0xFFE7400F /* Debug Enable Register */ +#else +# define CFG_DER 0 +#endif + +/* + * Init Memory Controller: + * ~~~~~~~~~~~~~~~~~~~~~~ + * + * BR0 and OR0 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ + +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) + +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * BR1 and OR1 (SDRAM) + * + */ +#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */ +#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ + +/* SDRAM timing: */ +#define CFG_OR_TIMING_SDRAM 0x00000000 + +#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM ) +#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +/* + * BR2 and OR2 (NVRAM) + * + */ +#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */ +#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ + +#define CFG_OR2_PRELIM 0xFFF80160 +#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) + +/* + * Memory Periodic Timer Prescaler + */ + +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ + +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/*----------------------------------------------------------------------- + * Internal Definitions + *----------------------------------------------------------------------- + * + */ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + + +#endif /* __CONFIG_H */ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index 6fa2d19c2f..d7dce71e31 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -35,6 +35,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_IP860 1 /* ...on a IP860 board */ +#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 9600 @@ -45,10 +46,6 @@ #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0" -#define CONFIG_ETHADDR 00:30:bf:01:02:d2 -#define CONFIG_IPADDR 10.0.0.5 -#define CONFIG_SERVERIP 10.0.0.2 - #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ @@ -230,10 +227,13 @@ SIUMCR_DBGC11 | SIUMCR_MLRC10) /*----------------------------------------------------------------------- - * Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails + * Clock Setting - get clock frequency from Board Revision Register *----------------------------------------------------------------------- */ -#define CONFIG_8xx_GCLK_FREQ 50000000 +#ifndef __ASSEMBLY__ +extern unsigned long ip860_get_clk_freq (void); +#endif +#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq() /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -430,6 +430,8 @@ typedef struct ip860_bcsr_s { unsigned char wd_trigger; /* +1A Watchdog trigger register */ unsigned char reservedD; unsigned char rmw_req; /* +1C RMW request register */ + unsigned char reservedE; + unsigned char bd_rev; /* +1E Board Revision register */ } ip860_bcsr_t; #endif /* __ASSEMBLY__ */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h index b56da695e8..d95596cadf 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -158,9 +158,9 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_BEDBUG | \ CFG_CMD_DATE | \ + CFG_CMD_DOC | \ CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_DOC) + CFG_CMD_I2C ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -211,11 +211,11 @@ * Flash and Boot ROM mapping */ -#define CFG_BOOTROM_BASE 0x60000000 +#define CFG_BOOTROM_BASE 0xFF800000 #define CFG_BOOTROM_SIZE 0x00080000 -#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_BASE 0xFF000000 #define CFG_FLASH0_SIZE 0x02000000 -#define CFG_DOC_BASE 0x60000000 +#define CFG_DOC_BASE 0xFF800000 #define CFG_DOC_SIZE 0x00100000 @@ -245,8 +245,8 @@ #define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_EEPROM_PAGE_WRITE_BITS 4 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_OFFSET 0 -#define CFG_ENV_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (2048 - 512) #endif /*----------------------------------------------------------------------- diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 0750116246..6c37208c05 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -70,7 +70,7 @@ "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ "ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \ "loadp 100000; bootm" - /* "tftpboot 100000 pImage; bootm" */ + /* "tftpboot 100000 uImage; bootm" */ #else /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index ad36c95603..acfe747cec 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -75,7 +75,7 @@ "setenv filesize;saveenv\0" \ "kernel_addr=40040000\0" \ "ramdisk_addr=40100000\0" \ - "kernel_img=/tftpboot/pImage\0" \ + "kernel_img=/tftpboot/uImage\0" \ "kernel_load=tftp 200000 $(kernel_img)\0" \ "net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \ "flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0" \ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index bbd5939f2f..9ad1839154 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -74,7 +74,7 @@ #define CONFIG_IPADDR 10.0.0.98 #define CONFIG_SERVERIP 10.0.0.1 #undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000" +#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000" /*----------------------------------------------------------------------*/ /* diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 6836326828..cc51ce6674 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -71,7 +71,7 @@ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/pImage\0" \ + "bootfile=/tftpboot/TQM860L/uImage\0" \ "kernel_addr=40040000\0" \ "ramdisk_addr=40100000\0" \ "" diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 71e08ce817..60aacfb762 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -67,7 +67,7 @@ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/pImage\0" \ + "bootfile=/tftpboot/TQM860L/uImage\0" \ "kernel_addr=40040000\0" \ "ramdisk_addr=40100000\0" \ "" diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index ac0e28a15e..37363a25ff 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -67,7 +67,7 @@ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/pImage\0" \ + "bootfile=/tftpboot/TQM860L/uImage\0" \ "kernel_addr=40040000\0" \ "ramdisk_addr=40100000\0" \ "" diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 5564b2310e..0d0b8c3162 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -67,7 +67,7 @@ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM860L/pImage\0" \ + "bootfile=/tftpboot/TQM860L/uImage\0" \ "kernel_addr=40040000\0" \ "ramdisk_addr=40100000\0" \ "" diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 66c79356f4..fa466007c9 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -97,7 +97,7 @@ "bootm $(kernel_addr)\0" \ "flash_self=run ramargs addip add_wdt addfb add_misc;" \ "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 100000 /tftpboot/pImage.lwmon;" \ + "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \ "run nfsargs addip add_wdt addfb;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "load=tftp 100000 /tftpboot/u-boot.bin\0" \ diff --git a/lib_ppc/board.c b/lib_ppc/board.c index a6464f0016..c617049f58 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -635,12 +635,15 @@ void board_init_r (gd_t *id, ulong dest_addr) icache_enable (); /* it's time to enable the instruction cache */ #endif -#if defined(CONFIG_BAB7xx) +#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45) /* - * Do pci configuration on BAB 7xx _before_ the flash - * is initialised, because we need the ISA bridge there. + * Do PCI configuration on BAB7xx and CPC45 _before_ the flash + * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus + * bridge there. */ pci_init (); +#endif +#if defined(CONFIG_BAB7xx) /* * Initialise the ISA bridge */ @@ -821,6 +824,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \ defined(CONFIG_CCM) || \ + defined(CONFIG_ELPT860) || \ defined(CONFIG_EP8260) || \ defined(CONFIG_IP860) || \ defined(CONFIG_IVML24) || \ diff --git a/rtc/Makefile b/rtc/Makefile index 5d6c7f557a..5e471a6fd6 100644 --- a/rtc/Makefile +++ b/rtc/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = librtc.a OBJS = date.o \ - ds1302.o ds1306.o ds1307.o ds1337.o ds1556.o ds174x.o \ + ds1302.o ds1306.o ds1307.o ds1337.o ds1556.o ds164x.o ds174x.o \ m41t11.o m48t35ax.o mc146818.o mk48t59.o \ mpc8xx.o pcf8563.o diff --git a/rtc/ds164x.c b/rtc/ds164x.c new file mode 100644 index 0000000000..3f329c73cc --- /dev/null +++ b/rtc/ds164x.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2002 + * ARIO Data Networks, Inc. dchiu@ariodata.com + * + * modified for DS164x: + * The LEOX team <team@leox.org>, http://www.leox.org + * + * Based on MontaVista DS1743 code and U-Boot mc146818 code + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for the DS164x RTC + */ + +/* #define RTC_DEBUG */ + +#include <common.h> +#include <command.h> +#include <rtc.h> + + +#if defined(CONFIG_RTC_DS164x) && (CONFIG_COMMANDS & CFG_CMD_DATE) + +static uchar rtc_read(unsigned int addr ); +static void rtc_write(unsigned int addr, uchar val); +static uchar bin2bcd(unsigned int n); +static unsigned bcd2bin(uchar c); + +#define RTC_EPOCH 2000 /* century */ + +/* + * DS164x registers layout + */ +#define RTC_BASE ( CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE ) + +#define RTC_YEAR ( RTC_BASE + 0x07 ) +#define RTC_MONTH ( RTC_BASE + 0x06 ) +#define RTC_DAY_OF_MONTH ( RTC_BASE + 0x05 ) +#define RTC_DAY_OF_WEEK ( RTC_BASE + 0x04 ) +#define RTC_HOURS ( RTC_BASE + 0x03 ) +#define RTC_MINUTES ( RTC_BASE + 0x02 ) +#define RTC_SECONDS ( RTC_BASE + 0x01 ) +#define RTC_CONTROL ( RTC_BASE + 0x00 ) + +#define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */ +#define RTC_CA_WRITE 0x80 +#define RTC_CA_READ 0x40 +#define RTC_CONTROLB RTC_SECONDS /* OSC=bit7 */ +#define RTC_CB_OSC_DISABLE 0x80 +#define RTC_CONTROLC RTC_DAY_OF_WEEK /* FT=bit6 */ +#define RTC_CC_FREQ_TEST 0x40 + +/* ------------------------------------------------------------------------- */ + +void rtc_get( struct rtc_time *tmp ) +{ + uchar sec, min, hour; + uchar mday, wday, mon, year; + + uchar reg_a; + + reg_a = rtc_read( RTC_CONTROLA ); + /* lock clock registers for read */ + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); + + sec = rtc_read( RTC_SECONDS ); + min = rtc_read( RTC_MINUTES ); + hour = rtc_read( RTC_HOURS ); + mday = rtc_read( RTC_DAY_OF_MONTH ); + wday = rtc_read( RTC_DAY_OF_WEEK ); + mon = rtc_read( RTC_MONTH ); + year = rtc_read( RTC_YEAR ); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); + +#ifdef RTC_DEBUG + printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, + hour, min, sec ); +#endif + tmp->tm_sec = bcd2bin( sec & 0x7F ); + tmp->tm_min = bcd2bin( min & 0x7F ); + tmp->tm_hour = bcd2bin( hour & 0x3F ); + tmp->tm_mday = bcd2bin( mday & 0x3F ); + tmp->tm_mon = bcd2bin( mon & 0x1F ); + tmp->tm_wday = bcd2bin( wday & 0x07 ); + + /* glue year in century (2000) */ + tmp->tm_year = bcd2bin( year ) + RTC_EPOCH; + + tmp->tm_yday = 0; + tmp->tm_isdst= 0; +#ifdef RTC_DEBUG + printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); +#endif +} + +void rtc_set( struct rtc_time *tmp ) +{ + uchar reg_a; + +#ifdef RTC_DEBUG + printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); +#endif + /* lock clock registers for write */ + reg_a = rtc_read( RTC_CONTROLA ); + rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); + + rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); + + rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); + rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); + rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); + rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); + rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); + + /* break year in century */ + rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); + + /* unlock clock registers after read */ + rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); +} + +void rtc_reset (void) +{ + uchar reg_a, reg_b; + + reg_a = rtc_read( RTC_CONTROLA ); + reg_b = rtc_read( RTC_CONTROLB ); + + if ( reg_b & RTC_CB_OSC_DISABLE ) + { + printf( "real-time-clock was stopped. Now starting...\n" ); + reg_a |= RTC_CA_WRITE; + reg_b &= ~RTC_CB_OSC_DISABLE; + + rtc_write( RTC_CONTROLA, reg_a ); + rtc_write( RTC_CONTROLB, reg_b ); + } + + /* make sure read/write clock register bits are cleared */ + reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); + rtc_write( RTC_CONTROLA, reg_a ); +} + +/* ------------------------------------------------------------------------- */ + +static uchar rtc_read( unsigned int addr ) +{ + uchar val = *(volatile unsigned char*)(addr); + +#ifdef RTC_DEBUG + printf( "rtc_read: %x:%x\n", addr, val ); +#endif + return( val ); +} + +static void rtc_write( unsigned int addr, uchar val ) +{ +#ifdef RTC_DEBUG + printf( "rtc_write: %x:%x\n", addr, val ); +#endif + *(volatile unsigned char*)(addr) = val; +} + +static unsigned bcd2bin (uchar n) +{ + return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); +} + +static unsigned char bin2bcd (unsigned int n) +{ + return (((n / 10) << 4) | (n % 10)); +} + +#endif /* CONFIG_RTC_DS164x && CFG_CMD_DATE */ diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index 1c22e7143d..696e30efda 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -22,7 +22,7 @@ */ /* - * Command line user interface to firmware (=PPCBoot) environment. + * Command line user interface to firmware (=U-Boot) environment. * * Implements: * fw_printenv [ name ... ] |