diff options
93 files changed, 5818 insertions, 208 deletions
@@ -17,66 +17,115 @@ Alexander Graf <agraf@csgraf.de> <agraf@suse.de> Allen Martin <amartin@nvidia.com> +Amanda Baze <amanda.baze@amd.com> <nicole.baze@xilinx.com> +Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> <amit.kumar-mahapatra@xilinx.com> Andreas Bießmann <andreas.devel@googlemail.com> Andreas Bießmann <andreas@biessmann.org> Aneesh V <aneesh@ti.com> Anup Patel <anup@brainfault.org> <anup.patel@wdc.com> +Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.com> +Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com> +Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com> Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com> +Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com> +Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com> +Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com> Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com> Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com> +Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com> Dirk Behme <dirk.behme@googlemail.com> +Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com> Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com> Fabio Estevam <fabio.estevam@nxp.com> +Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com> +Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com> Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com> Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de> +Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com> +Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> +Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com> +Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com> <izhar.ameer.shaikh@xilinx.com> Jagan Teki <402jagan@gmail.com> Jagan Teki <jaganna@gmail.com> Jagan Teki <jaganna@xilinx.com> Jagan Teki <jagannadh.teki@gmail.com> Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com> +Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com> Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net> -Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org> -Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com> +John Linn <john.linn@amd.com> <john.linn@xilinx.com> +Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com> +Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com> +Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com> +Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com> +Lukasz Majewski <lukma@denx.de> Marek Behún <kabel@kernel.org> <marek.behun@nic.cz> Marek Behún <kabel@kernel.org> Marek Behun <marek.behun@nic.cz> Marek Vasut <marex@denx.de> <marek.vasut+renesas@gmail.com> Marek Vasut <marex@denx.de> <marek.vasut@gmail.com> Marek Vasut <marex@denx.de> <marex at denx.de> Markus Klotzbuecher <mk@denx.de> -Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com> Masahiro Yamada <yamada.masahiro@socionext.com> <masahiroy@kernel.org> +Masahiro Yamada <yamada.masahiro@socionext.com> <yamada.m@jp.panasonic.com> +Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz> Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com> -Michal Simek <michal.simek@xilinx.com> <monstr@monstr.eu> -Michal Simek <michal.simek@xilinx.com> <Monstr@seznam.cz> -Michal Simek <michal.simek@xilinx.com> <root@monstr.eu> +Michal Simek <michal.simek@amd.com> <monstr@monstr.eu> +Michal Simek <michal.simek@amd.com> <root@monstr.eu> +Mirza <Taimoor_Mirza@mentor.com> +Mounika Grace Akula <mounika.akula@amd.com> <mounika.grace.akula@xilinx.com> +Mubin Usman Sayyed <mubin.sayyed@amd.com> <mubin.usman.sayyed@xilinx.com> +Nathalie Chan King Choy <nathalie.chan-king-choy@amd.com> <nathalie.chan-king-choy@xilinx.com> +Nathalie Chan King Choy <nathalie.chan-king-choy@amd.com> <nathalie@xilinx.com> +Nava kishore Manne <nava.kishore.manne@amd.com> <nava.manne@xilinx.com> +Neal Frager <neal.frager@amd.com> <neal.frager@xilinx.com> Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com> Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de> Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com> Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com> Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com> +Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com> Prabhakar Kushwaha <prabhakar@freescale.com> +Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@amd.com> <punnaiah.choudary.kalluri@xilinx.com> +Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.com> Rajeshwari Shinde <rajeshwari.s@samsung.com> -Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es> +Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com> +Ravi Patel <ravi.patel@amd.com> <ravi.patel@xilinx.com> Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com> +Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es> +Rohit Visavalia <rohit.visavalia@amd.com> <rohit.visavalia@xilinx.com> Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com> +Saeed Nowshadi <saeed.nowshadi@amd.com> <saeed.nowshadi@xilinx.com> +Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> <lakshmi.sai.krishna.potthuri@xilinx.com> +Sai Pavan Boddu <sai.pavan.boddu@amd.com> <sai.pavan.boddu@xilinx.com> +Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com> Sandeep Paulraj <s-paulraj@ti.com> +Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com> Shaohui Xie <Shaohui.Xie@freescale.com> +Shravya Kumbham <shravya.kumbham@amd.com> <shravya.kumbham@xilinx.com> +Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> <shubhrajyoti.datta@xilinx.com> +Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.paladugu@xilinx.com> +Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com> +Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com> +Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com> Stefan Roese <sr@denx.de> <stroese> Stefano Babic <sbabic@denx.de> +Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com> Tom Rini <trini@konsulko.com> <trini@ti.com> +Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com> TsiChung Liew <Tsi-Chung.Liew@freescale.com> -Wolfgang Denk <wd@denx.de> <wdenk> -Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de> -Wolfgang Denk <wd@denx.de> <wd@pollux.(none)> -Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de> -Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de> +Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com> +Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com> +Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com> +Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com> Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de> Wolfgang Denk <wd@denx.de> <wd@castor.denx.de> -Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de> +Wolfgang Denk <wd@denx.de> <wd@fifi.denx.de> Wolfgang Denk <wd@denx.de> <wd@nyx.(none)> -York Sun <yorksun@freescale.com> +Wolfgang Denk <wd@denx.de> <wd@nyx.denx.de> +Wolfgang Denk <wd@denx.de> <wd@pollux.(none)> +Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de> +Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de> +Wolfgang Denk <wd@denx.de> <wdenk> York Sun <york.sun@nxp.com> +York Sun <yorksun@freescale.com> Łukasz Majewski <l.majewski@samsung.com> -Lukasz Majewski <lukma@denx.de> -Mirza <Taimoor_Mirza@mentor.com> @@ -2119,7 +2119,7 @@ tools/version.h: include/version.h $(Q)mkdir -p $(dir $@) $(call if_changed,copy) -envtools: scripts_basic $(version_h) $(timestamp_h) tools/version.h +envtools: u-boot-initial-env scripts_basic $(version_h) $(timestamp_h) tools/version.h $(Q)$(MAKE) $(build)=tools/env tools-only: export TOOLS_ONLY=y diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index f1e4e26b8f..e33e53636a 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -107,6 +107,11 @@ config ARMV7_LPAE Say Y here to use the long descriptor page table format. This is required if U-Boot runs in HYP mode. +config ARMV7_SET_CORTEX_SMPEN + bool + help + Enable the ARM Cortex ACTLR.SMP enable bit in U-boot. + config SPL_ARMV7_SET_CORTEX_SMPEN bool help diff --git a/arch/arm/dts/r9a06g032-ddr.dtsi b/arch/arm/dts/r9a06g032-ddr.dtsi new file mode 100644 index 0000000000..8c7d0873fe --- /dev/null +++ b/arch/arm/dts/r9a06g032-ddr.dtsi @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0 + + cadence,ctl-000 = < + DENALI_CTL_00_DATA + DENALI_CTL_01_DATA + DENALI_CTL_02_DATA + DENALI_CTL_03_DATA + DENALI_CTL_04_DATA + DENALI_CTL_05_DATA + DENALI_CTL_06_DATA + DENALI_CTL_07_DATA + DENALI_CTL_08_DATA + DENALI_CTL_09_DATA + + DENALI_CTL_10_DATA + DENALI_CTL_11_DATA + DENALI_CTL_12_DATA + DENALI_CTL_13_DATA + DENALI_CTL_14_DATA + DENALI_CTL_15_DATA + DENALI_CTL_16_DATA + DENALI_CTL_17_DATA + DENALI_CTL_18_DATA + DENALI_CTL_19_DATA + + DENALI_CTL_20_DATA + DENALI_CTL_21_DATA + DENALI_CTL_22_DATA + DENALI_CTL_23_DATA + DENALI_CTL_24_DATA + DENALI_CTL_25_DATA + DENALI_CTL_26_DATA + DENALI_CTL_27_DATA + DENALI_CTL_28_DATA + DENALI_CTL_29_DATA + + DENALI_CTL_30_DATA + DENALI_CTL_31_DATA + DENALI_CTL_32_DATA + DENALI_CTL_33_DATA + DENALI_CTL_34_DATA + DENALI_CTL_35_DATA + DENALI_CTL_36_DATA + DENALI_CTL_37_DATA + DENALI_CTL_38_DATA + DENALI_CTL_39_DATA + + DENALI_CTL_40_DATA + DENALI_CTL_41_DATA + DENALI_CTL_42_DATA + DENALI_CTL_43_DATA + DENALI_CTL_44_DATA + DENALI_CTL_45_DATA + DENALI_CTL_46_DATA + DENALI_CTL_47_DATA + DENALI_CTL_48_DATA + DENALI_CTL_49_DATA + + DENALI_CTL_50_DATA + DENALI_CTL_51_DATA + DENALI_CTL_52_DATA + DENALI_CTL_53_DATA + DENALI_CTL_54_DATA + DENALI_CTL_55_DATA + DENALI_CTL_56_DATA + DENALI_CTL_57_DATA + DENALI_CTL_58_DATA + DENALI_CTL_59_DATA + + DENALI_CTL_60_DATA + DENALI_CTL_61_DATA + DENALI_CTL_62_DATA + DENALI_CTL_63_DATA + DENALI_CTL_64_DATA + DENALI_CTL_65_DATA + DENALI_CTL_66_DATA + DENALI_CTL_67_DATA + DENALI_CTL_68_DATA + DENALI_CTL_69_DATA + + DENALI_CTL_70_DATA + DENALI_CTL_71_DATA + DENALI_CTL_72_DATA + DENALI_CTL_73_DATA + DENALI_CTL_74_DATA + DENALI_CTL_75_DATA + DENALI_CTL_76_DATA + DENALI_CTL_77_DATA + DENALI_CTL_78_DATA + DENALI_CTL_79_DATA + + DENALI_CTL_80_DATA + DENALI_CTL_81_DATA + DENALI_CTL_82_DATA + DENALI_CTL_83_DATA + DENALI_CTL_84_DATA + DENALI_CTL_85_DATA + DENALI_CTL_86_DATA + DENALI_CTL_87_DATA + DENALI_CTL_88_DATA + DENALI_CTL_89_DATA + + DENALI_CTL_90_DATA + DENALI_CTL_91_DATA + DENALI_CTL_92_DATA + >; + + cadence,ctl-350 = < + DENALI_CTL_350_DATA + DENALI_CTL_351_DATA + DENALI_CTL_352_DATA + DENALI_CTL_353_DATA + DENALI_CTL_354_DATA + DENALI_CTL_355_DATA + DENALI_CTL_356_DATA + DENALI_CTL_357_DATA + DENALI_CTL_358_DATA + DENALI_CTL_359_DATA + + DENALI_CTL_360_DATA + DENALI_CTL_361_DATA + DENALI_CTL_362_DATA + DENALI_CTL_363_DATA + DENALI_CTL_364_DATA + DENALI_CTL_365_DATA + DENALI_CTL_366_DATA + DENALI_CTL_367_DATA + DENALI_CTL_368_DATA + DENALI_CTL_369_DATA + + DENALI_CTL_370_DATA + DENALI_CTL_371_DATA + DENALI_CTL_372_DATA + DENALI_CTL_373_DATA + DENALI_CTL_374_DATA + >; + +#undef DENALI_CTL_00_DATA +#undef DENALI_CTL_01_DATA +#undef DENALI_CTL_02_DATA +#undef DENALI_CTL_03_DATA +#undef DENALI_CTL_04_DATA +#undef DENALI_CTL_05_DATA +#undef DENALI_CTL_06_DATA +#undef DENALI_CTL_07_DATA +#undef DENALI_CTL_08_DATA +#undef DENALI_CTL_09_DATA +#undef DENALI_CTL_10_DATA +#undef DENALI_CTL_11_DATA +#undef DENALI_CTL_12_DATA +#undef DENALI_CTL_13_DATA +#undef DENALI_CTL_14_DATA +#undef DENALI_CTL_15_DATA +#undef DENALI_CTL_16_DATA +#undef DENALI_CTL_17_DATA +#undef DENALI_CTL_18_DATA +#undef DENALI_CTL_19_DATA +#undef DENALI_CTL_20_DATA +#undef DENALI_CTL_21_DATA +#undef DENALI_CTL_22_DATA +#undef DENALI_CTL_23_DATA +#undef DENALI_CTL_24_DATA +#undef DENALI_CTL_25_DATA +#undef DENALI_CTL_26_DATA +#undef DENALI_CTL_27_DATA +#undef DENALI_CTL_28_DATA +#undef DENALI_CTL_29_DATA +#undef DENALI_CTL_30_DATA +#undef DENALI_CTL_31_DATA +#undef DENALI_CTL_32_DATA +#undef DENALI_CTL_33_DATA +#undef DENALI_CTL_34_DATA +#undef DENALI_CTL_35_DATA +#undef DENALI_CTL_36_DATA +#undef DENALI_CTL_37_DATA +#undef DENALI_CTL_38_DATA +#undef DENALI_CTL_39_DATA +#undef DENALI_CTL_40_DATA +#undef DENALI_CTL_41_DATA +#undef DENALI_CTL_42_DATA +#undef DENALI_CTL_43_DATA +#undef DENALI_CTL_44_DATA +#undef DENALI_CTL_45_DATA +#undef DENALI_CTL_46_DATA +#undef DENALI_CTL_47_DATA +#undef DENALI_CTL_48_DATA +#undef DENALI_CTL_49_DATA +#undef DENALI_CTL_50_DATA +#undef DENALI_CTL_51_DATA +#undef DENALI_CTL_52_DATA +#undef DENALI_CTL_53_DATA +#undef DENALI_CTL_54_DATA +#undef DENALI_CTL_55_DATA +#undef DENALI_CTL_56_DATA +#undef DENALI_CTL_57_DATA +#undef DENALI_CTL_58_DATA +#undef DENALI_CTL_59_DATA +#undef DENALI_CTL_60_DATA +#undef DENALI_CTL_61_DATA +#undef DENALI_CTL_62_DATA +#undef DENALI_CTL_63_DATA +#undef DENALI_CTL_64_DATA +#undef DENALI_CTL_65_DATA +#undef DENALI_CTL_66_DATA +#undef DENALI_CTL_67_DATA +#undef DENALI_CTL_68_DATA +#undef DENALI_CTL_69_DATA +#undef DENALI_CTL_70_DATA +#undef DENALI_CTL_71_DATA +#undef DENALI_CTL_72_DATA +#undef DENALI_CTL_73_DATA +#undef DENALI_CTL_74_DATA +#undef DENALI_CTL_75_DATA +#undef DENALI_CTL_76_DATA +#undef DENALI_CTL_77_DATA +#undef DENALI_CTL_78_DATA +#undef DENALI_CTL_79_DATA +#undef DENALI_CTL_80_DATA +#undef DENALI_CTL_81_DATA +#undef DENALI_CTL_82_DATA +#undef DENALI_CTL_83_DATA +#undef DENALI_CTL_84_DATA +#undef DENALI_CTL_85_DATA +#undef DENALI_CTL_86_DATA +#undef DENALI_CTL_87_DATA +#undef DENALI_CTL_88_DATA +#undef DENALI_CTL_89_DATA +#undef DENALI_CTL_90_DATA +#undef DENALI_CTL_91_DATA +#undef DENALI_CTL_92_DATA +#undef DENALI_CTL_93_DATA +#undef DENALI_CTL_94_DATA +#undef DENALI_CTL_95_DATA +#undef DENALI_CTL_96_DATA +#undef DENALI_CTL_97_DATA +#undef DENALI_CTL_98_DATA +#undef DENALI_CTL_99_DATA +#undef DENALI_CTL_100_DATA +#undef DENALI_CTL_101_DATA +#undef DENALI_CTL_102_DATA +#undef DENALI_CTL_103_DATA +#undef DENALI_CTL_104_DATA +#undef DENALI_CTL_105_DATA +#undef DENALI_CTL_106_DATA +#undef DENALI_CTL_107_DATA +#undef DENALI_CTL_108_DATA +#undef DENALI_CTL_109_DATA +#undef DENALI_CTL_110_DATA +#undef DENALI_CTL_111_DATA +#undef DENALI_CTL_112_DATA +#undef DENALI_CTL_113_DATA +#undef DENALI_CTL_114_DATA +#undef DENALI_CTL_115_DATA +#undef DENALI_CTL_116_DATA +#undef DENALI_CTL_117_DATA +#undef DENALI_CTL_118_DATA +#undef DENALI_CTL_119_DATA +#undef DENALI_CTL_120_DATA +#undef DENALI_CTL_121_DATA +#undef DENALI_CTL_122_DATA +#undef DENALI_CTL_123_DATA +#undef DENALI_CTL_124_DATA +#undef DENALI_CTL_125_DATA +#undef DENALI_CTL_126_DATA +#undef DENALI_CTL_127_DATA +#undef DENALI_CTL_128_DATA +#undef DENALI_CTL_129_DATA +#undef DENALI_CTL_130_DATA +#undef DENALI_CTL_131_DATA +#undef DENALI_CTL_132_DATA +#undef DENALI_CTL_133_DATA +#undef DENALI_CTL_134_DATA +#undef DENALI_CTL_135_DATA +#undef DENALI_CTL_136_DATA +#undef DENALI_CTL_137_DATA +#undef DENALI_CTL_138_DATA +#undef DENALI_CTL_139_DATA +#undef DENALI_CTL_140_DATA +#undef DENALI_CTL_141_DATA +#undef DENALI_CTL_142_DATA +#undef DENALI_CTL_143_DATA +#undef DENALI_CTL_144_DATA +#undef DENALI_CTL_145_DATA +#undef DENALI_CTL_146_DATA +#undef DENALI_CTL_147_DATA +#undef DENALI_CTL_148_DATA +#undef DENALI_CTL_149_DATA +#undef DENALI_CTL_150_DATA +#undef DENALI_CTL_151_DATA +#undef DENALI_CTL_152_DATA +#undef DENALI_CTL_153_DATA +#undef DENALI_CTL_154_DATA +#undef DENALI_CTL_155_DATA +#undef DENALI_CTL_156_DATA +#undef DENALI_CTL_157_DATA +#undef DENALI_CTL_158_DATA +#undef DENALI_CTL_159_DATA +#undef DENALI_CTL_160_DATA +#undef DENALI_CTL_161_DATA +#undef DENALI_CTL_162_DATA +#undef DENALI_CTL_163_DATA +#undef DENALI_CTL_164_DATA +#undef DENALI_CTL_165_DATA +#undef DENALI_CTL_166_DATA +#undef DENALI_CTL_167_DATA +#undef DENALI_CTL_168_DATA +#undef DENALI_CTL_169_DATA +#undef DENALI_CTL_170_DATA +#undef DENALI_CTL_171_DATA +#undef DENALI_CTL_172_DATA +#undef DENALI_CTL_173_DATA +#undef DENALI_CTL_174_DATA +#undef DENALI_CTL_175_DATA +#undef DENALI_CTL_176_DATA +#undef DENALI_CTL_177_DATA +#undef DENALI_CTL_178_DATA +#undef DENALI_CTL_179_DATA +#undef DENALI_CTL_180_DATA +#undef DENALI_CTL_181_DATA +#undef DENALI_CTL_182_DATA +#undef DENALI_CTL_183_DATA +#undef DENALI_CTL_184_DATA +#undef DENALI_CTL_185_DATA +#undef DENALI_CTL_186_DATA +#undef DENALI_CTL_187_DATA +#undef DENALI_CTL_188_DATA +#undef DENALI_CTL_189_DATA +#undef DENALI_CTL_190_DATA +#undef DENALI_CTL_191_DATA +#undef DENALI_CTL_192_DATA +#undef DENALI_CTL_193_DATA +#undef DENALI_CTL_194_DATA +#undef DENALI_CTL_195_DATA +#undef DENALI_CTL_196_DATA +#undef DENALI_CTL_197_DATA +#undef DENALI_CTL_198_DATA +#undef DENALI_CTL_199_DATA +#undef DENALI_CTL_200_DATA +#undef DENALI_CTL_201_DATA +#undef DENALI_CTL_202_DATA +#undef DENALI_CTL_203_DATA +#undef DENALI_CTL_204_DATA +#undef DENALI_CTL_205_DATA +#undef DENALI_CTL_206_DATA +#undef DENALI_CTL_207_DATA +#undef DENALI_CTL_208_DATA +#undef DENALI_CTL_209_DATA +#undef DENALI_CTL_210_DATA +#undef DENALI_CTL_211_DATA +#undef DENALI_CTL_212_DATA +#undef DENALI_CTL_213_DATA +#undef DENALI_CTL_214_DATA +#undef DENALI_CTL_215_DATA +#undef DENALI_CTL_216_DATA +#undef DENALI_CTL_217_DATA +#undef DENALI_CTL_218_DATA +#undef DENALI_CTL_219_DATA +#undef DENALI_CTL_220_DATA +#undef DENALI_CTL_221_DATA +#undef DENALI_CTL_222_DATA +#undef DENALI_CTL_223_DATA +#undef DENALI_CTL_224_DATA +#undef DENALI_CTL_225_DATA +#undef DENALI_CTL_226_DATA +#undef DENALI_CTL_227_DATA +#undef DENALI_CTL_228_DATA +#undef DENALI_CTL_229_DATA +#undef DENALI_CTL_230_DATA +#undef DENALI_CTL_231_DATA +#undef DENALI_CTL_232_DATA +#undef DENALI_CTL_233_DATA +#undef DENALI_CTL_234_DATA +#undef DENALI_CTL_235_DATA +#undef DENALI_CTL_236_DATA +#undef DENALI_CTL_237_DATA +#undef DENALI_CTL_238_DATA +#undef DENALI_CTL_239_DATA +#undef DENALI_CTL_240_DATA +#undef DENALI_CTL_241_DATA +#undef DENALI_CTL_242_DATA +#undef DENALI_CTL_243_DATA +#undef DENALI_CTL_244_DATA +#undef DENALI_CTL_245_DATA +#undef DENALI_CTL_246_DATA +#undef DENALI_CTL_247_DATA +#undef DENALI_CTL_248_DATA +#undef DENALI_CTL_249_DATA +#undef DENALI_CTL_250_DATA +#undef DENALI_CTL_251_DATA +#undef DENALI_CTL_252_DATA +#undef DENALI_CTL_253_DATA +#undef DENALI_CTL_254_DATA +#undef DENALI_CTL_255_DATA +#undef DENALI_CTL_256_DATA +#undef DENALI_CTL_257_DATA +#undef DENALI_CTL_258_DATA +#undef DENALI_CTL_259_DATA +#undef DENALI_CTL_260_DATA +#undef DENALI_CTL_261_DATA +#undef DENALI_CTL_262_DATA +#undef DENALI_CTL_263_DATA +#undef DENALI_CTL_264_DATA +#undef DENALI_CTL_265_DATA +#undef DENALI_CTL_266_DATA +#undef DENALI_CTL_267_DATA +#undef DENALI_CTL_268_DATA +#undef DENALI_CTL_269_DATA +#undef DENALI_CTL_270_DATA +#undef DENALI_CTL_271_DATA +#undef DENALI_CTL_272_DATA +#undef DENALI_CTL_273_DATA +#undef DENALI_CTL_274_DATA +#undef DENALI_CTL_275_DATA +#undef DENALI_CTL_276_DATA +#undef DENALI_CTL_277_DATA +#undef DENALI_CTL_278_DATA +#undef DENALI_CTL_279_DATA +#undef DENALI_CTL_280_DATA +#undef DENALI_CTL_281_DATA +#undef DENALI_CTL_282_DATA +#undef DENALI_CTL_283_DATA +#undef DENALI_CTL_284_DATA +#undef DENALI_CTL_285_DATA +#undef DENALI_CTL_286_DATA +#undef DENALI_CTL_287_DATA +#undef DENALI_CTL_288_DATA +#undef DENALI_CTL_289_DATA +#undef DENALI_CTL_290_DATA +#undef DENALI_CTL_291_DATA +#undef DENALI_CTL_292_DATA +#undef DENALI_CTL_293_DATA +#undef DENALI_CTL_294_DATA +#undef DENALI_CTL_295_DATA +#undef DENALI_CTL_296_DATA +#undef DENALI_CTL_297_DATA +#undef DENALI_CTL_298_DATA +#undef DENALI_CTL_299_DATA +#undef DENALI_CTL_300_DATA +#undef DENALI_CTL_301_DATA +#undef DENALI_CTL_302_DATA +#undef DENALI_CTL_303_DATA +#undef DENALI_CTL_304_DATA +#undef DENALI_CTL_305_DATA +#undef DENALI_CTL_306_DATA +#undef DENALI_CTL_307_DATA +#undef DENALI_CTL_308_DATA +#undef DENALI_CTL_309_DATA +#undef DENALI_CTL_310_DATA +#undef DENALI_CTL_311_DATA +#undef DENALI_CTL_312_DATA +#undef DENALI_CTL_313_DATA +#undef DENALI_CTL_314_DATA +#undef DENALI_CTL_315_DATA +#undef DENALI_CTL_316_DATA +#undef DENALI_CTL_317_DATA +#undef DENALI_CTL_318_DATA +#undef DENALI_CTL_319_DATA +#undef DENALI_CTL_320_DATA +#undef DENALI_CTL_321_DATA +#undef DENALI_CTL_322_DATA +#undef DENALI_CTL_323_DATA +#undef DENALI_CTL_324_DATA +#undef DENALI_CTL_325_DATA +#undef DENALI_CTL_326_DATA +#undef DENALI_CTL_327_DATA +#undef DENALI_CTL_328_DATA +#undef DENALI_CTL_329_DATA +#undef DENALI_CTL_330_DATA +#undef DENALI_CTL_331_DATA +#undef DENALI_CTL_332_DATA +#undef DENALI_CTL_333_DATA +#undef DENALI_CTL_334_DATA +#undef DENALI_CTL_335_DATA +#undef DENALI_CTL_336_DATA +#undef DENALI_CTL_337_DATA +#undef DENALI_CTL_338_DATA +#undef DENALI_CTL_339_DATA +#undef DENALI_CTL_340_DATA +#undef DENALI_CTL_341_DATA +#undef DENALI_CTL_342_DATA +#undef DENALI_CTL_343_DATA +#undef DENALI_CTL_344_DATA +#undef DENALI_CTL_345_DATA +#undef DENALI_CTL_346_DATA +#undef DENALI_CTL_347_DATA +#undef DENALI_CTL_348_DATA +#undef DENALI_CTL_349_DATA +#undef DENALI_CTL_350_DATA +#undef DENALI_CTL_351_DATA +#undef DENALI_CTL_352_DATA +#undef DENALI_CTL_353_DATA +#undef DENALI_CTL_354_DATA +#undef DENALI_CTL_355_DATA +#undef DENALI_CTL_356_DATA +#undef DENALI_CTL_357_DATA +#undef DENALI_CTL_358_DATA +#undef DENALI_CTL_359_DATA +#undef DENALI_CTL_360_DATA +#undef DENALI_CTL_361_DATA +#undef DENALI_CTL_362_DATA +#undef DENALI_CTL_363_DATA +#undef DENALI_CTL_364_DATA +#undef DENALI_CTL_365_DATA +#undef DENALI_CTL_366_DATA +#undef DENALI_CTL_367_DATA +#undef DENALI_CTL_368_DATA +#undef DENALI_CTL_369_DATA +#undef DENALI_CTL_370_DATA +#undef DENALI_CTL_371_DATA +#undef DENALI_CTL_372_DATA +#undef DENALI_CTL_373_DATA +#undef DENALI_CTL_374_DATA diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi new file mode 100644 index 0000000000..794e711103 --- /dev/null +++ b/arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Configuration file for binman + * + * After building u-boot, can generate the SPKG output by running: + * tools/binman/binman build -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -O <outdir> + */ + +#include <config.h> + +/ { + binman: binman { + }; +}; + +&binman { + mkimage { + filename = "u-boot.bin.spkg"; + args = "-n board/schneider/rzn1-snarc/spkgimage.cfg -T spkgimage -a 0x20040000 -e 0x20040000"; + u-boot { + }; + }; +}; diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts b/arch/arm/dts/r9a06g032-rzn1-snarc.dts new file mode 100644 index 0000000000..7de8ee15ef --- /dev/null +++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Schneider RZ/N1 Board + * + * Based on r9a06g032-rzn1d400-db.dts + */ + +/dts-v1/; + +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> +#include "r9a06g032.dtsi" + +/ { + model = "Schneider RZ/N1 Board"; + compatible = "schneider,rzn1", "renesas,r9a06g032"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + soc { + plat_regs: syscon@4000c000 { + compatible = "syscon"; + reg = <0x4000c000 0x1000>; + }; + + system-controller@4000c000 { + regmap = <&plat_regs>; + }; + + ddrctrl: memory-controller@4000d000 { + compatible = "cadence,ddr-ctrl"; + reg = <0x4000d000 0x1000>, <0x4000e000 0x100>; + reg-names = "ddrc", "phy"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_CLK_DDRC>, <&sysctrl R9A06G032_HCLK_DDRC>; + clock-names = "clk_ddrc", "hclk_ddrc"; + syscon = <&plat_regs>; + status = "disabled"; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&plat_regs>; + offset = <0x198>; /* sysctrl.RSTEN */ + mask = <0x40>; /* bit 6 = SWRST_REQ */ + value = <0x40>; + }; +}; + +&ddrctrl { + status = "okay"; + + conf-1 { + size = <0x40000000>; /* 1 GB */ + #include "renesas/is43tr16256a_125k_CTL.h" + #include "r9a06g032-ddr.dtsi" + }; + conf-2 { + size = <0x10000000>; /* 256 MB */ + #include "renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h" + #include "r9a06g032-ddr.dtsi" + }; +}; + +&pinctrl { + status = "okay"; + + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + bias-disable; + }; +}; + +&uart0 { + pinctrl-0 = <&pins_uart0>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi new file mode 100644 index 0000000000..0fa565a1c3 --- /dev/null +++ b/arch/arm/dts/r9a06g032.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r9a06g032-sysctrl.h> + +/ { + compatible = "renesas,r9a06g032"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clocks = <&sysctrl R9A06G032_CLK_A7MP>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clocks = <&sysctrl R9A06G032_CLK_A7MP>; + enable-method = "renesas,r9a06g032-smp"; + cpu-release-addr = <0 0x4000c204>; + }; + }; + + ext_jtag_clk: extjtagclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_mclk: extmclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + + ext_rgmii_ref: extrgmiiref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + ext_rtc_clk: extrtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + rtc0: rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + wdt0: watchdog@40008000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + wdt1: watchdog@40009000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40009000 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + sysctrl: system-controller@4000c000 { + compatible = "renesas,r9a06g032-sysctrl"; + reg = <0x4000c000 0x1000>; + status = "okay"; + #clock-cells = <1>; + #power-domain-cells = <0>; + + clocks = <&ext_mclk>, <&ext_rtc_clk>, + <&ext_jtag_clk>, <&ext_rgmii_ref>; + clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; + #address-cells = <1>; + #size-cells = <1>; + + dmamux: dma-router@a0 { + compatible = "renesas,rzn1-dmamux"; + reg = <0xa0 4>; + #dma-cells = <6>; + dma-requests = <32>; + dma-masters = <&dma0 &dma1>; + }; + }; + + udc: usb@4001e000 { + compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; + reg = <0x4001e000 0x2000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_USBF>, + <&sysctrl R9A06G032_HCLK_USBPM>; + clock-names = "hclkf", "hclkpm"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + pci_usb: pci@40030000 { + compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; + device_type = "pci"; + clocks = <&sysctrl R9A06G032_HCLK_USBH>, + <&sysctrl R9A06G032_HCLK_USBPM>, + <&sysctrl R9A06G032_CLK_PCI_USB>; + clock-names = "hclkh", "hclkpm", "pciclk"; + power-domains = <&sysctrl>; + reg = <0x40030000 0xc00>, + <0x40020000 0x1100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; + /* Should map all possible DDR as inbound ranges, but + * the IP only supports a 256MB, 512MB, or 1GB window. + * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) + */ + dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usbphy>; + phy-names = "usb"; + }; + }; + + uart0: serial@40060000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40060000 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@40061000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40061000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@40062000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; + reg = <0x40062000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@50000000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50000000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@50001000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50001000 0x400>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@50002000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50002000 0x400>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart6: serial@50003000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50003000 0x400>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart7: serial@50004000 { + compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; + reg = <0x50004000 0x400>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + pinctrl: pinctrl@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + status = "okay"; + }; + + nand_controller: nand-controller@40102000 { + compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; + reg = <0x40102000 0x2000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; + clock-names = "hclk", "eclk"; + power-domains = <&sysctrl>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dma0: dma-controller@40104000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40104000 0x1000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA0>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + dma1: dma-controller@40105000 { + compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; + reg = <0x40105000 0x1000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&sysctrl R9A06G032_HCLK_DMA1>; + dma-channels = <8>; + dma-requests = <16>; + dma-masters = <1>; + #dma-cells = <3>; + block_size = <0xfff>; + data-width = <8>; + }; + + gmac2: ethernet@44002000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + + eth_miic: eth-miic@44030000 { + compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44030000 0x10000>; + clocks = <&sysctrl R9A06G032_CLK_MII_REF>, + <&sysctrl R9A06G032_CLK_RGMII_REF>, + <&sysctrl R9A06G032_CLK_RMII_REF>, + <&sysctrl R9A06G032_HCLK_SWITCH_RG>; + clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; + power-domains = <&sysctrl>; + status = "disabled"; + + mii_conv1: mii-conv@1 { + reg = <1>; + status = "disabled"; + }; + + mii_conv2: mii-conv@2 { + reg = <2>; + status = "disabled"; + }; + + mii_conv3: mii-conv@3 { + reg = <3>; + status = "disabled"; + }; + + mii_conv4: mii-conv@4 { + reg = <4>; + status = "disabled"; + }; + + mii_conv5: mii-conv@5 { + reg = <5>; + status = "disabled"; + }; + }; + + switch: switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, + <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + power-domains = <&sysctrl>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0>; + pcs-handle = <&mii_conv5>; + status = "disabled"; + }; + + switch_port1: port@1 { + reg = <1>; + pcs-handle = <&mii_conv4>; + status = "disabled"; + }; + + switch_port2: port@2 { + reg = <2>; + pcs-handle = <&mii_conv3>; + status = "disabled"; + }; + + switch_port3: port@3 { + reg = <3>; + pcs-handle = <&mii_conv2>; + status = "disabled"; + }; + + switch_port4: port@4 { + reg = <4>; + ethernet = <&gmac2>; + label = "cpu"; + phy-mode = "internal"; + status = "disabled"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gic: interrupt-controller@44101000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x44101000 0x1000>, /* Distributer */ + <0x44102000 0x2000>, /* CPU interface */ + <0x44104000 0x2000>, /* Virt interface control */ + <0x44106000 0x2000>; /* Virt CPU interface */ + interrupts = + <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + can0: can@52104000 { + compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + + can1: can@52105000 { + compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; + reg = <0x52105000 0x800>; + reg-io-width = <4>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_CAN1>; + power-domains = <&sysctrl>; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + arm,cpu-registers-not-fw-configured; + always-on; + interrupts = + <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + usbphy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts index cbf52c88b9..cfe0710229 100644 --- a/arch/arm/dts/zynq-dlc20-rev1.0.dts +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -26,7 +26,7 @@ }; chosen { - bootargs = "earlyprintk"; + bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 875ee080df..5f280f4d8e 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -8,7 +8,7 @@ #include "zynq-7000.dtsi" / { - model = "Zynq MicroZED Board"; + model = "Avnet MicroZed board"; compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { @@ -19,11 +19,11 @@ memory@0 { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; chosen { - bootargs = "earlyprintk"; + bootargs = "earlycon"; stdout-path = "serial0:115200n8"; }; @@ -42,11 +42,6 @@ status = "okay"; }; -&uart1 { - bootph-all; - status = "okay"; -}; - &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -62,8 +57,41 @@ status = "okay"; }; +&uart1 { + bootph-all; + status = "okay"; +}; + &usb0 { status = "okay"; dr_mode = "host"; usb-phy = <&usb_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; +}; + +&pinctrl0 { + pinctrl_usb0_default: usb0-default { + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + + conf { + groups = "usb0_0_grp"; + slew-rate = <0>; + io-standard = <1>; + }; + + conf-rx { + pins = "MIO29", "MIO31", "MIO36"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", + "MIO35", "MIO37", "MIO38", "MIO39"; + bias-disable; + }; + }; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index ed75049741..f6ed047f3d 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -224,7 +224,7 @@ }; partition@22A0000 { label = "User"; - reg = <0x22A0000 0x1db0000>; /* 29.5 MB */ + reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 1ef7d68bdf..3061ccd34c 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -48,6 +48,24 @@ config RZA1 prompt "Renesas ARM SoCs RZ/A1 (32bit)" select CPU_V7A +config RZN1 + prompt "Renesas ARM SoCs RZ/N1 (32bit)" + select CPU_V7A + select ARMV7_SET_CORTEX_SMPEN if !SPL + select SPL_ARMV7_SET_CORTEX_SMPEN if SPL + select CLK + select CLK_RENESAS + select CLK_R9A06G032 + select DM + select DM_ETH + select DM_SERIAL + select PINCTRL + select PINCONF + select REGMAP + select SYSRESET + select SYSRESET_SYSCON + imply CMD_DM + endchoice config SYS_SOC @@ -56,5 +74,6 @@ config SYS_SOC source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.rza1" +source "arch/arm/mach-rmobile/Kconfig.rzn1" endif diff --git a/arch/arm/mach-rmobile/Kconfig.rzn1 b/arch/arm/mach-rmobile/Kconfig.rzn1 new file mode 100644 index 0000000000..73138d69f9 --- /dev/null +++ b/arch/arm/mach-rmobile/Kconfig.rzn1 @@ -0,0 +1,20 @@ +if RZN1 + +choice + prompt "Renesas RZ/N1 Board select" + default TARGET_SCHNEIDER_RZN1 + +config TARGET_SCHNEIDER_RZN1 + bool "Schneider RZN1 board" + help + Support the Schneider RZN1D and RZN1S boards, which are based + on the Renesas RZ/N1 SoC. + +endchoice + +config SYS_SOC + default "rzn1" + +source "board/schneider/rzn1-snarc/Kconfig" + +endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 7e7465a2c8..71a856ea87 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -30,7 +30,7 @@ void enable_caches(void) #endif #ifdef CONFIG_DISPLAY_CPUINFO -#ifndef CONFIG_RZA1 +#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1) __weak const u8 *rzg_get_cpu_name(void) { return 0; @@ -126,11 +126,17 @@ int print_cpuinfo(void) return 0; } -#else +#elif defined(CONFIG_RZA1) int print_cpuinfo(void) { printf("CPU: Renesas Electronics RZ/A1\n"); return 0; } +#else /* CONFIG_RZN1 */ +int print_cpuinfo(void) +{ + printf("CPU: Renesas Electronics RZ/N1\n"); + return 0; +} #endif #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 2891878973..7a12f4b2b6 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -32,7 +32,8 @@ #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 -#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 +#define ZYNQMP_R5_0_TCM_START_ADDR 0xFFE00000 +#define ZYNQMP_R5_1_TCM_START_ADDR 0xFFE90000 #define ZYNQMP_TCM_BOTH_SIZE 0x40000 #define ZYNQMP_CORE_APU0 0 @@ -215,9 +216,14 @@ static void set_r5_start(u8 high) writel(tmp, &rpu_base->rpu1_cfg); } -static void write_tcm_boot_trampoline(u32 boot_addr) +static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr) { if (boot_addr) { + u64 tcm_start_addr = ZYNQMP_R5_0_TCM_START_ADDR; + + if (nr == ZYNQMP_CORE_RPU1) + tcm_start_addr = ZYNQMP_R5_1_TCM_START_ADDR; + /* * Boot trampoline is simple ASM code below. * @@ -229,12 +235,12 @@ static void write_tcm_boot_trampoline(u32 boot_addr) * bx r1 */ debug("Write boot trampoline for %x\n", boot_addr); - writel(0xea000000, ZYNQMP_TCM_START_ADDRESS); - writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4); - writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8); - writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc); - writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10); - writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for + writel(0xea000000, tcm_start_addr); + writel(boot_addr, tcm_start_addr + 0x4); + writel(0xe59f0004, tcm_start_addr + 0x8); + writel(0xe5901000, tcm_start_addr + 0xc); + writel(0xe12fff11, tcm_start_addr + 0x10); + writel(0x00000004, tcm_start_addr + 0x14); } } @@ -247,8 +253,10 @@ void initialize_tcm(bool mode) release_r5_reset(ZYNQMP_CORE_RPU0, LOCK); } else { set_r5_tcm_mode(SPLIT); + set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, SPLIT); set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT); enable_clock_r5(); + release_r5_reset(ZYNQMP_CORE_RPU0, SPLIT); release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT); } } @@ -326,7 +334,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) enable_clock_r5(); release_r5_reset(nr, LOCK); dcache_disable(); - write_tcm_boot_trampoline(boot_addr_uniq); + write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, LOCK); mark_r5_used(nr, LOCK); @@ -339,7 +347,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) enable_clock_r5(); release_r5_reset(nr, SPLIT); dcache_disable(); - write_tcm_boot_trampoline(boot_addr_uniq); + write_tcm_boot_trampoline(nr, boot_addr_uniq); dcache_enable(); set_r5_halt_mode(nr, RELEASE, SPLIT); mark_r5_used(nr, SPLIT); diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 453e53db71..ff9f9222e6 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -86,8 +86,8 @@ filename-prefixes = "/", "/boot/"; bootdev-order = "mmc2", "mmc1"; - syslinux { - compatible = "u-boot,distro-syslinux"; + extlinux { + compatible = "u-boot,extlinux"; }; efi { @@ -344,7 +344,7 @@ vsync-len = <13>; }; }; - panel-timings { + panel-timing { clock-frequency = <6500000>; hactive = <240>; vactive = <320>; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 16ce5cb892..663d7ca991 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -223,7 +223,7 @@ int board_late_init(void) char mmcbootdev_str[16]; ret = uclass_first_device_err(UCLASS_CROS_EC, &dev); - if (ret && ret != -ENODEV) { + if (ret && ret != -ENODEV && ret != -EPFNOSUPPORT) { /* Force console on */ gd->flags &= ~GD_FLG_SILENT; diff --git a/board/schneider/rzn1-snarc/Kconfig b/board/schneider/rzn1-snarc/Kconfig new file mode 100644 index 0000000000..1c1c235f00 --- /dev/null +++ b/board/schneider/rzn1-snarc/Kconfig @@ -0,0 +1,18 @@ +if TARGET_SCHNEIDER_RZN1 + +config TEXT_BASE + default 0x20040000 + +config SYS_MONITOR_LEN + default 524288 + +config SYS_BOARD + default "rzn1-snarc" + +config SYS_VENDOR + default "schneider" + +config SYS_CONFIG_NAME + default "rzn1-snarc" + +endif diff --git a/board/schneider/rzn1-snarc/Makefile b/board/schneider/rzn1-snarc/Makefile new file mode 100644 index 0000000000..e197ca8cb4 --- /dev/null +++ b/board/schneider/rzn1-snarc/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := rzn1.o diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c new file mode 100644 index 0000000000..09241c3a95 --- /dev/null +++ b/board/schneider/rzn1-snarc/rzn1.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = gd->ram_base + 0x100; + + return 0; +} + +int dram_init(void) +{ + struct udevice *dev; + int err; + + /* + * This will end up calling cadence_ddr_probe(), + * and will also update gd->ram_size. + */ + err = uclass_get_device(UCLASS_RAM, 0, &dev); + if (err) + debug("DRAM init failed: %d\n", err); + + return err; +} diff --git a/board/schneider/rzn1-snarc/spkgimage.cfg b/board/schneider/rzn1-snarc/spkgimage.cfg new file mode 100644 index 0000000000..b5faf96b00 --- /dev/null +++ b/board/schneider/rzn1-snarc/spkgimage.cfg @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Schneider Electric +# +# SPKG image header, for booting on RZ/N1 + +# b[35:32] SPKG version +VERSION 1 + +# b[42:41] ECC Block size: 0=256 bytes, 1=512 bytes, 2=1024 bytes +NAND_ECC_BLOCK_SIZE 1 + +# b[45] NAND enable (boolean) +NAND_ECC_ENABLE 1 + +# b[50:48] ECC Scheme: 0=BCH2 1=BCH4 2=BCH8 3=BCH16 4=BCH24 5=BCH32 +NAND_ECC_SCHEME 3 + +# b[63:56] ECC bytes per block +NAND_BYTES_PER_ECC_BLOCK 28 + +# Provide dummy BLp header (boolean) +ADD_DUMMY_BLP 1 + +# Pad the image to a multiple of +PADDING 64K diff --git a/boot/Kconfig b/boot/Kconfig index 8c27f52ec3..eea5ed6040 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -437,6 +437,7 @@ config BOOTSTD_DEFAULTS depends on BOOTSTD imply USE_BOOTCOMMAND select BOOT_DEFAULTS + select BOOTMETH_DISTRO help These are not required but are commonly needed to support a good selection of booting methods. Enable this to improve the capability @@ -462,30 +463,38 @@ config BOOTMETH_GLOBAL EFI bootmgr, since they take full control over which bootdevs are selected to boot. -config BOOTMETH_DISTRO - bool "Bootdev support for distro boot" +config BOOTMETH_EXTLINUX + bool "Bootdev support for extlinux boot" select PXE_UTILS default y help - Enables support for distro boot using bootdevs. This makes the + Enables support for extlinux boot using bootdevs. This makes the bootdevs look for a 'extlinux/extlinux.conf' on each filesystem they scan. + The specification for this filed is here: + + https://uapi-group.org/specifications/specs/boot_loader_specification/ + This provides a way to try out standard boot on an existing boot flow. -config BOOTMETH_DISTRO_PXE - bool "Bootdev support for distro boot over network" +config BOOTMETH_EXTLINUX_PXE + bool "Bootdev support for extlinux boot over network" depends on CMD_PXE && CMD_NET && DM_ETH default y help - Enables support for distro boot using bootdevs. This makes the + Enables support for extlinux boot using bootdevs. This makes the bootdevs look for a 'extlinux/extlinux.conf' on the tftp server. + The specification for this file is here: + + https://uapi-group.org/specifications/specs/boot_loader_specification/ + This provides a way to try out standard boot on an existing boot flow. config BOOTMETH_EFILOADER bool "Bootdev support for EFI boot" - depends on CMD_BOOTEFI + depends on EFI_LOADER default y help Enables support for EFI boot using bootdevs. This makes the @@ -515,6 +524,13 @@ config BOOTMETH_VBE supports selection of various firmware components, seleciton of an OS to boot as well as updating these using fwupd. +config BOOTMETH_DISTRO + bool # Options needed to boot any distro + select BOOTMETH_SCRIPT # E.g. Armbian uses scripts + select BOOTMETH_EXTLINUX # E.g. Debian uses these + select BOOTMETH_EXTLINUX_PXE if CMD_PXE && CMD_NET && DM_ETH + select BOOTMETH_EFILOADER if EFI_LOADER # E.g. Ubuntu uses this + config SPL_BOOTMETH_VBE bool "Bootdev support for Verified Boot for Embedded (SPL)" depends on SPL && FIT @@ -638,6 +654,7 @@ config BOOTMETH_SANDBOX config BOOTMETH_SCRIPT bool "Bootdev support for U-Boot scripts" default y if BOOTSTD_FULL + select HUSH_PARSER help Enables support for booting a distro via a U-Boot script. This makes the bootdevs look for a 'boot/boot.scr' file which can be used to @@ -1553,8 +1570,8 @@ config USE_BOOTCOMMAND config BOOTCOMMAND string "bootcmd value" depends on USE_BOOTCOMMAND && !USE_DEFAULT_ENV_FILE - default "bootflow scan -lb" if BOOTSTD_BOOTCOMMAND && CMD_BOOTFLOW_FULL - default "bootflow scan" if BOOTSTD_BOOTCOMMAND && !CMD_BOOTFLOW_FULL + default "bootflow scan -lb" if BOOTSTD_DEFAULTS && CMD_BOOTFLOW_FULL + default "bootflow scan" if BOOTSTD_DEFAULTS && !CMD_BOOTFLOW_FULL default "run distro_bootcmd" if !BOOTSTD_BOOTCOMMAND && DISTRO_DEFAULTS help This is the string of commands that will be used as bootcmd and if diff --git a/boot/Makefile b/boot/Makefile index 88193a1b60..f94c31d922 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -24,8 +24,8 @@ obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootflow.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootmeth-uclass.o obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += bootstd-uclass.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_DISTRO) += bootmeth_distro.o -obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_DISTRO_PXE) += bootmeth_pxe.o +obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX) += bootmeth_extlinux.o +obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EXTLINUX_PXE) += bootmeth_pxe.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_EFILOADER) += bootmeth_efi.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SANDBOX) += bootmeth_sandbox.o obj-$(CONFIG_$(SPL_TPL_)BOOTMETH_SCRIPT) += bootmeth_script.o diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 57d2944647..9660ff7567 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -154,8 +154,15 @@ int bootdev_find_in_blk(struct udevice *dev, struct udevice *blk, ret = -ESHUTDOWN; else bflow->state = BOOTFLOWST_MEDIA; - if (ret) + if (ret) { + /* allow partition 1 to be missing */ + if (iter->part == 1) { + iter->max_part = 3; + ret = -ENOENT; + } + return log_msg_ret("part", ret); + } /* * Currently we don't get the number of partitions, so just diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c index 2aee1e0f0c..3b3e0614da 100644 --- a/boot/bootmeth-uclass.c +++ b/boot/bootmeth-uclass.c @@ -319,7 +319,7 @@ static int alloc_file(const char *fname, uint size, void **bufp) return log_msg_ret("read", ret); } if (size != bytes_read) - return log_msg_ret("bread", -EINVAL); + return log_msg_ret("bread", -EIO); buf[size] = '\0'; *bufp = buf; diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 6f70f2229b..af31fbfc85 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -235,7 +235,7 @@ static int distro_efi_read_bootflow_file(struct udevice *dev, ret = efiload_read_file(desc, bflow); if (ret) - return log_msg_ret("read", -EINVAL); + return log_msg_ret("read", ret); fdt_addr = env_get_hex("fdt_addr_r", 0); diff --git a/boot/bootmeth_distro.c b/boot/bootmeth_extlinux.c index b4b73ecbf5..24be076022 100644 --- a/boot/bootmeth_distro.c +++ b/boot/bootmeth_extlinux.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Bootmethod for distro boot (syslinux boot from a block device) + * Bootmethod for extlinux boot from a block device * * Copyright 2021 Google LLC * Written by Simon Glass <sjg@chromium.org> @@ -14,15 +14,15 @@ #include <bootmeth.h> #include <bootstd.h> #include <command.h> -#include <distro.h> #include <dm.h> +#include <extlinux.h> #include <fs.h> #include <malloc.h> #include <mapmem.h> #include <mmc.h> #include <pxe_utils.h> -static int distro_get_state_desc(struct udevice *dev, char *buf, int maxsize) +static int extlinux_get_state_desc(struct udevice *dev, char *buf, int maxsize) { if (IS_ENABLED(CONFIG_SANDBOX)) { int len; @@ -35,10 +35,10 @@ static int distro_get_state_desc(struct udevice *dev, char *buf, int maxsize) return 0; } -static int distro_getfile(struct pxe_context *ctx, const char *file_path, - char *file_addr, ulong *sizep) +static int extlinux_getfile(struct pxe_context *ctx, const char *file_path, + char *file_addr, ulong *sizep) { - struct distro_info *info = ctx->userdata; + struct extlinux_info *info = ctx->userdata; ulong addr; int ret; @@ -54,7 +54,7 @@ static int distro_getfile(struct pxe_context *ctx, const char *file_path, return 0; } -static int distro_check(struct udevice *dev, struct bootflow_iter *iter) +static int extlinux_check(struct udevice *dev, struct bootflow_iter *iter) { int ret; @@ -67,12 +67,12 @@ static int distro_check(struct udevice *dev, struct bootflow_iter *iter) } /** - * distro_fill_info() - Decode the extlinux file to find out distro info + * extlinux_fill_info() - Decode the extlinux file to find out its info * * @bflow: Bootflow to process * @return 0 if OK, -ve on error */ -static int distro_fill_info(struct bootflow *bflow) +static int extlinux_fill_info(struct bootflow *bflow) { struct membuff mb; char line[200]; @@ -98,7 +98,7 @@ static int distro_fill_info(struct bootflow *bflow) return 0; } -static int distro_read_bootflow(struct udevice *dev, struct bootflow *bflow) +static int extlinux_read_bootflow(struct udevice *dev, struct bootflow *bflow) { struct blk_desc *desc; const char *const *prefixes; @@ -121,7 +121,7 @@ static int distro_read_bootflow(struct udevice *dev, struct bootflow *bflow) do { prefix = prefixes ? prefixes[i] : NULL; - ret = bootmeth_try_file(bflow, desc, prefix, DISTRO_FNAME); + ret = bootmeth_try_file(bflow, desc, prefix, EXTLINUX_FNAME); } while (ret && prefixes && prefixes[++i]); if (ret) return log_msg_ret("try", ret); @@ -131,25 +131,25 @@ static int distro_read_bootflow(struct udevice *dev, struct bootflow *bflow) if (ret) return log_msg_ret("read", ret); - ret = distro_fill_info(bflow); + ret = extlinux_fill_info(bflow); if (ret) return log_msg_ret("inf", ret); return 0; } -static int distro_boot(struct udevice *dev, struct bootflow *bflow) +static int extlinux_boot(struct udevice *dev, struct bootflow *bflow) { struct cmd_tbl cmdtp = {}; /* dummy */ struct pxe_context ctx; - struct distro_info info; + struct extlinux_info info; ulong addr; int ret; addr = map_to_sysmem(bflow->buf); info.dev = dev; info.bflow = bflow; - ret = pxe_setup_ctx(&ctx, &cmdtp, distro_getfile, &info, true, + ret = pxe_setup_ctx(&ctx, &cmdtp, extlinux_getfile, &info, true, bflow->subdir, false); if (ret) return log_msg_ret("ctx", -EINVAL); @@ -161,33 +161,33 @@ static int distro_boot(struct udevice *dev, struct bootflow *bflow) return 0; } -static int distro_bootmeth_bind(struct udevice *dev) +static int extlinux_bootmeth_bind(struct udevice *dev) { struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev); plat->desc = IS_ENABLED(CONFIG_BOOTSTD_FULL) ? - "Syslinux boot from a block device" : "syslinux"; + "Extlinux boot from a block device" : "extlinux"; return 0; } -static struct bootmeth_ops distro_bootmeth_ops = { - .get_state_desc = distro_get_state_desc, - .check = distro_check, - .read_bootflow = distro_read_bootflow, +static struct bootmeth_ops extlinux_bootmeth_ops = { + .get_state_desc = extlinux_get_state_desc, + .check = extlinux_check, + .read_bootflow = extlinux_read_bootflow, .read_file = bootmeth_common_read_file, - .boot = distro_boot, + .boot = extlinux_boot, }; -static const struct udevice_id distro_bootmeth_ids[] = { - { .compatible = "u-boot,distro-syslinux" }, +static const struct udevice_id extlinux_bootmeth_ids[] = { + { .compatible = "u-boot,extlinux" }, { } }; -U_BOOT_DRIVER(bootmeth_distro) = { - .name = "bootmeth_distro", +U_BOOT_DRIVER(bootmeth_extlinux) = { + .name = "bootmeth_extlinux", .id = UCLASS_BOOTMETH, - .of_match = distro_bootmeth_ids, - .ops = &distro_bootmeth_ops, - .bind = distro_bootmeth_bind, + .of_match = extlinux_bootmeth_ids, + .ops = &extlinux_bootmeth_ops, + .bind = extlinux_bootmeth_bind, }; diff --git a/boot/bootmeth_pxe.c b/boot/bootmeth_pxe.c index 5a8af2bbd0..ce986bd260 100644 --- a/boot/bootmeth_pxe.c +++ b/boot/bootmeth_pxe.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Bootmethod for distro boot using PXE (network boot) + * Bootmethod for extlinux boot using PXE (network boot) * * Copyright 2021 Google LLC * Written by Simon Glass <sjg@chromium.org> @@ -13,8 +13,8 @@ #include <bootflow.h> #include <bootmeth.h> #include <command.h> -#include <distro.h> #include <dm.h> +#include <extlinux.h> #include <fs.h> #include <log.h> #include <malloc.h> @@ -23,10 +23,10 @@ #include <net.h> #include <pxe_utils.h> -static int distro_pxe_getfile(struct pxe_context *ctx, const char *file_path, - char *file_addr, ulong *sizep) +static int extlinux_pxe_getfile(struct pxe_context *ctx, const char *file_path, + char *file_addr, ulong *sizep) { - struct distro_info *info = ctx->userdata; + struct extlinux_info *info = ctx->userdata; ulong addr; int ret; @@ -39,7 +39,7 @@ static int distro_pxe_getfile(struct pxe_context *ctx, const char *file_path, return 0; } -static int distro_pxe_check(struct udevice *dev, struct bootflow_iter *iter) +static int extlinux_pxe_check(struct udevice *dev, struct bootflow_iter *iter) { int ret; @@ -54,7 +54,8 @@ static int distro_pxe_check(struct udevice *dev, struct bootflow_iter *iter) return 0; } -static int distro_pxe_read_bootflow(struct udevice *dev, struct bootflow *bflow) +static int extlinux_pxe_read_bootflow(struct udevice *dev, + struct bootflow *bflow) { const char *addr_str; char fname[200]; @@ -90,7 +91,7 @@ static int distro_pxe_read_bootflow(struct udevice *dev, struct bootflow *bflow) } } snprintf(fname, sizeof(fname), "%s%s", - bflow->subdir ? bflow->subdir : "", DISTRO_FNAME); + bflow->subdir ? bflow->subdir : "", EXTLINUX_FNAME); bflow->fname = strdup(fname); if (!bflow->fname) @@ -108,8 +109,9 @@ static int distro_pxe_read_bootflow(struct udevice *dev, struct bootflow *bflow) return 0; } -static int distro_pxe_read_file(struct udevice *dev, struct bootflow *bflow, - const char *file_path, ulong addr, ulong *sizep) +static int extlinux_pxe_read_file(struct udevice *dev, struct bootflow *bflow, + const char *file_path, ulong addr, + ulong *sizep) { char *tftp_argv[] = {"tftp", NULL, NULL, NULL}; struct pxe_context *ctx = dev_get_priv(dev); @@ -133,11 +135,11 @@ static int distro_pxe_read_file(struct udevice *dev, struct bootflow *bflow, return 0; } -static int distro_pxe_boot(struct udevice *dev, struct bootflow *bflow) +static int extlinux_pxe_boot(struct udevice *dev, struct bootflow *bflow) { struct pxe_context *ctx = dev_get_priv(dev); struct cmd_tbl cmdtp = {}; /* dummy */ - struct distro_info info; + struct extlinux_info info; ulong addr; int ret; @@ -145,7 +147,7 @@ static int distro_pxe_boot(struct udevice *dev, struct bootflow *bflow) info.dev = dev; info.bflow = bflow; info.cmdtp = &cmdtp; - ret = pxe_setup_ctx(ctx, &cmdtp, distro_pxe_getfile, &info, false, + ret = pxe_setup_ctx(ctx, &cmdtp, extlinux_pxe_getfile, &info, false, bflow->subdir, false); if (ret) return log_msg_ret("ctx", -EINVAL); @@ -157,7 +159,7 @@ static int distro_pxe_boot(struct udevice *dev, struct bootflow *bflow) return 0; } -static int distro_bootmeth_pxe_bind(struct udevice *dev) +static int extlinux_bootmeth_pxe_bind(struct udevice *dev) { struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev); @@ -167,23 +169,23 @@ static int distro_bootmeth_pxe_bind(struct udevice *dev) return 0; } -static struct bootmeth_ops distro_bootmeth_pxe_ops = { - .check = distro_pxe_check, - .read_bootflow = distro_pxe_read_bootflow, - .read_file = distro_pxe_read_file, - .boot = distro_pxe_boot, +static struct bootmeth_ops extlinux_bootmeth_pxe_ops = { + .check = extlinux_pxe_check, + .read_bootflow = extlinux_pxe_read_bootflow, + .read_file = extlinux_pxe_read_file, + .boot = extlinux_pxe_boot, }; -static const struct udevice_id distro_bootmeth_pxe_ids[] = { - { .compatible = "u-boot,distro-pxe" }, +static const struct udevice_id extlinux_bootmeth_pxe_ids[] = { + { .compatible = "u-boot,extlinux-pxe" }, { } }; U_BOOT_DRIVER(bootmeth_pxe) = { .name = "bootmeth_pxe", .id = UCLASS_BOOTMETH, - .of_match = distro_bootmeth_pxe_ids, - .ops = &distro_bootmeth_pxe_ops, - .bind = distro_bootmeth_pxe_bind, + .of_match = extlinux_bootmeth_pxe_ids, + .ops = &extlinux_bootmeth_pxe_ops, + .bind = extlinux_bootmeth_pxe_bind, .priv_auto = sizeof(struct pxe_context), }; diff --git a/boot/bootmeth_qfw.c b/boot/bootmeth_qfw.c index a5f95d4d0c..ecd4b082fd 100644 --- a/boot/bootmeth_qfw.c +++ b/boot/bootmeth_qfw.c @@ -89,7 +89,7 @@ static struct bootmeth_ops qfw_bootmeth_ops = { }; static const struct udevice_id qfw_bootmeth_ids[] = { - { .compatible = "u-boot,qfw-syslinux" }, + { .compatible = "u-boot,qfw-extlinux" }, { } }; diff --git a/boot/bootmeth_sandbox.c b/boot/bootmeth_sandbox.c index 13ec5e95e6..aabc57e635 100644 --- a/boot/bootmeth_sandbox.c +++ b/boot/bootmeth_sandbox.c @@ -56,7 +56,7 @@ static struct bootmeth_ops sandbox_bootmeth_ops = { }; static const struct udevice_id sandbox_bootmeth_ids[] = { - { .compatible = "u-boot,sandbox-syslinux" }, + { .compatible = "u-boot,sandbox-extlinux" }, { } }; diff --git a/boot/image.c b/boot/image.c index 958dbf8534..5c4f9b807d 100644 --- a/boot/image.c +++ b/boot/image.c @@ -181,6 +181,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" }, { IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" }, { IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", }, + { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" }, { -1, "", "", }, }; diff --git a/cmd/Kconfig b/cmd/Kconfig index 87291e2d84..365371fb51 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -258,7 +258,7 @@ config CMD_BOOTFLOW config CMD_BOOTFLOW_FULL bool "bootflow - extract subcommands" depends on BOOTSTD_FULL - default y if BOOTSTD_FULL + default y help Add the ability to list the available bootflows, select one and obtain information about it. diff --git a/cmd/bootflow.c b/cmd/bootflow.c index cfe3422698..5c61286a2a 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -55,7 +55,7 @@ static void report_bootflow_err(struct bootflow *bflow, int err) break; } - printf(", err=%d\n", err); + printf(", err=%dE\n", err); } /** @@ -125,7 +125,7 @@ static int do_bootflow_scan(struct cmd_tbl *cmdtp, int flag, int argc, dev = std->cur_bootdev; } else { if (has_args) { - printf("Flags not supported: enable CONFIG_BOOTFLOW_FULL\n"); + printf("Flags not supported: enable CONFIG_BOOTSTD_FULL\n"); return CMD_RET_USAGE; } boot = true; @@ -620,7 +620,6 @@ static int do_usb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct usb_device *udev = NULL; int i; - extern char usb_started; if (argc < 2) return CMD_RET_USAGE; diff --git a/common/usb.c b/common/usb.c index ae9253dfc0..836506dcd9 100644 --- a/common/usb.c +++ b/common/usb.c @@ -43,7 +43,7 @@ #define USB_BUFSIZ 512 static int asynch_allowed; -char usb_started; /* flag for the started/stopped USB status */ +bool usb_started; /* flag for the started/stopped USB status */ #if !CONFIG_IS_ENABLED(DM_USB) static struct usb_device usb_dev[USB_MAX_DEVICE]; diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig new file mode 100644 index 0000000000..eb52aa3c8a --- /dev/null +++ b/configs/rzn1_snarc_defconfig @@ -0,0 +1,24 @@ +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_LEN=0xb0000 +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="r9a06g032-rzn1-snarc" +CONFIG_RZN1=y +CONFIG_SYS_LOAD_ADDR=0x80008000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x8fffffff +# CONFIG_ARCH_MISC_INIT is not set +# CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_SYS_ALT_MEMTEST_BITFLIP is not set +CONFIG_CMD_CLK=y +CONFIG_OF_CONTROL=y +CONFIG_RAM=y +CONFIG_CADENCE_DDR_CTRL=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index fb8f86cd69..97904bdec0 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_SMC=y CONFIG_CMD_EXT4_WRITE=y @@ -109,6 +110,7 @@ CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y +CONFIG_DM_RNG=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y @@ -134,3 +136,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 86cfbd6f4f..a1feafc49b 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_SMC=y CONFIG_CMD_EXT4_WRITE=y @@ -98,6 +99,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y @@ -112,6 +114,7 @@ CONFIG_ZYNQ_GEM=y CONFIG_POWER_DOMAIN=y CONFIG_ZYNQMP_POWER_DOMAIN=y CONFIG_RESET_ZYNQMP=y +CONFIG_DM_RNG=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y @@ -138,3 +141,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index e1b241f843..c4bbde2206 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -91,6 +91,7 @@ CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y CONFIG_CMD_GETTIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_SMC=y @@ -171,6 +172,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y @@ -230,6 +232,9 @@ CONFIG_SPLASH_SCREEN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 120daa48ee..9ef25b1091 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -34,6 +34,7 @@ Board-specific doc openpiton/index purism/index qualcomm/index + renesas/index rockchip/index samsung/index siemens/index diff --git a/doc/board/renesas/index.rst b/doc/board/renesas/index.rst new file mode 100644 index 0000000000..fb6558ec11 --- /dev/null +++ b/doc/board/renesas/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +======= + +.. toctree:: + :maxdepth: 2 + + renesas + rzn1 diff --git a/doc/board/renesas/renesas.rst b/doc/board/renesas/renesas.rst new file mode 100644 index 0000000000..04dee8da24 --- /dev/null +++ b/doc/board/renesas/renesas.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas +======= + +About this +---------- + +This document describes the information about Renesas supported boards +and their usage steps. + +Renesas boards +-------------- + +Renesas is a SoC solutions provider for automotive and industrial applications. + +U-Boot supports several Renesas SoC families: + +* R-Car Gen2 (32-bit) + - Blanche board + - Gose board + - Koelsch board + - Lager board + - Silk board + - Porter board + - Stout board +* R-Car Gen3 (64-bit) + - Condor board + - Draak board + - Eagle board + - Ebisu board + - Salvator-X and Salvator-XS boards + - ULCB board +* R-Car Gen4 (64-bit) + - Falcon board + - Spider board + - Whitehawk board +* RZ/A1 (32-bit) + - GR-PEACH board +* RZ/G + - Beacon-rzg2 board + - Hihope-rzg2 board + - ek874 board +* RZ/N1 (32-bit) + - Schneider rzn1-snarc board diff --git a/doc/board/renesas/rzn1.rst b/doc/board/renesas/rzn1.rst new file mode 100644 index 0000000000..e6d636b89e --- /dev/null +++ b/doc/board/renesas/rzn1.rst @@ -0,0 +1,76 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Renesas RZ/N1 +============= + +Building +-------- + +This document describes how to build and flash U-Boot for the RZ/N1. + +U-Boot +^^^^^^ + +Clone the U-Boot repository and build it as follows: + +.. code-block:: bash + + git clone --depth 1 https://source.denx.de/u-boot/u-boot.git + cd u-boot + make rzn1_snarc_defconfig + make CROSS_COMPILE=arm-linux-gnu- + +This produces `u-boot` which is an ELF executable, suitable for use with `gdb` +and JTAG debugging tools. + +It also produceds `u-boot.bin` which is a raw binary. + +Binman +^^^^^^ + +The BootROM in the RZ/N1 SoC expects to find the boot image in SPKG format. +This format is documented in Chapter 7.4 of the RZ/N1 User Manual. + +The `binman` tool may be used to generate the SPKG format for booting. +See tools/binman/binman.rst for details on this tool and its pre-requisites. + +.. code-block:: bash + + binman -d arch/arm/dts/r9a06g032-rzn1-snarc.dtb -o <OUT> + +This will produce `u-boot.bin.spkg` in the specified <OUT> directory. It can +then be flashed into QSPI, NAND, or loaded via USB-DFU mode. + +SPKG image +^^^^^^^^^^ + +Alternatively, the same SPKG image can be built by calling `mkimage` as follows: + +.. code-block:: bash + + tools/mkimage -n board/schneider/rzn1-snarc/spkgimage.cfg \ + -T spkgimage -a 0x20040000 -e 0x20040000 \ + -d u-boot.bin u-boot.bin.spkg + +This produces `u-boot.bin.spkg` which can be flashed into QSPI, NAND, or loaded +via USB-DFU mode. + +Take note of the load and execution address, which are encoded into the SPKG +headers. For development convenience, mkimage computes the execution offset +(part of the SPKG header) by subtracting the supplied load address from the +supplied execution address. + +Also note there are other parameters, notably ECC configuration in the case of +boot from NAND, specified in the `spkgimage.cfg` configuration file. + +Flashing +-------- + +The RZ/N1 is able to boot from QSPI, NAND, or via USB (DFU). In all cases the +on-board BootROM expects for the binary to be wrapped with a "SPKG" header. + +It is possible to recover a bricked unit by using the USB (DFU) boot mode. This +allows uploading U-Boot into the internal RAM. Thereafter U-Boot can be used to +program the QSPI and/or NAND, making use of U-Boot dfu mode. + +Otherwise the only other option for recovery is via JTAG. diff --git a/doc/develop/bootstd.rst b/doc/develop/bootstd.rst index 5dfa6cfce5..7a2a69fdfc 100644 --- a/doc/develop/bootstd.rst +++ b/doc/develop/bootstd.rst @@ -154,7 +154,7 @@ bootmeths This environment variable can be used to control the list of bootmeths used and their ordering for example:: - setenv bootmeths "syslinux efi" + setenv bootmeths "extlinux efi" Entries may be removed or re-ordered in this list to affect the order the bootmeths are tried on each bootdev. If the variable is empty, the default @@ -389,8 +389,8 @@ Configuration ------------- Standard boot is enabled with `CONFIG_BOOTSTD`. Each bootmeth has its own CONFIG -option also. For example, `CONFIG_BOOTMETH_DISTRO` enables support for distro -boot from a disk. +option also. For example, `CONFIG_BOOTMETH_EXTLINUX` enables support for +booting from a disk using an `extlinux.conf` file. To enable all feature sof standard boot, use `CONFIG_BOOTSTD_FULL`. This includes the full set of commands, more error messages when things go wrong and @@ -406,8 +406,8 @@ Available bootmeth drivers Bootmeth drivers are provided for: - - distro boot from a disk (syslinux) - - distro boot from a network (PXE) + - extlinux / syslinux boot from a disk + - extlinux boot from a network (PXE) - U-Boot scripts from disk, network or SPI flash - EFI boot using bootefi from disk - VBE @@ -683,8 +683,8 @@ This feature can be added as needed. Note that sandbox is a special case, since in that case the host filesystem can be accessed even though the block device is NULL. -If we take the example of the `bootmeth_distro` driver, this call ends up at -`distro_read_bootflow()`. It has the filesystem ready, so tries various +If we take the example of the `bootmeth_extlinux` driver, this call ends up at +`extlinux_read_bootflow()`. It has the filesystem ready, so tries various filenames to try to find the `extlinux.conf` file, reading it if possible. If all goes well the bootflow ends up in the `BOOTFLOWST_READY` state. @@ -697,12 +697,12 @@ the `BOOTFLOWST_READY` state. That is the basic operation of scanning for bootflows. The process of booting a bootflow is handled by the bootmeth driver for that bootflow. In the case of -distro boot, this parses and processes the `extlinux.conf` file that was read. -See `distro_boot()` for how that works. The processing may involve reading +extlinux boot, this parses and processes the `extlinux.conf` file that was read. +See `extlinux_boot()` for how that works. The processing may involve reading additional files, which is handled by the `read_file()` method, which is -`distro_read_file()` in this case. All bootmethds should support reading files, -since the bootflow is typically only the basic instructions and does not include -the operating system itself, ramdisk, device tree, etc. +`extlinux_read_file()` in this case. All bootmethds should support reading +files, since the bootflow is typically only the basic instructions and does not +include the operating system itself, ramdisk, device tree, etc. The vast majority of the bootstd code is concerned with iterating through partitions on bootdevs and using bootmethds to find bootflows. diff --git a/doc/device-tree-bindings/bootmeth.txt b/doc/device-tree-bindings/bootmeth.txt index de6396a7b3..127b09cd1b 100644 --- a/doc/device-tree-bindings/bootmeth.txt +++ b/doc/device-tree-bindings/bootmeth.txt @@ -7,8 +7,8 @@ device (bootdev). These are normally created as children of the bootstd device. Required properties: compatible: - "u-boot,distro-syslinux" - distro boot from a block device - "u-boot,distro-pxe" - distro boot from a network device + "u-boot,extlinux" - distro boot from a block device + "u-boot,extlinux-pxe" - distro boot from a network device "u-boot,distro-efi" - EFI boot from an .efi file "u-boot,efi-bootmgr" - EFI boot using boot manager (bootmgr) @@ -21,8 +21,8 @@ Example: filename-prefixes = "/", "/boot/"; bootdev-order = "mmc2", "mmc1"; - syslinux { - compatible = "u-boot,distro-syslinux"; + extlinux { + compatible = "u-boot,extlinux"; }; efi { diff --git a/doc/device-tree-bindings/bootstd.txt b/doc/device-tree-bindings/bootstd.txt index 8706c5f499..1f1b9cba60 100644 --- a/doc/device-tree-bindings/bootstd.txt +++ b/doc/device-tree-bindings/bootstd.txt @@ -26,8 +26,8 @@ Example: filename-prefixes = "/", "/boot/"; bootdev-order = "mmc2", "mmc1"; - syslinux { - compatible = "u-boot,distro-syslinux"; + extlinux { + compatible = "u-boot,extlinux"; }; efi { diff --git a/doc/mkimage.1 b/doc/mkimage.1 index d8727ec73c..76c7859bb0 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -662,6 +662,51 @@ rk3568 .TE .RE . +.SS spkgimage +The primary configuration file consists of lines containing key/value pairs +delimited by whitespace. An example follows. +.PP +.RS +.EX +# Comments and blank lines may be used +.I key1 value1 +.I key2 value2 +.EE +.RE +.P +The supported +.I key +types are as follows. +.TP +.B VERSION +.TQ +.B NAND_ECC_BLOCK_SIZE +.TQ +.B NAND_ECC_ENABLE +.TQ +.B NAND_ECC_SCHEME +.TQ +.B NAND_BYTES_PER_ECC_BLOCK +These all take a positive integer value as their argument. +The value will be copied directly into the respective field +of the SPKG header structure. For details on these values, +refer to Section 7.4 of the Renesas RZ/N1 User's Manual. +. +.TP +.B ADD_DUMMY_BLP +Takes a numeric argument, which is treated as a boolean. Any nonzero +value will cause a fake BLp security header to be included in the SPKG +output. +. +.TP +.B PADDING +Takes a positive integer value, with an optional +.B K +or +.B M +suffix, indicating KiB / MiB respectively. +The output SPKG file will be padded to a multiple of this value. +. .SS sunxi_egon The primary configuration is the name to use for the device tree. . diff --git a/doc/usage/cmd/bootflow.rst b/doc/usage/cmd/bootflow.rst index cad09bbec9..8590efca21 100644 --- a/doc/usage/cmd/bootflow.rst +++ b/doc/usage/cmd/bootflow.rst @@ -148,7 +148,7 @@ Name mmc\@7e202000.bootdev.part_2 Device mmc\@7e202000.bootdev Block dev mmc\@7e202000.blk Type distro -Method: syslinux +Method: extlinux State ready Partition 2 Subdir (none) diff --git a/doc/usage/cmd/bootmeth.rst b/doc/usage/cmd/bootmeth.rst index 29d8215a0c..f632d74e1d 100644 --- a/doc/usage/cmd/bootmeth.rst +++ b/doc/usage/cmd/bootmeth.rst @@ -45,7 +45,7 @@ The format looks like this: ===== === ================== ================================= Order Seq Name Description ===== === ================== ================================= - 0 0 distro Syslinux boot from a block device + 0 0 extlinunx Extlinux boot from a block device 1 1 efi EFI boot from an .efi file 2 2 pxe PXE boot from a network device 3 3 sandbox Sandbox boot for testing @@ -77,7 +77,7 @@ This shows listing bootmeths. All are present and in the normal order:: => bootmeth list Order Seq Name Description ----- --- ------------------ ------------------ - 0 0 distro Syslinux boot from a block device + 0 0 distro Extlinux boot from a block device 1 1 efi EFI boot from an .efi file 2 2 pxe PXE boot from a network device 3 3 sandbox Sandbox boot for testing @@ -92,7 +92,7 @@ Now the order is changed, to include only two of them:: Order Seq Name Description ----- --- ------------------ ------------------ 0 3 sandbox Sandbox boot for testing - 1 0 distro Syslinux boot from a block device + 1 0 distro Extlinux boot from a block device ----- --- ------------------ ------------------ (2 bootmeths) @@ -102,7 +102,7 @@ which are not:: => bootmeth list -a Order Seq Name Description ----- --- ------------------ ------------------ - 1 0 distro Syslinux boot from a block device + 1 0 distro Extlinux boot from a block device - 1 efi EFI boot from an .efi file - 2 pxe PXE boot from a network device 0 3 sandbox Sandbox boot for testing diff --git a/doc/usage/cmd/dm.rst b/doc/usage/cmd/dm.rst index 236cd02bd6..74c6b01e36 100644 --- a/doc/usage/cmd/dm.rst +++ b/doc/usage/cmd/dm.rst @@ -366,7 +366,7 @@ This example shows the abridged sandbox output:: .. sysreset 0 [ ] sysreset_sandbox |-- sysreset_sandbox bootstd 0 [ ] bootstd_drv |-- bootstd - bootmeth 0 [ ] bootmeth_distro | |-- syslinux + bootmeth 0 [ ] bootmeth_extlinux | |-- extlinux bootmeth 1 [ ] bootmeth_efi | `-- efi reboot-mod 0 [ ] reboot-mode-gpio |-- reboot-mode0 reboot-mod 1 [ ] reboot-mode-rtc |-- reboot-mode@14 diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 45671c6925..437a82cd48 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -2,7 +2,12 @@ config CLK_RENESAS bool "Renesas clock drivers" depends on CLK && ARCH_RMOBILE help - Enable support for clock present on Renesas RCar SoCs. + Enable support for clock present on Renesas SoCs. + +config CLK_RCAR + bool "Renesas RCar clock driver support" + help + Enable common code for clocks on Renesas RCar SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" @@ -11,6 +16,7 @@ config CLK_RCAR_GEN2 bool "Renesas RCar Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS + select CLK_RCAR help Enable this to support the clocks on Renesas RCar Gen2 SoC. @@ -48,6 +54,7 @@ config CLK_RCAR_GEN3 bool "Renesas RCar Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS + select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help @@ -143,3 +150,9 @@ config CLK_R8A779G0 depends on CLK_RCAR_GEN3 help Enable this to support the clocks on Renesas R8A779G0 SoC. + +config CLK_R9A06G032 + bool "Renesas R9A06G032 clock driver" + depends on CLK_RENESAS + help + Enable this to support the clocks on Renesas R9A06G032 SoC. diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index fe0391e520..48373e61b9 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,4 +1,4 @@ -obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o +obj-$(CONFIG_CLK_RCAR) += renesas-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o @@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o +obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c new file mode 100644 index 0000000000..d2f61236fe --- /dev/null +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -0,0 +1,1103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R9A06G032 clock driver + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <asm/io.h> + +#include <dt-bindings/clock/r9a06g032-sysctrl.h> + +/** + * struct regbit - describe one bit in a register + * @reg: offset of register relative to base address, + * expressed in units of 32-bit words (not bytes), + * @bit: which bit (0 to 31) in the register + * + * This structure is used to compactly encode the location + * of a single bit in a register. Five bits are needed to + * encode the bit number. With uint16_t data type, this + * leaves 11 bits to encode a register offset up to 2047. + * + * Since registers are aligned on 32-bit boundaries, the + * offset will be specified in 32-bit words rather than bytes. + * This allows encoding an offset up to 0x1FFC (8188) bytes. + * + * Helper macro RB() takes care of converting the register + * offset from bytes to 32-bit words. + */ +struct regbit { + u16 reg:11; + u16 bit:5; +}; + +#define RB(_reg, _bit) ((struct regbit) { \ + .reg = (_reg) / 4, \ + .bit = (_bit) \ +}) + +/** + * struct r9a06g032_gate - clock-related control bits + * @gate: clock enable/disable + * @reset: clock module reset (active low) + * @ready: enables NoC forwarding of read/write requests to device, + * (eg. device is ready to handle read/write requests) + * @midle: request to idle the NoC interconnect + * + * Each of these fields describes a single bit in a register, + * which controls some aspect of clock gating. The @gate field + * is mandatory, this one enables/disables the clock. The + * other fields are optional, with zero indicating "not used". + * + * In most cases there is a @reset bit which needs to be + * de-asserted to bring the module out of reset. + * + * Modules may also need to signal when the are @ready to + * handle requests (read/writes) from the NoC interconnect. + * + * Similarly, the @midle bit is used to idle the master. + */ +struct r9a06g032_gate { + struct regbit gate, reset, ready, midle; + /* Unused fields omitted to save space */ + /* struct regbit scon, mirack, mistat */; +}; + +enum gate_type { + K_GATE = 0, /* gate which enable/disable */ + K_FFC, /* fixed factor clock */ + K_DIV, /* divisor */ + K_BITSEL, /* special for UARTs */ + K_DUALGATE /* special for UARTs */ +}; + +/** + * struct r9a06g032_clkdesc - describe a single clock + * @name: string describing this clock + * @managed: boolean indicating if this clock should be + * started/stopped as part of power management + * (not used in u-boot) + * @type: see enum @gate_type + * @index: the ID of this clock element + * @source: the ID+1 of the parent clock element. + * Root clock uses ID of ~0 (PARENT_ID); + * @gate: clock enable/disable + * @div_min: smallest permitted clock divider + * @div_max: largest permitted clock divider + * @reg: clock divider register offset, in 32-bit words + * @div_table: optional list of fixed clock divider values; + * must be in ascending order, zero for unused + * @div: divisor for fixed-factor clock + * @mul: multiplier for fixed-factor clock + * @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7 + * @sel: select either g1/r1 or g2/r2 as clock source + * @g1: 1st source gate (clock enable/disable) + * @r1: 1st source reset (module reset) + * @g2: 2nd source gate (clock enable/disable) + * @r2: 2nd source reset (module reset) + * + * Describes a single element in the clock tree hierarchy. + * As there are quite a large number of clock elements, this + * structure is packed tightly to conserve space. + */ +struct r9a06g032_clkdesc { + const char *name; + uint32_t managed:1; + enum gate_type type:3; + uint32_t index:8; + uint32_t source:8; /* source index + 1 (0 == none) */ + union { + /* type = K_GATE */ + struct r9a06g032_gate gate; + /* type = K_DIV */ + struct { + unsigned int div_min:10, div_max:10, reg:10; + u16 div_table[4]; + }; + /* type = K_FFC */ + struct { + u16 div, mul; + }; + /* type = K_DUALGATE */ + struct { + uint16_t group:1; + struct regbit sel, g1, r1, g2, r2; + } dual; + }; +}; + +/* + * The last three arguments are not currently used, + * but are kept in the r9a06g032_clocks table below. + */ +#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \ + .gate = _clk, \ + .reset = _rst, \ + .ready = _rdy, \ + .midle = _midle, \ + /* .scon = _scon, */ \ + /* .mirack = _mirack, */ \ + /* .mistat = _mistat */ \ +} +#define D_GATE(_idx, _n, _src, ...) { \ + .type = K_GATE, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .gate = I_GATE(__VA_ARGS__) \ +} +#define D_MODULE(_idx, _n, _src, ...) { \ + .type = K_GATE, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .managed = 1, \ + .gate = I_GATE(__VA_ARGS__) \ +} +#define D_ROOT(_idx, _n, _mul, _div) { \ + .type = K_FFC, \ + .index = R9A06G032_##_idx, \ + .name = _n, \ + .div = _div, \ + .mul = _mul \ +} +#define D_FFC(_idx, _n, _src, _div) { \ + .type = K_FFC, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .div = _div, \ + .mul = 1 \ +} +#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ + .type = K_DIV, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .reg = _reg, \ + .div_min = _min, \ + .div_max = _max, \ + .div_table = { __VA_ARGS__ } \ +} +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \ + .type = K_DUALGATE, \ + .index = R9A06G032_##_idx, \ + .source = 1 + R9A06G032_##_src, \ + .name = _n, \ + .dual = { \ + .group = _g, \ + .g1 = _g1, \ + .r1 = _r1, \ + .g2 = _g2, \ + .r2 = _r2 \ + }, \ +} + +/* Internal clock IDs */ +#define R9A06G032_CLKOUT 0 +#define R9A06G032_CLKOUT_D10 2 +#define R9A06G032_CLKOUT_D16 3 +#define R9A06G032_CLKOUT_D160 4 +#define R9A06G032_CLKOUT_D1OR2 5 +#define R9A06G032_CLKOUT_D20 6 +#define R9A06G032_CLKOUT_D40 7 +#define R9A06G032_CLKOUT_D5 8 +#define R9A06G032_CLKOUT_D8 9 +#define R9A06G032_DIV_ADC 10 +#define R9A06G032_DIV_I2C 11 +#define R9A06G032_DIV_NAND 12 +#define R9A06G032_DIV_P1_PG 13 +#define R9A06G032_DIV_P2_PG 14 +#define R9A06G032_DIV_P3_PG 15 +#define R9A06G032_DIV_P4_PG 16 +#define R9A06G032_DIV_P5_PG 17 +#define R9A06G032_DIV_P6_PG 18 +#define R9A06G032_DIV_QSPI0 19 +#define R9A06G032_DIV_QSPI1 20 +#define R9A06G032_DIV_REF_SYNC 21 +#define R9A06G032_DIV_SDIO0 22 +#define R9A06G032_DIV_SDIO1 23 +#define R9A06G032_DIV_SWITCH 24 +#define R9A06G032_DIV_UART 25 +#define R9A06G032_DIV_MOTOR 64 +#define R9A06G032_CLK_DDRPHY_PLLCLK_D4 78 +#define R9A06G032_CLK_ECAT100_D4 79 +#define R9A06G032_CLK_HSR100_D2 80 +#define R9A06G032_CLK_REF_SYNC_D4 81 +#define R9A06G032_CLK_REF_SYNC_D8 82 +#define R9A06G032_CLK_SERCOS100_D2 83 +#define R9A06G032_DIV_CA7 84 + +#define R9A06G032_UART_GROUP_012 154 +#define R9A06G032_UART_GROUP_34567 155 + +#define R9A06G032_CLOCK_COUNT (R9A06G032_UART_GROUP_34567 + 1) + +static const struct r9a06g032_clkdesc r9a06g032_clocks[] = { + D_ROOT(CLKOUT, "clkout", 25, 1), + D_ROOT(CLK_PLL_USB, "clk_pll_usb", 12, 10), + D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10), + D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16), + D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160), + D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2), + D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20), + D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40), + D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5), + D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8), + D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250), + D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16), + D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32), + D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200), + D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128), + D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128), + D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128), + D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40), + D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64), + D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7), + D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7), + D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16), + D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128), + D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128), + D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40), + D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128), + D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9), + RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0), + RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12), + RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0), + RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15), + RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0), + RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18), + RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0), + RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21), + RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0), + RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10), + RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6), + RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8), + RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4), + RB(0x50, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20), + RB(0xec, 21), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2), + RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4), + RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6), + RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4), + RB(0x104, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6), + RB(0x104, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0), + RB(0x114, 1), RB(0x114, 2), RB(0x00, 0), + RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3), + RB(0x114, 4), RB(0x114, 5), RB(0x00, 0), + RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6), + RB(0x114, 7), RB(0x114, 8), RB(0x00, 0), + RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9), + RB(0x114, 10), RB(0x114, 11), RB(0x00, 0), + RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4), + RB(0x54, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4), + RB(0x90, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0), + RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0), + RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2), + RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4), + RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6), + RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0), + RB(0x104, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2), + RB(0x104, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2), + RB(0x130, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8), + D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0), + RB(0x80, 1), RB(0x00, 0), RB(0x80, 2), + RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)), + D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0), + RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0), + RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0), + RB(0x84, 2), RB(0x00, 0), RB(0x84, 1), + RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)), + D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3), + RB(0x118, 4), RB(0x118, 5), RB(0x00, 0), + RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6), + RB(0x118, 7), RB(0x118, 8), RB(0x00, 0), + RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9), + RB(0x118, 10), RB(0x118, 11), RB(0x00, 0), + RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3), + RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0), + RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6), + RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0), + RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3), + RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4), + RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)), + D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0), + RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2), + RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)), + D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12), + RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14), + RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)), + D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9), + RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0), + RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)), + D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4), + D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4), + D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2), + D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4), + D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8), + D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2), + D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4), + D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3), + RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0), + RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6), + RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0), + RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15), + RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12), + RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0), + RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0), + RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0), + RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3), + RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640), + D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0), + RB(0x174, 1), RB(0x00, 0), RB(0x174, 2), + RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)), + D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3), + RB(0x64, 4), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3), + RB(0x80, 4), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4), + RB(0x90, 5), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0), + RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4), + RB(0x84, 3), RB(0x00, 0), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15), + RB(0x34, 16), RB(0x34, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0), + RB(0x184, 1), RB(0x184, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3), + RB(0x24, 4), RB(0x24, 5), RB(0x00, 0), + RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0), + RB(0x24, 1), RB(0x00, 0), RB(0x24, 2), + RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)), + D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0), + RB(0x64, 2), RB(0x00, 0), RB(0x64, 1), + RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)), + D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0), + RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3), + RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)), + D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4), + RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7), + RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)), + D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0), + RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3), + RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)), + D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0), + RB(0x70, 1), RB(0x70, 2), RB(0x70, 3), + RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)), + D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18), + RB(0x40, 19), RB(0x40, 20), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21), + RB(0x40, 22), RB(0x40, 23), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9), + RB(0x44, 10), RB(0x44, 11), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0), + RB(0x90, 2), RB(0x00, 0), RB(0x90, 1), + RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)), + D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9), + RB(0x34, 10), RB(0x34, 11), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12), + RB(0x34, 13), RB(0x34, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0), + RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0), + RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4), + RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0), + RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0), + RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3), + RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)), + D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0), + RB(0x50, 1), RB(0x50, 2), RB(0x50, 3), + RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)), + D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12), + RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14), + RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)), + D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12), + RB(0x44, 13), RB(0x44, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15), + RB(0x44, 16), RB(0x44, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6), + RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0), + RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9), + RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0), + RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0), + RB(0x54, 1), RB(0x54, 2), RB(0x54, 3), + RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)), + D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0), + RB(0x90, 1), RB(0x90, 2), RB(0x90, 3), + RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)), + D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0), + RB(0x154, 1), RB(0x154, 2), RB(0x00, 0), + RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0), + RB(0x140, 3), RB(0x00, 0), RB(0x140, 2), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0), + RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3), + RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)), + D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0), + RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3), + RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)), + D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3), + RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0), + RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0), + RB(0x40, 1), RB(0x40, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3), + RB(0x40, 4), RB(0x40, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6), + RB(0x40, 7), RB(0x40, 8), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9), + RB(0x40, 10), RB(0x40, 11), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12), + RB(0x40, 13), RB(0x40, 14), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15), + RB(0x40, 16), RB(0x40, 17), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0), + RB(0x00, 0), RB(0x130, 1), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0), + RB(0x188, 1), RB(0x188, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0), + RB(0x34, 1), RB(0x34, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3), + RB(0x34, 4), RB(0x34, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6), + RB(0x34, 7), RB(0x34, 8), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24), + RB(0x40, 25), RB(0x40, 26), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27), + RB(0x40, 28), RB(0x40, 29), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0), + RB(0x44, 1), RB(0x44, 2), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3), + RB(0x44, 4), RB(0x44, 5), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6), + RB(0x44, 7), RB(0x44, 8), RB(0x00, 0), + RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)), + /* + * These are not hardware clocks, but are needed to handle the special + * case where we have a 'selector bit' that doesn't just change the + * parent for a clock, but also the gate it's supposed to use. + */ + { + .index = R9A06G032_UART_GROUP_012, + .name = "uart_group_012", + .type = K_BITSEL, + .source = 1 + R9A06G032_DIV_UART, + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */ + .dual.sel = RB(0x34, 30), + .dual.group = 0, + }, + { + .index = R9A06G032_UART_GROUP_34567, + .name = "uart_group_34567", + .type = K_BITSEL, + .source = 1 + R9A06G032_DIV_P2_PG, + /* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */ + .dual.sel = RB(0xec, 24), + .dual.group = 1, + }, + D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, + RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)), + D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, + RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)), + D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, + RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)), + D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, + RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)), + D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, + RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)), + D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, + RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)), + D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, + RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)), + D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, + RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)), +}; + +struct r9a06g032_priv { + struct regmap *regmap; + struct clk mclk; +}; + +static const struct r9a06g032_clkdesc *r9a06g032_clk_get(struct clk *clk) +{ + const unsigned long clkid = clk->id & 0xffff; + int i; + + for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); i++) { + if (r9a06g032_clocks[i].index == clkid) + return &r9a06g032_clocks[i]; + } + + return NULL; +} + +#define PARENT_ID (~0) + +static int r9a06g032_clk_get_parent(struct clk *clk, struct clk *parent) +{ + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + + if (!desc) + return -ENOENT; + + if (desc->source) + parent->id = desc->source - 1; + else + parent->id = PARENT_ID; /* Top-level clock */ + + parent->dev = clk->dev; + + return 0; +} + +static ulong r9a06g032_clk_get_parent_rate(struct clk *clk) +{ + struct clk parent; + unsigned long parent_rate; + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + + if (r9a06g032_clk_get_parent(clk, &parent)) { + dev_dbg(clk->dev, "Failed to get parent clock for id=%lu\b", clk->id); + return 0; + } + + if (parent.id == PARENT_ID) + parent_rate = clk_get_rate(&clocks->mclk); + else + parent_rate = clk_get_rate(&parent); + + if (!parent_rate) + dev_dbg(clk->dev, "%s: parent_rate is zero\n", __func__); + + return parent_rate; +} + +/* register/bit pairs are encoded as an uint16_t */ +static void clk_rdesc_set(struct r9a06g032_priv *clocks, + struct regbit rb, unsigned int on) +{ + uint reg = rb.reg * 4; + uint bit = rb.bit; + + if (!reg && !bit) + return; + + uint mask = BIT(bit); + uint val = (!!on) << bit; + + regmap_update_bits(clocks->regmap, reg, mask, val); +} + +static int clk_rdesc_get(struct r9a06g032_priv *clocks, + struct regbit rb) +{ + uint reg = rb.reg * 4; + uint bit = rb.bit; + u32 val = 0; + + regmap_read(clocks->regmap, reg, &val); + + return !!(val & BIT(bit)); +} + +/* + * Cheating a little bit here: leverage the existing code to control the + * per-clock reset. It should really be handled by a reset controller instead. + */ +void clk_rzn1_reset_state(struct clk *clk, int on) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + const struct r9a06g032_gate *g; + + assert(desc); + assert(desc->type == K_GATE); + g = &desc->gate; + + clk_rdesc_set(clocks, g->reset, on); +} + +/* + * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's + * clock gate framework as the gates on the R9A06G032 have a special enabling + * sequence, therefore we use this little proxy. + */ +static int r9a06g032_clk_gate_set(struct clk *clk, int on) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + const struct r9a06g032_gate *g; + + assert(desc); + assert(desc->type == K_GATE); + g = &desc->gate; + + /* Enable or disable the clock */ + clk_rdesc_set(clocks, g->gate, on); + + /* De-assert reset */ + clk_rdesc_set(clocks, g->reset, 1); + + /* Hardware manual recommends 5us delay after enabling clock & reset */ + udelay(5); + + /* If the peripheral is memory mapped (i.e. an AXI slave), there is an + * associated SLVRDY bit in the System Controller that needs to be set + * so that the FlexWAY bus fabric passes on the read/write requests. + */ + clk_rdesc_set(clocks, g->ready, on); + + /* Clear 'Master Idle Request' bit */ + clk_rdesc_set(clocks, g->midle, !on); + + /* Note: We don't wait for FlexWAY Socket Connection signal */ + + return 0; +} + +static int r9a06g032_clk_gate_enable(struct clk *clk) +{ + return r9a06g032_clk_gate_set(clk, 1); +} + +static int r9a06g032_clk_gate_disable(struct clk *clk) +{ + return r9a06g032_clk_gate_set(clk, 0); +} + +/* + * Fixed factor clock + */ +static ulong r9a06g032_ffc_get_rate(struct clk *clk) +{ + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + unsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk); + unsigned long long rate; + + rate = (unsigned long long)parent_rate * desc->mul; + rate = DIV_ROUND_UP(rate, desc->div); + + return (ulong)rate; +} + +/* + * This implements R9A06G032 clock divider 'driver'. This differs from the + * standard clk_divider because the set_rate method must also set b[31] to + * trigger the hardware rate change. In theory it should also wait for this + * bit to clear. + */ +static ulong r9a06g032_div_get_rate(struct clk *clk) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + unsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk); + u32 div = 0; + + regmap_read(clocks->regmap, 4 * desc->reg, &div); + + if (div < desc->div_min) + div = desc->div_min; + else if (div > desc->div_max) + div = desc->div_max; + return DIV_ROUND_UP(parent_rate, div); +} + +static ulong r9a06g032_div_set_rate(struct clk *clk, ulong rate) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + unsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk); + size_t i; + + /* + 1 to cope with rates that have the remainder dropped */ + u32 div = DIV_ROUND_UP(parent_rate, rate + 1); + + /* Clamp to allowable range */ + if (div < desc->div_min) + div = desc->div_min; + else if (div > desc->div_max) + div = desc->div_max; + + /* Limit to allowable divisors */ + for (i = 0; i < ARRAY_SIZE(desc->div_table) - 2; i++) { + u16 div_m = desc->div_table[i]; + u16 div_p = desc->div_table[i + 1]; + + if (!div_m || !div_p) + continue; + + if (div >= div_m && div <= div_p) { + /* + * select the divider that generates + * the value closest to ideal frequency + */ + u32 m = rate - DIV_ROUND_UP(parent_rate, div_m); + u32 p = DIV_ROUND_UP(parent_rate, div_p) - rate; + + div = p >= m ? div_m : div_p; + } + } + + dev_dbg(clk->dev, "%s clkid %lu rate %ld parent %ld div %d\n", + __func__, clk->id, rate, parent_rate, div); + + /* + * Need to write the bit 31 with the divider value to + * latch it. Technically we should wait until it has been + * cleared too. + * TODO: Find whether this callback is sleepable, in case + * the hardware /does/ require some sort of spinloop here. + */ + regmap_write(clocks->regmap, 4 * desc->reg, div | BIT(31)); + + return 0; +} + +/* + * Dual gate. This handles toggling the approprate clock/reset bits, + * which depends on the mux setting above. + */ +static int r9a06g032_clk_dualgate_setenable(struct r9a06g032_priv *clocks, + const struct r9a06g032_clkdesc *desc, + int enable) +{ + u8 sel_bit = clk_rdesc_get(clocks, desc->dual.sel); + struct regbit gate[2] = { desc->dual.g1, desc->dual.g2 }; + struct regbit reset[2] = { desc->dual.r1, desc->dual.r2 }; + + /* we always turn off the 'other' gate, regardless */ + clk_rdesc_set(clocks, gate[!sel_bit], 0); + clk_rdesc_set(clocks, reset[!sel_bit], 1); + + /* set the gate as requested */ + clk_rdesc_set(clocks, gate[sel_bit], enable); + clk_rdesc_set(clocks, reset[sel_bit], 1); + + return 0; +} + +static int r9a06g032_clk_dualgate_enable(struct clk *clk) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + + return r9a06g032_clk_dualgate_setenable(clocks, desc, 1); +} + +static int r9a06g032_clk_dualgate_disable(struct clk *clk) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + + return r9a06g032_clk_dualgate_setenable(clocks, desc, 0); +} + +static int r9a06g032_clk_dualgate_is_enabled(struct clk *clk) +{ + struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + u8 sel_bit = clk_rdesc_get(clocks, desc->dual.sel); + struct regbit gate[2] = { desc->dual.g1, desc->dual.g2 }; + + return clk_rdesc_get(clocks, gate[sel_bit]); +} + +/* + * Main clock driver + */ +static int r9a06g032_clk_enable(struct clk *clk) +{ + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + + switch (desc->type) { + case K_GATE: + return r9a06g032_clk_gate_enable(clk); + case K_DUALGATE: + return r9a06g032_clk_dualgate_enable(clk); + default: + dev_dbg(clk->dev, "ERROR: unhandled type=%d\n", desc->type); + break; + } + + return 0; +} + +static int r9a06g032_clk_disable(struct clk *clk) +{ + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + + switch (desc->type) { + case K_GATE: + return r9a06g032_clk_gate_disable(clk); + case K_DUALGATE: + return r9a06g032_clk_dualgate_disable(clk); + default: + dev_dbg(clk->dev, "ERROR: unhandled type=%d\n", desc->type); + break; + } + + return 0; +} + +static ulong r9a06g032_clk_get_rate(struct clk *clk) +{ + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + ulong ret = 0; + + assert(desc); + + switch (desc->type) { + case K_FFC: + ret = r9a06g032_ffc_get_rate(clk); + break; + case K_GATE: + ret = r9a06g032_clk_get_parent_rate(clk); + break; + case K_DIV: + ret = r9a06g032_div_get_rate(clk); + break; + case K_BITSEL: + /* + * Look at the mux to determine parent. + * 0 means it is coming from UART DIV (group 012 or 34567) + * 1 means it is coming from USB_PLL (fixed at 48MHz) + */ + if (r9a06g032_clk_dualgate_is_enabled(clk)) { + struct clk usb_clk = { .id = R9A06G032_CLK_PLL_USB }; + + ret = r9a06g032_clk_get_parent_rate(&usb_clk); + } else { + ret = r9a06g032_clk_get_parent_rate(clk); + } + break; + case K_DUALGATE: + ret = r9a06g032_clk_get_parent_rate(clk); + break; + } + + return ret; +} + +static ulong r9a06g032_clk_set_rate(struct clk *clk, ulong rate) +{ + const struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk); + ulong ret = 0; + + assert(desc); + + switch (desc->type) { + case K_DIV: + ret = r9a06g032_div_set_rate(clk, rate); + break; + default: + dev_dbg(clk->dev, "ERROR: not implemented for %d\n", desc->type); + }; + + return ret; +} + +static int r9a06g032_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + if (args->args_count != 1) { + dev_dbg(clk->dev, "Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + clk->id = args->args[0]; + + return 0; +} + +static const struct clk_ops r9a06g032_clk_ops = { + .enable = r9a06g032_clk_enable, + .disable = r9a06g032_clk_disable, + .get_rate = r9a06g032_clk_get_rate, + .set_rate = r9a06g032_clk_set_rate, + .of_xlate = r9a06g032_clk_of_xlate, +}; + +/* Reset Enable Register */ +#define RZN1_SYSCTRL_REG_RSTEN 288 /* 0x120*/ +#define RZN1_SYSCTRL_REG_RSTEN_MRESET_EN BIT(0) +#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_CA7_0_EN BIT(1) +#define RZN1_SYSCTRL_REG_RSTEN_WDA7RST_CA7_1_EN BIT(2) +#define RZN1_SYSCTRL_REG_RSTEN_WDM3RST_EN BIT(3) +#define RZN1_SYSCTRL_REG_RSTEN_CM3LOCKUPRST_EN BIT(4) +#define RZN1_SYSCTRL_REG_RSTEN_CM3SYSRESET_EN BIT(5) +#define RZN1_SYSCTRL_REG_RSTEN_SWRST_EN BIT(6) + +static int r9a06g032_clk_probe(struct udevice *dev) +{ + struct r9a06g032_priv *priv = dev_get_priv(dev); + + priv->regmap = syscon_regmap_lookup_by_phandle(dev, "regmap"); + if (IS_ERR(priv->regmap)) { + dev_dbg(dev, "unable to find regmap\n"); + return PTR_ERR(priv->regmap); + } + + /* Enable S/W reset */ + regmap_write(priv->regmap, RZN1_SYSCTRL_REG_RSTEN, + RZN1_SYSCTRL_REG_RSTEN_MRESET_EN | + RZN1_SYSCTRL_REG_RSTEN_SWRST_EN); + + /* Get master clock */ + return clk_get_by_name(dev, "mclk", &priv->mclk); +} + +static const struct udevice_id r9a06g032_clk_ids[] = { + { .compatible = "renesas,r9a06g032-sysctrl" }, + { } +}; + +U_BOOT_DRIVER(clk_r9a06g032) = { + .name = "clk_r9a06g032", + .id = UCLASS_CLK, + .of_match = r9a06g032_clk_ids, + .priv_auto = sizeof(struct r9a06g032_priv), + .ops = &r9a06g032_clk_ops, + .probe = &r9a06g032_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 3b59b70c24..546db675aa 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -131,7 +131,10 @@ void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index, { fdt_addr_t addr = devfdt_get_addr_size_index(dev, index, size); - return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)(uintptr_t)addr; + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return map_sysmem(addr, 0); } fdt_addr_t devfdt_get_addr_name(const struct udevice *dev, const char *name) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index f49ee493d3..ec574c4460 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -998,7 +998,7 @@ int ofnode_decode_panel_timing(ofnode parent, u32 val = 0; int ret = 0; - timings = ofnode_find_subnode(parent, "panel-timings"); + timings = ofnode_find_subnode(parent, "panel-timing"); if (!ofnode_valid(timings)) return -EINVAL; memset(dt, 0, sizeof(*dt)); diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index dee84263c3..3b74feae68 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -90,7 +90,7 @@ static int s5p_sdhci_core_init(struct sdhci_host *host) host->name = S5P_NAME; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | - SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; host->max_clk = 52000000; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index f378f6fb61..8ade7949a6 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -2196,6 +2196,12 @@ ulong flash_get_size(phys_addr_t base, int banknum) /* multiply the size by the number of chips */ info->size *= size_ratio; max_size = cfi_flash_bank_size(banknum); +#ifdef CONFIG_CFI_FLASH + if (max_size) + max_size = min((unsigned long)info->addr_size, max_size); + else + max_size = info->addr_size; +#endif if (max_size && info->size > max_size) { debug("[truncated from %ldMiB]", info->size >> 20); info->size = max_size; @@ -2492,15 +2498,17 @@ unsigned long flash_init(void) static int cfi_flash_probe(struct udevice *dev) { fdt_addr_t addr; + fdt_size_t size; int idx; for (idx = 0; idx < CFI_MAX_FLASH_BANKS; idx++) { - addr = dev_read_addr_index(dev, idx); + addr = dev_read_addr_size_index(dev, idx, &size); if (addr == FDT_ADDR_T_NONE) break; flash_info[cfi_flash_num_flash_banks].dev = dev; flash_info[cfi_flash_num_flash_banks].base = addr; + flash_info[cfi_flash_num_flash_banks].addr_size = size; cfi_flash_num_flash_banks++; } gd->bd->bi_flashstart = flash_info[0].base; diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 852adee4b4..fc1f01a02c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_ARCH_RMOBILE) += renesas/ +obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 509cdd3fb2..0ea39b4a3f 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -139,3 +139,10 @@ config PINCTRL_PFC_R7S72100 Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs. endif + +config PINCTRL_RZN1 + bool "Renesas RZ/N1 R906G032 pin control driver" + depends on RZN1 + default y if RZN1 + help + Support pin multiplexing control on Renesas RZ/N1 R906G032 SoCs. diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 5cea1423ca..1a61c39d84 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o +obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c new file mode 100644 index 0000000000..fdc43c8e71 --- /dev/null +++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2018 Renesas Electronics Europe Limited + * + * Phil Edworthy <phil.edworthy@renesas.com> + * Based on a driver originally written by Michel Pollet at Renesas. + */ + +#include <dt-bindings/pinctrl/rzn1-pinctrl.h> + +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/pinctrl.h> +#include <dm/read.h> +#include <regmap.h> + +/* Field positions and masks in the pinmux registers */ +#define RZN1_L1_PIN_DRIVE_STRENGTH 10 +#define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0 +#define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1 +#define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2 +#define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3 +#define RZN1_L1_PIN_PULL 8 +#define RZN1_L1_PIN_PULL_NONE 0 +#define RZN1_L1_PIN_PULL_UP 1 +#define RZN1_L1_PIN_PULL_DOWN 3 +#define RZN1_L1_FUNCTION 0 +#define RZN1_L1_FUNC_MASK 0xf +#define RZN1_L1_FUNCTION_L2 0xf + +/* + * The hardware manual describes two levels of multiplexing, but it's more + * logical to think of the hardware as three levels, with level 3 consisting of + * the multiplexing for Ethernet MDIO signals. + * + * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying + * that level 2 functions are used instead. Level 2 has a lot more options, + * going from 0 to 61. Level 3 allows selection of MDIO functions which can be + * floating, or one of seven internal peripherals. Unfortunately, there are two + * level 2 functions that can select MDIO, and two MDIO channels so we have four + * sets of level 3 functions. + * + * For this driver, we've compounded the numbers together, so: + * 0 to 9 is level 1 + * 10 to 71 is 10 + level 2 number + * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function. + * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function. + * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function. + * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function. + * Examples: + * Function 28 corresponds UART0 + * Function 73 corresponds to MDIO0 to GMAC0 + * + * There are 170 configurable pins (called PL_GPIO in the datasheet). + */ + +/* + * Structure detailing the HW registers on the RZ/N1 devices. + * Both the Level 1 mux registers and Level 2 mux registers have the same + * structure. The only difference is that Level 2 has additional MDIO registers + * at the end. + */ +struct rzn1_pinctrl_regs { + u32 conf[170]; + u32 pad0[86]; + u32 status_protect; /* 0x400 */ + /* MDIO mux registers, level2 only */ + u32 l2_mdio[2]; +}; + +#define NUM_CONF ARRAY_SIZE(((struct rzn1_pinctrl_regs *)0)->conf) + +#define level1_write(map, member, val) \ + regmap_range_set(map, 0, struct rzn1_pinctrl_regs, member, val) + +#define level1_read(map, member, valp) \ + regmap_range_get(map, 0, struct rzn1_pinctrl_regs, member, valp) + +#define level2_write(map, member, val) \ + regmap_range_set(map, 1, struct rzn1_pinctrl_regs, member, val) + +#define level2_read(map, member, valp) \ + regmap_range_get(map, 1, struct rzn1_pinctrl_regs, member, valp) + +/** + * struct rzn1_pmx_func - describes rzn1 pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + * @num_groups: the number of groups + */ +struct rzn1_pmx_func { + const char *name; + const char **groups; + unsigned int num_groups; +}; + +/** + * struct rzn1_pin_group - describes an rzn1 pin group + * @name: the name of this specific pin group + * @func: the name of the function selected by this group + * @npins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins() + * @pin_ids: array of pin_ids, i.e. the value used to select the mux + */ +struct rzn1_pin_group { + const char *name; + const char *func; + unsigned int npins; + unsigned int *pins; + u8 *pin_ids; +}; + +struct rzn1_pinctrl { + struct device *dev; + struct clk *clk; + struct pinctrl_dev *pctl; + u32 lev1_protect_phys; + u32 lev2_protect_phys; + int mdio_func[2]; + + struct rzn1_pin_group *groups; + unsigned int ngroups; + + struct rzn1_pmx_func *functions; + unsigned int nfunctions; +}; + +struct rzn1_pinctrl_priv { + struct regmap *regmap; + u32 lev1_protect_phys; + u32 lev2_protect_phys; + + struct clk *clk; +}; + +enum { + LOCK_LEVEL1 = 0x1, + LOCK_LEVEL2 = 0x2, + LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2, +}; + +static void rzn1_hw_set_lock(struct rzn1_pinctrl_priv *priv, u8 lock, u8 value) +{ + /* + * The pinmux configuration is locked by writing the physical address of + * the status_protect register to itself. It is unlocked by writing the + * address | 1. + */ + if (lock & LOCK_LEVEL1) { + u32 val = priv->lev1_protect_phys | !(value & LOCK_LEVEL1); + + level1_write(priv->regmap, status_protect, val); + } + + if (lock & LOCK_LEVEL2) { + u32 val = priv->lev2_protect_phys | !(value & LOCK_LEVEL2); + + level2_write(priv->regmap, status_protect, val); + } +} + +static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl_priv *priv, int mdio, + u32 func) +{ + debug("setting mdio%d to %u\n", mdio, func); + + level2_write(priv->regmap, l2_mdio[mdio], func); +} + +/* + * Using a composite pin description, set the hardware pinmux registers + * with the corresponding values. + * Make sure to unlock write protection and reset it afterward. + * + * NOTE: There is no protection for potential concurrency, it is assumed these + * calls are serialized already. + */ +static int rzn1_set_hw_pin_func(struct rzn1_pinctrl_priv *priv, + unsigned int pin, unsigned int func) +{ + u32 l1_cache; + u32 l2_cache; + u32 l1; + u32 l2; + + /* Level 3 MDIO multiplexing */ + if (func >= RZN1_FUNC_MDIO0_HIGHZ && + func <= RZN1_FUNC_MDIO1_E1_SWITCH) { + int mdio_channel; + u32 mdio_func; + + if (func <= RZN1_FUNC_MDIO1_HIGHZ) + mdio_channel = 0; + else + mdio_channel = 1; + + /* Get MDIO func, and convert the func to the level 2 number */ + if (func <= RZN1_FUNC_MDIO0_SWITCH) { + mdio_func = func - RZN1_FUNC_MDIO0_HIGHZ; + func = RZN1_FUNC_ETH_MDIO; + } else if (func <= RZN1_FUNC_MDIO0_E1_SWITCH) { + mdio_func = func - RZN1_FUNC_MDIO0_E1_HIGHZ; + func = RZN1_FUNC_ETH_MDIO_E1; + } else if (func <= RZN1_FUNC_MDIO1_SWITCH) { + mdio_func = func - RZN1_FUNC_MDIO1_HIGHZ; + func = RZN1_FUNC_ETH_MDIO; + } else { + mdio_func = func - RZN1_FUNC_MDIO1_E1_HIGHZ; + func = RZN1_FUNC_ETH_MDIO_E1; + } + rzn1_pinctrl_mdio_select(priv, mdio_channel, mdio_func); + } + + /* Note here, we do not allow anything past the MDIO Mux values */ + if (pin >= NUM_CONF || func >= RZN1_FUNC_MDIO0_HIGHZ) + return -EINVAL; + + level1_read(priv->regmap, conf[pin], &l1); + l1_cache = l1; + level2_read(priv->regmap, conf[pin], &l2); + l2_cache = l2; + + debug("setting func for pin %u to %u\n", pin, func); + + l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION); + + if (func < RZN1_FUNC_L2_OFFSET) { + l1 |= (func << RZN1_L1_FUNCTION); + } else { + l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION); + + l2 = func - RZN1_FUNC_L2_OFFSET; + } + + /* If either configuration changes, we update both anyway */ + if (l1 != l1_cache || l2 != l2_cache) { + level1_write(priv->regmap, conf[pin], l1); + level2_write(priv->regmap, conf[pin], l2); + } + + return 0; +} + +static int rzn1_pinconf_set(struct rzn1_pinctrl_priv *priv, unsigned int pin, + unsigned int bias, unsigned int strength) +{ + u32 l1, l1_cache; + u32 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA; + + level1_read(priv->regmap, conf[pin], &l1); + l1_cache = l1; + + switch (bias) { + case PIN_CONFIG_BIAS_PULL_UP: + debug("set pin %d pull up\n", pin); + l1 &= ~(0x3 << RZN1_L1_PIN_PULL); + l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + debug("set pin %d pull down\n", pin); + l1 &= ~(0x3 << RZN1_L1_PIN_PULL); + l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL); + break; + case PIN_CONFIG_BIAS_DISABLE: + debug("set pin %d bias off\n", pin); + l1 &= ~(0x3 << RZN1_L1_PIN_PULL); + l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL); + break; + } + + switch (strength) { + case 4: + drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA; + break; + case 6: + drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA; + break; + case 8: + drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA; + break; + case 12: + drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA; + break; + } + + debug("set pin %d drv %umA\n", pin, drv); + + l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH); + l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH); + + if (l1 != l1_cache) + level1_write(priv->regmap, conf[pin], l1); + + return 0; +} + +static int rzn1_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + struct rzn1_pinctrl_priv *priv = dev_get_priv(dev); + int size; + int ret; + u32 val; + u32 bias; + + /* Pullup/down bias, common to all pins in group */ + bias = PIN_CONFIG_BIAS_PULL_UP; + if (dev_read_bool(config, "bias-disable")) + bias = PIN_CONFIG_BIAS_DISABLE; + else if (dev_read_bool(config, "bias-pull-up")) + bias = PIN_CONFIG_BIAS_PULL_UP; + else if (dev_read_bool(config, "bias-pull-down")) + bias = PIN_CONFIG_BIAS_PULL_DOWN; + + /* Drive strength, common to all pins in group */ + u32 strength = dev_read_u32_default(config, "drive-strength", 8); + + /* Number of pins */ + ret = dev_read_size(config, "pinmux"); + if (ret < 0) + return ret; + + size = ret / sizeof(val); + + for (int i = 0; i < size; i++) { + ret = dev_read_u32_index(config, "pinmux", i, &val); + if (ret) + return ret; + unsigned int pin = val & 0xff; + unsigned int func = val >> 8; + + debug("%s pin %d func %d bias %d strength %d\n", + config->name, pin, func, bias, strength); + + rzn1_hw_set_lock(priv, LOCK_ALL, LOCK_ALL); + rzn1_set_hw_pin_func(priv, pin, func); + rzn1_pinconf_set(priv, pin, bias, strength); + rzn1_hw_set_lock(priv, LOCK_ALL, 0); + } + + return 0; +} + +static struct pinctrl_ops rzn1_pinctrl_ops = { + .set_state = rzn1_pinctrl_set_state, +}; + +static int rzn1_pinctrl_probe(struct udevice *dev) +{ + struct rzn1_pinctrl_priv *priv = dev_get_priv(dev); + ofnode node = dev_ofnode(dev); + int ret; + + ret = regmap_init_mem(node, &priv->regmap); + if (ret) + return ret; + + priv->lev1_protect_phys = (u32)regmap_get_range(priv->regmap, 0) + + offsetof(struct rzn1_pinctrl_regs, status_protect); + priv->lev2_protect_phys = (u32)regmap_get_range(priv->regmap, 1) + + offsetof(struct rzn1_pinctrl_regs, status_protect); + + return 0; +} + +static const struct udevice_id rzn1_pinctrl_ids[] = { + { .compatible = "renesas,rzn1-pinctrl", }, + { }, +}; + +U_BOOT_DRIVER(pinctrl_rzn1) = { + .name = "rzn1-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rzn1_pinctrl_ids, + .priv_auto = sizeof(struct rzn1_pinctrl_priv), + .ops = &rzn1_pinctrl_ops, + .probe = rzn1_pinctrl_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 1acf212f87..bf99964577 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -108,6 +108,7 @@ config IMXRT_SDRAM This driver is for the sdram memory interface with the SEMC. source "drivers/ram/aspeed/Kconfig" +source "drivers/ram/cadence/Kconfig" source "drivers/ram/rockchip/Kconfig" source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 2b9429cfee..6eb1a24135 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -24,3 +24,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/ endif obj-$(CONFIG_ARCH_OCTEON) += octeon/ + +obj-$(CONFIG_ARCH_RMOBILE) += renesas/ +obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ diff --git a/drivers/ram/cadence/Kconfig b/drivers/ram/cadence/Kconfig new file mode 100644 index 0000000000..2d5469cb8e --- /dev/null +++ b/drivers/ram/cadence/Kconfig @@ -0,0 +1,12 @@ +if RAM || SPL_RAM + +config CADENCE_DDR_CTRL + bool "Enable Cadence DDR controller" + depends on DM + help + Enable support for Cadence DDR controller, as found on + the Renesas RZ/N1 SoC. This controller has a large number + of registers which need to be programmed, mostly using values + obtained from Denali SOMA files via a TCL script. + +endif diff --git a/drivers/ram/cadence/Makefile b/drivers/ram/cadence/Makefile new file mode 100644 index 0000000000..b4226cf6f2 --- /dev/null +++ b/drivers/ram/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_CADENCE_DDR_CTRL) += ddr_ctrl.o diff --git a/drivers/ram/cadence/ddr_ctrl.c b/drivers/ram/cadence/ddr_ctrl.c new file mode 100644 index 0000000000..3e5959a84a --- /dev/null +++ b/drivers/ram/cadence/ddr_ctrl.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +/* + * The Cadence DDR Controller has a huge number of registers that principally + * cover two aspects, DDR specific timing information and AXI bus interfacing. + * Cadence's TCL script generates all of the register values for specific + * DDR devices operating at a specific frequency. The TCL script uses Denali + * SOMA files as inputs. The tool also generates the AXI bus register values as + * well, however this driver assumes that users will want to modifiy these to + * meet a specific application's needs. + * Therefore, this driver is passed two arrays containing register values for + * the DDR device specific information, and explicity sets the AXI registers. + * + * AXI bus interfacing: + * The controller has four AXI slaves connections, and each of these can be + * programmed to accept requests from specific AXI masters (using their IDs). + * The regions of DDR that can be accessed by each AXI slave can be set such + * as to isolate DDR used by one AXI master from another. Further, the maximum + * bandwidth allocated to each AXI slave can be set. + */ + +#include <common.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <asm/io.h> +#include <wait_bit.h> +#include <renesas/ddr_ctrl.h> + +/* avoid warning for real pr_debug in <linux/printk.h> */ +#ifdef pr_debug +#undef pr_debug +#endif + +#ifdef DEBUG + #define pr_debug(fmt, args...) printf(fmt, ##args) + #define pr_debug2(fmt, args...) printf(fmt, ##args) +#else + #define pr_debug(fmt, args...) + #define pr_debug2(fmt, args...) +#endif + +#define DDR_NR_AXI_PORTS 4 +#define DDR_NR_ENTRIES 16 + +#define DDR_START_REG (0) /* DENALI_CTL_00 */ +#define DDR_CS0_MR1_REG (32 * 4) /* DENALI_CTL_32 */ +#define DDR_CS0_MR2_REG (32 * 4 + 2) /* DENALI_CTL_32 */ +#define DDR_CS1_MR1_REG (34 * 4 + 2) /* DENALI_CTL_34 */ +#define DDR_CS1_MR2_REG (35 * 4) /* DENALI_CTL_35 */ +#define DDR_ECC_ENABLE_REG (36 * 4 + 2) /* DENALI_CTL_36 */ +#define DDR_ECC_DISABLE_W_UC_ERR_REG (37 * 4 + 2) /* DENALI_CTL_37 */ +#define DDR_HALF_DATAPATH_REG (54 * 4) /* DENALI_CTL_54 */ +#define DDR_INTERRUPT_STATUS (56 * 4) /* DENALI_CTL_56 */ +#define DDR_INTERRUPT_ACK (57 * 4) /* DENALI_CTL_57 */ +#define DDR_INTERRUPT_MASK (58 * 4) /* DENALI_CTL_58 */ +#define DDR_CS0_ODT_MAP_REG (62 * 4 + 2) /* DENALI_CTL_62 */ +#define DDR_CS1_ODT_MAP_REG (63 * 4) /* DENALI_CTL_63 */ +#define DDR_ODT_TODTL_2CMD (63 * 4 + 2) /* DENALI_CTL_63 */ +#define DDR_ODT_TODTH_WR (63 * 4 + 3) /* DENALI_CTL_63 */ +#define DDR_ODT_TODTH_RD (64 * 4 + 0) /* DENALI_CTL_64 */ +#define DDR_ODT_EN (64 * 4 + 1) /* DENALI_CTL_64 */ +#define DDR_ODT_WR_TO_ODTH (64 * 4 + 2) /* DENALI_CTL_64 */ +#define DDR_ODT_RD_TO_ODTH (64 * 4 + 3) /* DENALI_CTL_64 */ +#define DDR_DIFF_CS_DELAY_REG (66 * 4) /* DENALI_CTL_66 */ +#define DDR_SAME_CS_DELAY_REG (67 * 4) /* DENALI_CTL_67 */ +#define DDR_RW_PRIORITY_REGS (87 * 4 + 2) /* DENALI_CTL_87 */ +#define DDR_RW_FIFO_TYPE_REGS (88 * 4) /* DENALI_CTL_88 */ +#define DDR_AXI_PORT_PROT_ENABLE_REG (90 * 4 + 3) /* DENALI_CTL_90 */ +#define DDR_ADDR_RANGE_REGS (91 * 4) /* DENALI_CTL_91 */ +#define DDR_RANGE_PROT_REGS (218 * 4 + 2) /* DENALI_CTL_218 */ +#define DDR_ARB_CMD_Q_THRESHOLD_REG (346 * 4 + 2) /* DENALI_CTL_346 */ +#define DDR_AXI_PORT_BANDWIDTH_REG (346 * 4 + 3) /* DENALI_CTL_346 */ +#define DDR_OPT_RMODW_REG (372 * 4 + 3) /* DENALI_CTL_372 */ + +static void ddrc_writeb(u8 val, void *p) +{ + pr_debug2("DDR: %p = 0x%02x\n", p, val); + writeb(val, p); +} + +static void ddrc_writew(u16 val, void *p) +{ + pr_debug2("DDR: %p = 0x%04x\n", p, val); + writew(val, p); +} + +static void ddrc_writel(u32 val, void *p) +{ + pr_debug2("DDR: %p = 0x%08x\n", p, val); + writel(val, p); +} + +void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength) +{ + void *reg; + u16 tmp; + + if (cs == 0) + reg = (u8 *)base + DDR_CS0_MR1_REG; + else + reg = (u8 *)base + DDR_CS1_MR1_REG; + + tmp = readw(reg); + + tmp &= ~MODE_REGISTER_MASK; + tmp |= MODE_REGISTER_MR1; + + tmp &= ~MR1_ODT_IMPEDANCE_MASK; + tmp |= odt_impedance; + + tmp &= ~MR1_DRIVE_STRENGTH_MASK; + tmp |= drive_strength; + + writew(tmp, reg); +} + +void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp) +{ + void *reg; + u16 tmp; + + if (cs == 0) + reg = (u8 *)base + DDR_CS0_MR2_REG; + else + reg = (u8 *)base + DDR_CS1_MR2_REG; + + tmp = readw(reg); + + tmp &= ~MODE_REGISTER_MASK; + tmp |= MODE_REGISTER_MR2; + + tmp &= ~MR2_DYNAMIC_ODT_MASK; + tmp |= dynamic_odt; + + tmp &= ~MR2_SELF_REFRESH_TEMP_MASK; + tmp |= self_refresh_temp; + + writew(tmp, reg); +} + +void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map) +{ + void *reg; + + if (cs == 0) + reg = (u8 *)base + DDR_CS0_ODT_MAP_REG; + else + reg = (u8 *)base + DDR_CS1_ODT_MAP_REG; + + writew(odt_map, reg); +} + +void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD, + u8 WR_TO_ODTH, u8 RD_TO_ODTH) +{ + writeb(TODTL_2CMD, (u8 *)base + DDR_ODT_TODTL_2CMD); + writeb(TODTH_WR, (u8 *)base + DDR_ODT_TODTH_WR); + writeb(TODTH_RD, (u8 *)base + DDR_ODT_TODTH_RD); + writeb(1, (u8 *)base + DDR_ODT_EN); + writeb(WR_TO_ODTH, (u8 *)base + DDR_ODT_WR_TO_ODTH); + writeb(RD_TO_ODTH, (u8 *)base + DDR_ODT_RD_TO_ODTH); +} + +void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w) +{ + u32 val = (w2w << 24) | (w2r << 16) | (r2w << 8) | r2r; + + writel(val, (u8 *)base + DDR_SAME_CS_DELAY_REG); +} + +void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w) +{ + u32 val = (w2w << 24) | (w2r << 16) | (r2w << 8) | r2r; + + writel(val, (u8 *)base + DDR_DIFF_CS_DELAY_REG); +} + +void cdns_ddr_set_port_rw_priority(void *base, int port, + u8 read_pri, u8 write_pri) +{ + u8 *reg8 = (u8 *)base + DDR_RW_PRIORITY_REGS; + + reg8 += (port * 3); + pr_debug("%s port %d (reg8=%p, DENALI_CTL_%d)\n", + __func__, port, reg8, (reg8 - (u8 *)base) / 4); + + ddrc_writeb(read_pri, reg8++); + ddrc_writeb(write_pri, reg8++); +} + +/* The DDR Controller has 16 entries. Each entry can specify an allowed address + * range (with 16KB resolution) for one of the 4 AXI slave ports. + */ +void cdns_ddr_enable_port_addr_range(void *base, int port, int entry, + u32 addr_start, u32 size) +{ + u32 addr_end; + u32 *reg32 = (u32 *)((u8 *)base + DDR_ADDR_RANGE_REGS); + u32 tmp; + + reg32 += (port * DDR_NR_ENTRIES * 2); + reg32 += (entry * 2); + pr_debug("%s port %d, entry %d (reg32=%p, DENALI_CTL_%d)\n", + __func__, port, entry, reg32, ((u8 *)reg32 - (u8 *)base) / 4); + + /* These registers represent 16KB address blocks */ + addr_start /= SZ_16K; + size /= SZ_16K; + if (size) + addr_end = addr_start + size - 1; + else + addr_end = addr_start; + + ddrc_writel(addr_start, reg32++); + + /* + * end_addr: Ensure we only set the bottom 18-bits as DENALI_CTL_218 + * also contains the AXI0 range protection bits. + */ + tmp = readl(reg32); + tmp &= ~(BIT(18) - 1); + tmp |= addr_end; + ddrc_writel(tmp, reg32); +} + +void cdns_ddr_enable_addr_range(void *base, int entry, + u32 addr_start, u32 size) +{ + int axi; + + for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) + cdns_ddr_enable_port_addr_range(base, axi, entry, + addr_start, size); +} + +void cdns_ddr_enable_port_prot(void *base, int port, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup) +{ + /* + * Technically, the offset here points to the byte before the start of + * the range protection registers. However, all entries consist of 8 + * bytes, except the first one (which is missing a padding byte) so we + * work around that subtlely. + */ + u8 *reg8 = (u8 *)base + DDR_RANGE_PROT_REGS; + + reg8 += (port * DDR_NR_ENTRIES * 8); + reg8 += (entry * 8); + pr_debug("%s port %d, entry %d (reg8=%p, DENALI_CTL_%d)\n", + __func__, port, entry, reg8, (reg8 - (u8 *)base) / 4); + + if (port == 0 && entry == 0) + ddrc_writeb(range_protection_bits, reg8 + 1); + else + ddrc_writeb(range_protection_bits, reg8); + + ddrc_writew(range_RID_check_bits, reg8 + 2); + ddrc_writew(range_WID_check_bits, reg8 + 4); + ddrc_writeb(range_RID_check_bits_ID_lookup, reg8 + 6); + ddrc_writeb(range_WID_check_bits_ID_lookup, reg8 + 7); +} + +void cdns_ddr_enable_prot(void *base, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup) +{ + int axi; + + for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) + cdns_ddr_enable_port_prot(base, axi, entry, + range_protection_bits, + range_RID_check_bits, + range_WID_check_bits, + range_RID_check_bits_ID_lookup, + range_WID_check_bits_ID_lookup); +} + +void cdns_ddr_set_port_bandwidth(void *base, int port, + u8 max_percent, u8 overflow_ok) +{ + u8 *reg8 = (u8 *)base + DDR_AXI_PORT_BANDWIDTH_REG; + + reg8 += (port * 3); + pr_debug("%s port %d, (reg8=%p, DENALI_CTL_%d)\n", + __func__, port, reg8, (reg8 - (u8 *)base) / 4); + + ddrc_writeb(max_percent, reg8++); /* Maximum bandwidth percentage */ + ddrc_writeb(overflow_ok, reg8++); /* Bandwidth overflow allowed */ +} + +void cdns_ddr_ctrl_init(void *ddr_ctrl_basex, int async, + const u32 *reg0, const u32 *reg350, + u32 ddr_start_addr, u32 ddr_size, + int enable_ecc, int enable_8bit) +{ + int i, axi, entry; + u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex; + u8 *base8 = (u8 *)ddr_ctrl_basex; + + ddrc_writel(*reg0, ddr_ctrl_base + 0); + /* 1 to 6 are read only */ + for (i = 7; i <= 26; i++) + ddrc_writel(*(reg0 + i), ddr_ctrl_base + i); + /* 27 to 29 are not changed */ + for (i = 30; i <= 87; i++) + ddrc_writel(*(reg0 + i), ddr_ctrl_base + i); + + /* Enable/disable ECC */ + if (enable_ecc) { + pr_debug("%s enabling ECC\n", __func__); + ddrc_writeb(1, base8 + DDR_ECC_ENABLE_REG); + } else { + ddrc_writeb(0, base8 + DDR_ECC_ENABLE_REG); + } + + /* ECC: Disable corruption for read/modify/write operations */ + ddrc_writeb(1, base8 + DDR_ECC_DISABLE_W_UC_ERR_REG); + + /* Set 8/16-bit data width using reduce bit (enable half datapath)*/ + if (enable_8bit) { + pr_debug("%s using 8-bit data\n", __func__); + ddrc_writeb(1, base8 + DDR_HALF_DATAPATH_REG); + } else { + ddrc_writeb(0, base8 + DDR_HALF_DATAPATH_REG); + } + + /* Threshold for command queue */ + ddrc_writeb(4, base8 + DDR_ARB_CMD_Q_THRESHOLD_REG); + + /* AXI port protection => enable */ + ddrc_writeb(0x01, base8 + DDR_AXI_PORT_PROT_ENABLE_REG); + + /* Set port interface type, default port priority and bandwidths */ + for (axi = 0; axi < DDR_NR_AXI_PORTS; axi++) { + /* port interface type: synchronous or asynchronous AXI clock */ + u8 *fifo_reg = base8 + DDR_RW_FIFO_TYPE_REGS + (axi * 3); + + if (async) + ddrc_writeb(0, fifo_reg); + else + ddrc_writeb(3, fifo_reg); + + /* R/W priorities */ + cdns_ddr_set_port_rw_priority(ddr_ctrl_base, axi, 2, 2); + + /* AXI bandwidth */ + cdns_ddr_set_port_bandwidth(ddr_ctrl_base, axi, 50, 1); + } + + /* + * The hardware requires that the valid address ranges must not overlap. + * So, we initialise all address ranges to be above the DDR, length 0. + */ + for (entry = 0; entry < DDR_NR_ENTRIES; entry++) + cdns_ddr_enable_addr_range(ddr_ctrl_base, entry, + ddr_start_addr + ddr_size, 0); + + for (i = 350; i <= 374; i++) + ddrc_writel(*(reg350 - 350 + i), ddr_ctrl_base + i); + + /* Disable optimised read-modify-write logic */ + ddrc_writeb(0, base8 + DDR_OPT_RMODW_REG); + + /* + * Disable all interrupts, we are not handling them. + * For detail of the interrupt mask, ack and status bits, see the + * manual's description of the 'int_status' parameter. + */ + ddrc_writel(0, base8 + DDR_INTERRUPT_MASK); + + /* + * Default settings to enable full access to the entire DDR. + * Users can set different ranges and access rights by calling these + * functions before calling cdns_ddr_ctrl_start(). + */ + cdns_ddr_enable_addr_range(ddr_ctrl_base, 0, + ddr_start_addr, ddr_size); + cdns_ddr_enable_prot(ddr_ctrl_base, 0, CDNS_DDR_RANGE_PROT_BITS_FULL, + 0xffff, 0xffff, 0x0f, 0x0f); +} + +void cdns_ddr_ctrl_start(void *ddr_ctrl_basex) +{ + u32 *ddr_ctrl_base = (u32 *)ddr_ctrl_basex; + u8 *base8 = (u8 *)ddr_ctrl_basex; + + /* Start */ + ddrc_writeb(1, base8 + DDR_START_REG); + + /* Wait for controller to be ready (interrupt status) */ + wait_for_bit_le32(base8 + DDR_INTERRUPT_STATUS, 0x100, true, 1000, false); + + /* clear all interrupts */ + ddrc_writel(~0, base8 + DDR_INTERRUPT_ACK); + + /* Step 19 Wait 500us from MRESETB=1 */ + udelay(500); + + /* Step 20 tCKSRX wait (From supply stable clock for MCK) */ + /* DENALI_CTL_19 TREF_ENABLE=0x1(=1), AREFRESH=0x1(=1) */ + ddrc_writel(0x01000100, ddr_ctrl_base + 19); +} diff --git a/drivers/ram/renesas/Makefile b/drivers/ram/renesas/Makefile new file mode 100644 index 0000000000..705cc4b6fa --- /dev/null +++ b/drivers/ram/renesas/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_RZN1) += rzn1/ diff --git a/drivers/ram/renesas/rzn1/Makefile b/drivers/ram/renesas/rzn1/Makefile new file mode 100644 index 0000000000..357c2a506e --- /dev/null +++ b/drivers/ram/renesas/rzn1/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += ddr_async.o diff --git a/drivers/ram/renesas/rzn1/ddr_async.c b/drivers/ram/renesas/rzn1/ddr_async.c new file mode 100644 index 0000000000..7a81497bc9 --- /dev/null +++ b/drivers/ram/renesas/rzn1/ddr_async.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * RZ/N1 DDR Controller initialisation + * + * The DDR Controller register values for a specific DDR device, mode and + * frequency are generated using a Cadence tool. + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <wait_bit.h> +#include <renesas/ddr_ctrl.h> + +void clk_rzn1_reset_state(struct clk *clk, int on); + +DECLARE_GLOBAL_DATA_PTR; + +struct cadence_ddr_info { + struct udevice *dev; + void __iomem *ddrc; + void __iomem *phy; + struct clk clk_ddrc; + struct clk hclk_ddrc; + struct regmap *syscon; + bool enable_ecc; + bool enable_8bit; + u32 ddr_size; + + /* These two used only during .probe */ + u32 *reg0; + u32 *reg350; +}; + +static inline u32 cadence_readl(void __iomem *addr, unsigned int offset) +{ + return readl(addr + offset); +} + +static inline void cadence_writel(void __iomem *addr, unsigned int offset, + u32 data) +{ + debug("%s: addr = 0x%p, value = 0x%08x\n", __func__, addr + offset, data); + writel(data, addr + offset); +} + +#define ddrc_readl(off) cadence_readl(priv->ddrc, off) +#define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val) + +#define phy_readl(off) cadence_readl(priv->phy, off) +#define phy_writel(val, off) cadence_writel(priv->phy, off, val) + +#define RZN1_DDR3_SINGLE_BANK 3 +#define RZN1_DDR3_DUAL_BANK 32 + +#define FUNCCTRL 0x00 +#define FUNCCTRL_MASKSDLOFS (0x18 << 16) +#define FUNCCTRL_DVDDQ_1_5V BIT(8) +#define FUNCCTRL_RESET_N BIT(0) +#define DLLCTRL 0x04 +#define DLLCTRL_ASDLLOCK BIT(26) +#define DLLCTRL_MFSL_500MHz (2 << 1) +#define DLLCTRL_MDLLSTBY BIT(0) +#define ZQCALCTRL 0x08 +#define ZQCALCTRL_ZQCALEND BIT(30) +#define ZQCALCTRL_ZQCALRSTB BIT(0) +#define ZQODTCTRL 0x0c +#define RDCTRL 0x10 +#define RDTMG 0x14 +#define FIFOINIT 0x18 +#define FIFOINIT_RDPTINITEXE BIT(8) +#define FIFOINIT_WRPTINITEXE BIT(0) +#define OUTCTRL 0x1c +#define OUTCTRL_ADCMDOE BIT(0) +#define WLCTRL1 0x40 +#define WLCTRL1_WLSTR BIT(24) +#define DQCALOFS1 0xe8 + +/* DDR PHY setup */ +static void ddr_phy_init(struct cadence_ddr_info *priv, int ddr_type) +{ + u32 val; + + /* Disable DDR Controller clock and FlexWAY connection */ + clk_disable(&priv->hclk_ddrc); + clk_disable(&priv->clk_ddrc); + + clk_rzn1_reset_state(&priv->hclk_ddrc, 0); + clk_rzn1_reset_state(&priv->clk_ddrc, 0); + + /* Enable DDR Controller clock and FlexWAY connection */ + clk_enable(&priv->clk_ddrc); + clk_enable(&priv->hclk_ddrc); + + /* DDR PHY Soft reset assert */ + ddrc_writel(FUNCCTRL_MASKSDLOFS | FUNCCTRL_DVDDQ_1_5V, FUNCCTRL); + + clk_rzn1_reset_state(&priv->hclk_ddrc, 1); + clk_rzn1_reset_state(&priv->clk_ddrc, 1); + + /* DDR PHY setup */ + phy_writel(DLLCTRL_MFSL_500MHz | DLLCTRL_MDLLSTBY, DLLCTRL); + phy_writel(0x00000182, ZQCALCTRL); + if (ddr_type == RZN1_DDR3_DUAL_BANK) + phy_writel(0xAB330031, ZQODTCTRL); + else if (ddr_type == RZN1_DDR3_SINGLE_BANK) + phy_writel(0xAB320051, ZQODTCTRL); + else /* DDR2 */ + phy_writel(0xAB330071, ZQODTCTRL); + phy_writel(0xB545B544, RDCTRL); + phy_writel(0x000000B0, RDTMG); + phy_writel(0x020A0806, OUTCTRL); + if (ddr_type == RZN1_DDR3_DUAL_BANK) + phy_writel(0x80005556, WLCTRL1); + else + phy_writel(0x80005C5D, WLCTRL1); + phy_writel(0x00000101, FIFOINIT); + phy_writel(0x00004545, DQCALOFS1); + + /* Step 9 MDLL reset release */ + val = phy_readl(DLLCTRL); + val &= ~DLLCTRL_MDLLSTBY; + phy_writel(val, DLLCTRL); + + /* Step 12 Soft reset release */ + val = phy_readl(FUNCCTRL); + val |= FUNCCTRL_RESET_N; + phy_writel(val, FUNCCTRL); + + /* Step 13 FIFO pointer initialize */ + phy_writel(FIFOINIT_RDPTINITEXE | FIFOINIT_WRPTINITEXE, FIFOINIT); + + /* Step 14 Execute ZQ Calibration */ + val = phy_readl(ZQCALCTRL); + val |= ZQCALCTRL_ZQCALRSTB; + phy_writel(val, ZQCALCTRL); + + /* Step 15 Wait for 200us or more, or wait for DFIINITCOMPLETE to be "1" */ + wait_for_bit_le32(priv->phy + DLLCTRL, DLLCTRL_ASDLLOCK, true, 1, false); + wait_for_bit_le32(priv->phy + ZQCALCTRL, ZQCALCTRL_ZQCALEND, true, 1, false); + + /* Step 16 Enable Address and Command output */ + val = phy_readl(OUTCTRL); + val |= OUTCTRL_ADCMDOE; + phy_writel(val, OUTCTRL); + + /* Step 17 Wait for 200us or more(from MRESETB=0) */ + udelay(200); +} + +static void ddr_phy_enable_wl(struct cadence_ddr_info *priv) +{ + u32 val; + + /* Step 26 (Set Write Leveling) */ + val = phy_readl(WLCTRL1); + val |= WLCTRL1_WLSTR; + phy_writel(val, WLCTRL1); +} + +#define RZN1_V_DDR_BASE 0x80000000 /* RZ/N1D only */ + +static void rzn1_ddr3_single_bank(void *ddr_ctrl_base) +{ + /* CS0 */ + cdns_ddr_set_mr1(ddr_ctrl_base, 0, + MR1_ODT_IMPEDANCE_60_OHMS, + MR1_DRIVE_STRENGTH_40_OHMS); + cdns_ddr_set_mr2(ddr_ctrl_base, 0, + MR2_DYNAMIC_ODT_OFF, + MR2_SELF_REFRESH_TEMP_EXT); + + /* ODT_WR_MAP_CS0 = 1, ODT_RD_MAP_CS0 = 0 */ + cdns_ddr_set_odt_map(ddr_ctrl_base, 0, 0x0100); +} + +static int rzn1_dram_init(struct cadence_ddr_info *priv) +{ + u32 version; + u32 ddr_start_addr = 0; + + ddr_phy_init(priv, RZN1_DDR3_SINGLE_BANK); + + /* + * Override DDR PHY Interface (DFI) related settings + * DFI is the internal interface between the DDR controller and the DDR PHY. + * These settings are specific to the board and can't be known by the settings + * provided for each DDR model within the generated include. + */ + priv->reg350[351 - 350] = 0x001e0000; + priv->reg350[352 - 350] = 0x1e680000; + priv->reg350[353 - 350] = 0x02000020; + priv->reg350[354 - 350] = 0x02000200; + priv->reg350[355 - 350] = 0x00000c30; + priv->reg350[356 - 350] = 0x00009808; + priv->reg350[357 - 350] = 0x020a0706; + priv->reg350[372 - 350] = 0x01000000; + + /* + * On ES1.0 devices, the DDR start address that the DDR Controller sees + * is the physical address of the DDR. However, later devices changed it + * to be 0 in order to fix an issue with DDR out-of-range detection. + */ +#define RZN1_SYSCTRL_REG_VERSION 412 + regmap_read(priv->syscon, RZN1_SYSCTRL_REG_VERSION, &version); + if (version == 0x10) + ddr_start_addr = RZN1_V_DDR_BASE; + + if (priv->enable_ecc) + priv->ddr_size = priv->ddr_size / 2; + + /* DDR Controller is always in ASYNC mode */ + cdns_ddr_ctrl_init(priv->ddrc, 1, + priv->reg0, priv->reg350, + ddr_start_addr, priv->ddr_size, + priv->enable_ecc, priv->enable_8bit); + + rzn1_ddr3_single_bank(priv->ddrc); + cdns_ddr_set_diff_cs_delays(priv->ddrc, 2, 7, 2, 2); + cdns_ddr_set_same_cs_delays(priv->ddrc, 0, 7, 0, 0); + cdns_ddr_set_odt_times(priv->ddrc, 5, 6, 6, 0, 4); + cdns_ddr_ctrl_start(priv->ddrc); + + ddr_phy_enable_wl(priv); + + if (priv->enable_ecc) { + /* + * Any read before a write will trigger an ECC un-correctable error, + * causing a data abort. However, this is also true for any read with a + * size less than the AXI bus width. So, the only sensible solution is + * to write to all of DDR now and take the hit... + */ + memset((void *)RZN1_V_DDR_BASE, 0xff, priv->ddr_size); + } + + return 0; +} + +static int cadence_ddr_get_info(struct udevice *udev, struct ram_info *info) +{ + info->base = 0; + info->size = gd->ram_size; + + return 0; +} + +static struct ram_ops cadence_ddr_ops = { + .get_info = cadence_ddr_get_info, +}; + +static int cadence_ddr_test(long *base, long maxsize) +{ + volatile long *addr = base; + long cnt; + + maxsize /= sizeof(long); + + for (cnt = 1; cnt <= maxsize; cnt <<= 1) { + addr[cnt - 1] = ~cnt; + } + + for (cnt = 1; cnt <= maxsize; cnt <<= 1) { + if (addr[cnt - 1] != ~cnt) { + return 0; + } + } + + return 1; +} + +static int cadence_ddr_probe(struct udevice *dev) +{ + struct cadence_ddr_info *priv = dev_get_priv(dev); + ofnode subnode; + int ret; + + priv->dev = dev; + + priv->ddrc = dev_remap_addr_name(dev, "ddrc"); + if (!priv->ddrc) { + dev_err(dev, "No reg property for Cadence DDR CTRL\n"); + return -EINVAL; + } + + priv->phy = dev_remap_addr_name(dev, "phy"); + if (!priv->phy) { + dev_err(dev, "No reg property for Cadence DDR PHY\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev, "clk_ddrc", &priv->clk_ddrc); + if (ret) { + dev_err(dev, "No clock for Cadence DDR\n"); + return ret; + } + + ret = clk_get_by_name(dev, "hclk_ddrc", &priv->hclk_ddrc); + if (ret) { + dev_err(dev, "No HCLK for Cadence DDR\n"); + return ret; + } + + priv->syscon = syscon_regmap_lookup_by_phandle(dev, "syscon"); + if (IS_ERR(priv->syscon)) { + dev_err(dev, "No syscon node found\n"); + return PTR_ERR(priv->syscon); + } + + priv->enable_ecc = dev_read_bool(dev, "enable-ecc"); + priv->enable_8bit = dev_read_bool(dev, "enable-8bit"); + + priv->reg0 = malloc(88 * sizeof(u32)); + priv->reg350 = malloc(25 * sizeof(u32)); + if (!priv->reg0 || !priv->reg350) + panic("malloc failure\n"); + + /* There may be multiple DDR configurations to try */ + dev_for_each_subnode(subnode, dev) { + ret = ofnode_read_u32(subnode, "size", &priv->ddr_size); + if (ret) { + dev_err(dev, "No size for Cadence DDR\n"); + continue; + } + + ret = ofnode_read_u32_array(subnode, "cadence,ctl-000", priv->reg0, 88); + if (ret) { + dev_err(dev, "No cadence,ctl-000\n"); + continue; + } + + ret = ofnode_read_u32_array(subnode, "cadence,ctl-350", priv->reg350, 25); + if (ret) { + dev_err(dev, "No cadence,ctl-350\n"); + continue; + } + + if (rzn1_dram_init(priv)) + continue; + + if (cadence_ddr_test((long *)RZN1_V_DDR_BASE, priv->ddr_size)) { + gd->ram_base = RZN1_V_DDR_BASE; + gd->ram_size = priv->ddr_size; + break; + } + } + + if (!priv->ddr_size) + panic("No valid DDR to start"); + + free(priv->reg350); + free(priv->reg0); + + return 0; +} + +static const struct udevice_id cadence_ddr_ids[] = { + { .compatible = "cadence,ddr-ctrl" }, + { } +}; + +U_BOOT_DRIVER(cadence_ddr) = { + .name = "cadence_ddr", + .id = UCLASS_RAM, + .of_match = cadence_ddr_ids, + .ops = &cadence_ddr_ops, + .probe = cadence_ddr_probe, + .priv_auto = sizeof(struct cadence_ddr_info), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 00e3ffcd1d..d1d4048966 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -676,7 +676,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) { int op_len, pos = 0, ret, i; - u32 dummy_bytes = 0; unsigned int flag = 0; const u8 *tx_buf = NULL; u8 *rx_buf = NULL; @@ -689,11 +688,6 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, } op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes; - if (op->dummy.nbytes) { - op_len = op->cmd.nbytes + op->addr.nbytes + - op->dummy.nbytes / op->dummy.buswidth; - dummy_bytes = op->dummy.nbytes / op->dummy.buswidth; - } u8 op_buf[op_len]; @@ -707,8 +701,8 @@ static int zynq_qspi_exec_op(struct spi_slave *slave, pos += op->addr.nbytes; } - if (dummy_bytes) - memset(op_buf + pos, 0xff, dummy_bytes); + if (op->dummy.nbytes) + memset(op_buf + pos, 0xff, op->dummy.nbytes); /* 1st transfer: opcode + address + dummy cycles */ /* Make sure to set END bit if no tx or rx data messages follow */ diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 28f7ca9654..02c0138a20 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -18,7 +18,6 @@ #include <dm/lists.h> #include <dm/uclass-internal.h> -extern bool usb_started; /* flag for the started/stopped USB status */ static bool asynch_allowed; struct usb_uclass_priv { diff --git a/drivers/usb/host/usb_bootdev.c b/drivers/usb/host/usb_bootdev.c index 32919f9928..06e8f61aa1 100644 --- a/drivers/usb/host/usb_bootdev.c +++ b/drivers/usb/host/usb_bootdev.c @@ -22,6 +22,9 @@ static int usb_bootdev_bind(struct udevice *dev) static int usb_bootdev_hunt(struct bootdev_hunter *info, bool show) { + if (usb_started) + return 0; + return usb_init(); } diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fcc0e85d2e..1e2f4e6de4 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -962,7 +962,7 @@ config BMP_32BPP endif # VIDEO config SPL_VIDEO - bool "Enable driver model support for LCD/video" + bool "Enable driver model support for LCD/video in SPL" depends on SPL_DM help The video subsystem adds a small amount of overhead to the image. diff --git a/include/bootmeth.h b/include/bootmeth.h index b12dfd42c9..c3df9702e8 100644 --- a/include/bootmeth.h +++ b/include/bootmeth.h @@ -255,7 +255,7 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global); * This selects the ordering to use for bootmeths * * @order_str: String containing the ordering. This is a comma-separate list of - * bootmeth-device names, e.g. "syslinux,efi". If empty then a default ordering + * bootmeth-device names, e.g. "extlinux,efi". If empty then a default ordering * is used, based on the sequence number of devices (i.e. using aliases) * Return: 0 if OK, -ENODEV if an unknown bootmeth is mentioned, -ENOMEM if * out of memory, -ENOENT if there are no bootmeth devices diff --git a/include/configs/rzn1-snarc.h b/include/configs/rzn1-snarc.h new file mode 100644 index 0000000000..9fee2ece54 --- /dev/null +++ b/include/configs/rzn1-snarc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Schneider RZ/N1 board + */ + +#ifndef __RZN1_SNARC_H +#define __RZN1_SNARC_H + +/* Internal RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE (1 * 1024 * 1024) + +#endif /* __RZN1_SNARC_H */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h new file mode 100644 index 0000000000..d9d7b8b4f4 --- /dev/null +++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R9A06G032 sysctrl IDs + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> + */ + +#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ +#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ + +#define R9A06G032_CLK_PLL_USB 1 +#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ +#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ +#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ +#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ +#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ +#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ +#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ +#define R9A06G032_CLK_25_PG4 26 +#define R9A06G032_CLK_25_PG5 27 +#define R9A06G032_CLK_25_PG6 28 +#define R9A06G032_CLK_25_PG7 29 +#define R9A06G032_CLK_25_PG8 30 +#define R9A06G032_CLK_ADC 31 +#define R9A06G032_CLK_ECAT100 32 +#define R9A06G032_CLK_HSR100 33 +#define R9A06G032_CLK_I2C0 34 +#define R9A06G032_CLK_I2C1 35 +#define R9A06G032_CLK_MII_REF 36 +#define R9A06G032_CLK_NAND 37 +#define R9A06G032_CLK_NOUSBP2_PG6 38 +#define R9A06G032_CLK_P1_PG2 39 +#define R9A06G032_CLK_P1_PG3 40 +#define R9A06G032_CLK_P1_PG4 41 +#define R9A06G032_CLK_P4_PG3 42 +#define R9A06G032_CLK_P4_PG4 43 +#define R9A06G032_CLK_P6_PG1 44 +#define R9A06G032_CLK_P6_PG2 45 +#define R9A06G032_CLK_P6_PG3 46 +#define R9A06G032_CLK_P6_PG4 47 +#define R9A06G032_CLK_PCI_USB 48 +#define R9A06G032_CLK_QSPI0 49 +#define R9A06G032_CLK_QSPI1 50 +#define R9A06G032_CLK_RGMII_REF 51 +#define R9A06G032_CLK_RMII_REF 52 +#define R9A06G032_CLK_SDIO0 53 +#define R9A06G032_CLK_SDIO1 54 +#define R9A06G032_CLK_SERCOS100 55 +#define R9A06G032_CLK_SLCD 56 +#define R9A06G032_CLK_SPI0 57 +#define R9A06G032_CLK_SPI1 58 +#define R9A06G032_CLK_SPI2 59 +#define R9A06G032_CLK_SPI3 60 +#define R9A06G032_CLK_SPI4 61 +#define R9A06G032_CLK_SPI5 62 +#define R9A06G032_CLK_SWITCH 63 +#define R9A06G032_HCLK_ECAT125 65 +#define R9A06G032_HCLK_PINCONFIG 66 +#define R9A06G032_HCLK_SERCOS 67 +#define R9A06G032_HCLK_SGPIO2 68 +#define R9A06G032_HCLK_SGPIO3 69 +#define R9A06G032_HCLK_SGPIO4 70 +#define R9A06G032_HCLK_TIMER0 71 +#define R9A06G032_HCLK_TIMER1 72 +#define R9A06G032_HCLK_USBF 73 +#define R9A06G032_HCLK_USBH 74 +#define R9A06G032_HCLK_USBPM 75 +#define R9A06G032_CLK_48_PG_F 76 +#define R9A06G032_CLK_48_PG4 77 +#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ +#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ +#define R9A06G032_HCLK_CAN0 85 +#define R9A06G032_HCLK_CAN1 86 +#define R9A06G032_HCLK_DELTASIGMA 87 +#define R9A06G032_HCLK_PWMPTO 88 +#define R9A06G032_HCLK_RSV 89 +#define R9A06G032_HCLK_SGPIO0 90 +#define R9A06G032_HCLK_SGPIO1 91 +#define R9A06G032_RTOS_MDC 92 +#define R9A06G032_CLK_CM3 93 +#define R9A06G032_CLK_DDRC 94 +#define R9A06G032_CLK_ECAT25 95 +#define R9A06G032_CLK_HSR50 96 +#define R9A06G032_CLK_HW_RTOS 97 +#define R9A06G032_CLK_SERCOS50 98 +#define R9A06G032_HCLK_ADC 99 +#define R9A06G032_HCLK_CM3 100 +#define R9A06G032_HCLK_CRYPTO_EIP150 101 +#define R9A06G032_HCLK_CRYPTO_EIP93 102 +#define R9A06G032_HCLK_DDRC 103 +#define R9A06G032_HCLK_DMA0 104 +#define R9A06G032_HCLK_DMA1 105 +#define R9A06G032_HCLK_GMAC0 106 +#define R9A06G032_HCLK_GMAC1 107 +#define R9A06G032_HCLK_GPIO0 108 +#define R9A06G032_HCLK_GPIO1 109 +#define R9A06G032_HCLK_GPIO2 110 +#define R9A06G032_HCLK_HSR 111 +#define R9A06G032_HCLK_I2C0 112 +#define R9A06G032_HCLK_I2C1 113 +#define R9A06G032_HCLK_LCD 114 +#define R9A06G032_HCLK_MSEBI_M 115 +#define R9A06G032_HCLK_MSEBI_S 116 +#define R9A06G032_HCLK_NAND 117 +#define R9A06G032_HCLK_PG_I 118 +#define R9A06G032_HCLK_PG19 119 +#define R9A06G032_HCLK_PG20 120 +#define R9A06G032_HCLK_PG3 121 +#define R9A06G032_HCLK_PG4 122 +#define R9A06G032_HCLK_QSPI0 123 +#define R9A06G032_HCLK_QSPI1 124 +#define R9A06G032_HCLK_ROM 125 +#define R9A06G032_HCLK_RTC 126 +#define R9A06G032_HCLK_SDIO0 127 +#define R9A06G032_HCLK_SDIO1 128 +#define R9A06G032_HCLK_SEMAP 129 +#define R9A06G032_HCLK_SPI0 130 +#define R9A06G032_HCLK_SPI1 131 +#define R9A06G032_HCLK_SPI2 132 +#define R9A06G032_HCLK_SPI3 133 +#define R9A06G032_HCLK_SPI4 134 +#define R9A06G032_HCLK_SPI5 135 +#define R9A06G032_HCLK_SWITCH 136 +#define R9A06G032_HCLK_SWITCH_RG 137 +#define R9A06G032_HCLK_UART0 138 +#define R9A06G032_HCLK_UART1 139 +#define R9A06G032_HCLK_UART2 140 +#define R9A06G032_HCLK_UART3 141 +#define R9A06G032_HCLK_UART4 142 +#define R9A06G032_HCLK_UART5 143 +#define R9A06G032_HCLK_UART6 144 +#define R9A06G032_HCLK_UART7 145 +#define R9A06G032_CLK_UART0 146 +#define R9A06G032_CLK_UART1 147 +#define R9A06G032_CLK_UART2 148 +#define R9A06G032_CLK_UART3 149 +#define R9A06G032_CLK_UART4 150 +#define R9A06G032_CLK_UART5 151 +#define R9A06G032_CLK_UART6 152 +#define R9A06G032_CLK_UART7 153 + +#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/include/dt-bindings/pinctrl/rzn1-pinctrl.h b/include/dt-bindings/pinctrl/rzn1-pinctrl.h new file mode 100644 index 0000000000..21d6cc4d59 --- /dev/null +++ b/include/dt-bindings/pinctrl/rzn1-pinctrl.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/N1 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_RZN1_PINCTRL_H +#define __DT_BINDINGS_RZN1_PINCTRL_H + +#define RZN1_PINMUX(_gpio, _func) \ + (((_func) << 8) | (_gpio)) + +/* + * Given the different levels of muxing on the SoC, it was decided to + * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO + * muxes are all represented by one single value. + * + * You can derive the hardware value pretty easily too, as + * 0...9 are Level 1 + * 10...71 are Level 2. The Level 2 mux will be set to this + * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be + * set accordingly. + * 72...103 are for the 2 MDIO muxes. + */ +#define RZN1_FUNC_HIGHZ 0 +#define RZN1_FUNC_0L 1 +#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 +#define RZN1_FUNC_CLK_ETH_NAND 3 +#define RZN1_FUNC_QSPI 4 +#define RZN1_FUNC_SDIO 5 +#define RZN1_FUNC_LCD 6 +#define RZN1_FUNC_LCD_E 7 +#define RZN1_FUNC_MSEBIM 8 +#define RZN1_FUNC_MSEBIS 9 +#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ + +#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) +#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) +#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) +#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) +#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) +#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) +#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) +#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) +#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) +#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) +#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) +#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) +#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) +#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) +#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) +#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) +#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) +#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) +#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) +#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) +#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) +#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) +#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) +#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) +#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) +#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) +#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) +#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) +#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) +#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) +#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) +#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) +#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) +#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) +#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) +#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) +#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) +#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) +#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) +#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) +#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) +#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) +#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) +#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) +#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) +#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) +#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) +#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) +#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) +#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) +#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) +#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) +#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) +#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) +#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) +#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) +#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) +#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) +#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) +#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) +#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) +#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) + +#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) + +/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ +#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) +#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) +#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) +#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) +#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) +#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) +#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) +#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) +/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) +#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) +#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) +#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) +#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) +#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) +#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) +#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) + +/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ +#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) +#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) +#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) +#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) +#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) +#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) +#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) +#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) +/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) +#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) +#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) +#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) +#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) +#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) +#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) +#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) + +#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) + +#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ diff --git a/include/env_default.h b/include/env_default.h index c0df39d62f..b16c22d5a2 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -10,9 +10,7 @@ #include <env_callback.h> #include <linux/stringify.h> -#ifndef USE_HOSTCC #include <generated/environment.h> -#endif #ifdef DEFAULT_ENV_INSTANCE_EMBEDDED env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { diff --git a/include/environment/ti/k3_rproc.env b/include/environment/ti/k3_rproc.env index 21dad7b241..87d9d76eba 100644 --- a/include/environment/ti/k3_rproc.env +++ b/include/environment/ti/k3_rproc.env @@ -7,14 +7,14 @@ boot_rprocs= rproc_load_and_boot_one= if load mmc ${bootpart} $loadaddr ${rproc_fw}; then if rproc load ${rproc_id} ${loadaddr} ${filesize}; then - rproc start ${rproc_id} + rproc start ${rproc_id}; fi; fi boot_rprocs_mmc= env set rproc_id; env set rproc_fw; for i in ${rproc_fw_binaries} ; do - if test -z ${rproc_id} ; then + if test -z "${rproc_id}" ; then env set rproc_id $i; else env set rproc_fw $i; diff --git a/include/distro.h b/include/extlinux.h index 2ee145871b..721ba46371 100644 --- a/include/distro.h +++ b/include/extlinux.h @@ -4,18 +4,18 @@ * Written by Simon Glass <sjg@chromium.org> */ -#ifndef __distro_h -#define __distro_h +#ifndef __extlinux_h +#define __extlinux_h -#define DISTRO_FNAME "extlinux/extlinux.conf" +#define EXTLINUX_FNAME "extlinux/extlinux.conf" /** - * struct distro_info - useful information for distro_getfile() + * struct extlinux_info - useful information for extlinux_getfile() * * @dev: bootmethod device being used to boot * @bflow: bootflow being booted */ -struct distro_info { +struct extlinux_info { struct udevice *dev; struct bootflow *bflow; struct cmd_tbl *cmdtp; diff --git a/include/flash.h b/include/flash.h index 95992fa689..3710a2731b 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,6 +46,7 @@ typedef struct { #ifdef CONFIG_CFI_FLASH /* DM-specific parts */ struct udevice *dev; phys_addr_t base; + phys_size_t addr_size; #endif } flash_info_t; diff --git a/include/image.h b/include/image.h index 456197d6fd..01a6787d21 100644 --- a/include/image.h +++ b/include/image.h @@ -230,6 +230,7 @@ enum image_type_t { IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */ IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */ IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ + IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/include/renesas/ddr_ctrl.h b/include/renesas/ddr_ctrl.h new file mode 100644 index 0000000000..77d7915b2b --- /dev/null +++ b/include/renesas/ddr_ctrl.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +#ifndef CADENCE_DDR_CTRL_H +#define CADENCE_DDR_CTRL_H + +enum cdns_ddr_range_prot { + CDNS_DDR_RANGE_PROT_BITS_PRIV_SECURE = 0, + CDNS_DDR_RANGE_PROT_BITS_SECURE = 1, + CDNS_DDR_RANGE_PROT_BITS_PRIV = 2, + CDNS_DDR_RANGE_PROT_BITS_FULL = 3, +}; + +/** + * Initialise the Cadence DDR Controller, but doesn't start it. + * + * It sets up the controller so that all 4 AXI slave ports allow access to all + * of the DDR with the same settings. This means that: + * - Full access permisions. + * - All read/write priorities are set to 2. + * - Bandwidth is set to 50%, overflow is allowed, i.e. it's a soft limit. + * If you want different properties for different ports and/or addr ranges, call + * the other functions before calling cdns_ddr_ctrl_start(). + * + * @ddr_ctrl_base Physical address of the DDR Controller. + * @async 0 if DDR clock is synchronous with the controller clock + * otherwise 1. + * @reg0 Pointer to array of 32-bit values to be written to registers + * 0 to 87. The values are generated by Cadence TCL scripts. + * @reg350 Pointer to array of 32-bit values to be written to registers + * 350 to 374. The values are generated by Cadence TCL scripts. + * @ddr_start_addr Physical address of the start of DDR. + * @ddr_size Size of the DDR in bytes. The controller will set the port + * protection range to match this size. + * @enable_ecc 0 to disable ECC, 1 to enable it. + * @enable_8bit 0 to use 16-bit bus width, 1 to use 8-bit bus width. + */ +void cdns_ddr_ctrl_init(void *ddr_ctrl_base, int async, + const u32 *reg0, const u32 *reg350, + u32 ddr_start_addr, u32 ddr_size, + int enable_ecc, int enable_8bit); + +/** + * Start the Cadence DDR Controller. + * + * @ddr_ctrl_base Physical address of the DDR Controller. + */ +void cdns_ddr_ctrl_start(void *ddr_ctrl_base); + +/** + * Set the priority for read and write operations for a specific AXI slave port. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @read_pri Priority for reads. Range is 0 to 3, where 0 is highest priority. + * @write_pri Priority for writes. Range is 0 to 3, where 0 is highest priority. + */ +void cdns_ddr_set_port_rw_priority(void *base, int port, + u8 read_pri, u8 write_pri); + +/** + * Specify address range for a protection entry, for a specific AXI slave port. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @entry The protection entry. Range is 0 to 15. + * @start_addr Physical of the address range, must be aligned to 16KB. + * @size Size of the address range, must be multiple of 16KB. + */ +void cdns_ddr_enable_port_addr_range(void *base, int port, int entry, + u32 addr_start, u32 size); + +/** + * Specify address range for a protection entry, for all AXI slave ports. + * + * @base Physical address of the DDR Controller. + * @entry The protection entry. Range is 0 to 15. + * @start_addr Physical of the address range, must be aligned to 16KB. + * @size Size of the address range, must be multiple of 16KB. + */ +void cdns_ddr_enable_addr_range(void *base, int entry, + u32 addr_start, u32 size); + +/** + * Specify protection entry details, for a specific AXI slave port. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @entry The protection entry. Range is 0 to 15. + */ +void cdns_ddr_enable_port_prot(void *base, int port, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup); + +/** + * Specify protection entry details, for all AXI slave ports. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @entry The protection entry. Range is 0 to 15. + */ +void cdns_ddr_enable_prot(void *base, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup); + +/** + * Specify bandwidth for each AXI port. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @max_percent 0 to 100. + */ +void cdns_ddr_set_port_bandwidth(void *base, int port, + u8 max_percent, u8 overflow_ok); + +/* Standard JEDEC registers */ +#define MODE_REGISTER_MASK (3 << 14) +#define MODE_REGISTER_MR0 (0 << 14) +#define MODE_REGISTER_MR1 (1 << 14) +#define MODE_REGISTER_MR2 (2 << 14) +#define MODE_REGISTER_MR3 (3 << 14) +#define MR1_DRIVE_STRENGTH_MASK ((1 << 5) | (1 << 1)) +#define MR1_DRIVE_STRENGTH_34_OHMS ((0 << 5) | (1 << 1)) +#define MR1_DRIVE_STRENGTH_40_OHMS ((0 << 5) | (0 << 1)) +#define MR1_ODT_IMPEDANCE_MASK ((1 << 9) | (1 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_60_OHMS ((0 << 9) | (0 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_120_OHMS ((0 << 9) | (1 << 6) | (0 << 2)) +#define MR1_ODT_IMPEDANCE_40_OHMS ((0 << 9) | (1 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_20_OHMS ((1 << 9) | (0 << 6) | (0 << 2)) +#define MR1_ODT_IMPEDANCE_30_OHMS ((1 << 9) | (0 << 6) | (1 << 2)) +#define MR2_DYNAMIC_ODT_MASK (3 << 9) +#define MR2_DYNAMIC_ODT_OFF (0 << 9) +#define MR2_SELF_REFRESH_TEMP_MASK (1 << 7) +#define MR2_SELF_REFRESH_TEMP_EXT (1 << 7) + +/** + * Set certain fields of the JEDEC MR1 register. + */ +void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength); + +/** + * Set certain fields of the JEDEC MR2 register. + */ +void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp); + +/** + * Set ODT map of the DDR Controller. + */ +void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map); + +/** + * Set ODT settings in the DDR Controller. + */ +void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD, + u8 WR_TO_ODTH, u8 RD_TO_ODTH); + +void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); +void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); + +#endif diff --git a/include/renesas/is43tr16256a_125k_CTL.h b/include/renesas/is43tr16256a_125k_CTL.h new file mode 100644 index 0000000000..fabc2c7b79 --- /dev/null +++ b/include/renesas/is43tr16256a_125k_CTL.h @@ -0,0 +1,419 @@ + +/* **************************************************************** + * CADENCE Copyright (c) 2001-2011 * + * Cadence Design Systems, Inc. * + * All rights reserved. * + * * + ****************************************************************** + * The values calculated from this script are meant to be * + * representative programmings. The values may not reflect the * + * actual required programming for production use. Please * + * closely review all programmed values for technical accuracy * + * before use in production parts. * + ****************************************************************** + * + * Module: regconfig.h + * Documentation: Register programming header file + * + ****************************************************************** + ****************************************************************** + * WARNING: This file was automatically generated. Manual + * editing may result in undetermined behavior. + ****************************************************************** + ******************************************************************/ +// REL: renesas.germany-LCES_DDR__2014-05-21 + +// ******************************************************************** +// Option: IP : IP Mode = CTL +// Option: BL : Burst Length = 8 +// Option: CL : CAS Latency = 8 +// Option: MHZ : Simulation MHz = 500 +// Option: AP : Auto Precharge Mode (0/1) = 0 +// Option: DLLBP : DLL Bypass Mode (0/1) = 1 +// Option: HALF : Half-Memory Support (0/1) = 0 +// Option: RDIMM : Registered Dimm Support (0/1) = 0 +// Option: AL : Additive Latency = 0 +// Option: RSV3 : Reserved (0) = 0 +// Option: TCK : Simulation period in ns = +// Option: RDDBIEN : Read DBI Enable (0/1) = 0 +// Option: SOMA : Memory-SOMA file(s) = is43tr16256a_125k_xml.soma +// ******************************************************************** +// Memory: is43tr16256a_125k_xml.soma +// ******************************************************************** + +#define DENALI_CTL_00_DATA 0x00000600 // VERSION:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x06 START:RW:0:1:=0x00 +#define DENALI_CTL_01_DATA 0x00000000 // READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00 +#define DENALI_CTL_02_DATA 0x00000000 // ASYNC_CDC_STAGES:RD:24:8:=0x00 WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00 +#define DENALI_CTL_03_DATA 0x00000000 // AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI0_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_04_DATA 0x00000000 // AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI1_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI1_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI1_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_05_DATA 0x00000000 // AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI2_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI2_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_06_DATA 0x00000000 // AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI3_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI3_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_07_DATA 0x00000005 // TINIT:RW:0:24:=0x000005 +#define DENALI_CTL_08_DATA 0x000186a0 // TRST_PWRON:RW:0:32:=0x000186a0 +#define DENALI_CTL_09_DATA 0x0003d090 // CKE_INACTIVE:RW:0:32:=0x0003d090 +#define DENALI_CTL_10_DATA 0x00000000 // TCPD:RW:8:16:=0x0000 INITAREF:RW:0:4:=0x00 +#define DENALI_CTL_11_DATA 0x10000200 // CASLAT_LIN:RW:24:6:=0x10 NO_CMD_INIT:RW:16:1:=0x00 TDLL:RW:0:16:=0x0200 +#define DENALI_CTL_12_DATA 0x04040006 // TCCD:RW:24:5:=0x04 TBST_INT_INTERVAL:RW:16:3:=0x04 ADDITIVE_LAT:RW:8:5:=0x00 WRLAT:RW:0:5:=0x06 +#define DENALI_CTL_13_DATA 0x04121904 // TWTR:RW:24:6:=0x04 TRAS_MIN:RW:16:8:=0x12 TRC:RW:8:8:=0x19 TRRD:RW:0:8:=0x04 +#define DENALI_CTL_14_DATA 0x04041407 // TMRD:RW:24:5:=0x04 TRTP:RW:16:4:=0x04 TFAW:RW:8:6:=0x14 TRP:RW:0:5:=0x07 +#define DENALI_CTL_15_DATA 0x00891c0c // TRAS_MAX:RW:8:17:=0x00891c TMOD:RW:0:8:=0x0c +#define DENALI_CTL_16_DATA 0x07000503 // TRCD:RW:24:8:=0x07 WRITEINTERP:RW:16:1:=0x00 TCKESR:RW:8:8:=0x05 TCKE:RW:0:3:=0x03 +#define DENALI_CTL_17_DATA 0x01010008 // TRAS_LOCKOUT:RW:24:1:=0x01 CONCURRENTAP:RW:16:1:=0x01 AP:RW:8:1:=0x00 TWR:RW:0:6:=0x08 +#define DENALI_CTL_18_DATA 0x0007030f // REG_DIMM_ENABLE:RW:24:1:=0x00 TRP_AB:RW:16:5:=0x07 BSTLEN:RW_D:8:3:=0x03 TDAL:RW:0:6:=0x0f +#define DENALI_CTL_19_DATA 0x01000000 // TREF_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:1:=0x00 AREFRESH:WR:8:1:=0x00 ADDRESS_MIRRORING:RW:0:2:=0x00 +#define DENALI_CTL_20_DATA 0x0f340082 // TREF:RW:16:14:=0x0f34 TRFC:RW:0:10:=0x0082 +#define DENALI_CTL_21_DATA 0x00000005 // TREF_INTERVAL:RW:0:14:=0x0005 +#define DENALI_CTL_22_DATA 0x000c0003 // TXPDLL:RW:16:16:=0x000c TPDEX:RW:0:16:=0x0003 +#define DENALI_CTL_23_DATA 0x00000000 // TXARDS:RW:16:16:=0x0000 TXARD:RW:0:16:=0x0000 +#define DENALI_CTL_24_DATA 0x00870200 // TXSNR:RW:16:16:=0x0087 TXSR:RW:0:16:=0x0200 +#define DENALI_CTL_25_DATA 0x00010000 // CKE_DELAY:RW:24:3:=0x00 ENABLE_QUICK_SREFRESH:RW:16:1:=0x01 SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00 PWRUP_SREFRESH_EXIT:RW:0:1:=0x00 +#define DENALI_CTL_26_DATA 0x00050500 // LP_CMD:WR:24:8:=0x00 CKSRX:RW:16:8:=0x05 CKSRE:RW:8:8:=0x05 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00 +#define DENALI_CTL_27_DATA 0x00000000 // LP_AUTO_EXIT_EN:RW:24:3:=0x00 LP_AUTO_ENTRY_EN:RW:16:3:=0x00 LP_ARB_STATE:RD:8:4:=0x00 LP_STATE:RD:0:6:=0x00 +#define DENALI_CTL_28_DATA 0x00000000 // LP_AUTO_SR_IDLE:RW:24:8:=0x00 LP_AUTO_PD_IDLE:RW:8:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:0:2:=0x00 +#define DENALI_CTL_29_DATA 0x00000000 // RESERVED:RW:8:7:=0x00 LP_AUTO_SR_MC_GATE_IDLE:RW:0:8:=0x00 +#define DENALI_CTL_30_DATA 0x00000000 // WRITE_MODEREG:RW+:0:26:=0x00000000 +#define DENALI_CTL_31_DATA 0x00084000 // MR0_DATA_0:RW:8:16:=0x0840 MRW_STATUS:RD:0:8:=0x00 +#define DENALI_CTL_32_DATA 0x00080046 // MR2_DATA_0:RW:16:16:=0x0008 MR1_DATA_0:RW:0:16:=0x0046 +#define DENALI_CTL_33_DATA 0x00000000 // MR3_DATA_0:RW:16:16:=0x0000 MRSINGLE_DATA_0:RW:0:16:=0x0000 +#define DENALI_CTL_34_DATA 0x00460840 // MR1_DATA_1:RW:16:16:=0x0046 MR0_DATA_1:RW:0:16:=0x0840 +#define DENALI_CTL_35_DATA 0x00000008 // MRSINGLE_DATA_1:RW:16:16:=0x0000 MR2_DATA_1:RW:0:16:=0x0008 +#define DENALI_CTL_36_DATA 0x00010000 // FWC:WR:24:1:=0x00 ECC_EN:RW:16:1:=0x01 MR3_DATA_1:RW:0:16:=0x0000 +#define DENALI_CTL_37_DATA 0x00000000 // ECC_DISABLE_W_UC_ERR:RW:16:1:=0x00 XOR_CHECK_BITS:RW:0:14:=0x0000 +#define DENALI_CTL_38_DATA 0x00000000 // ECC_U_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 // ECC_U_SYND:RD:0:7:=0x00 +#define DENALI_CTL_40_DATA 0x00000000 // ECC_U_DATA:RD:0:32:=0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 // ECC_C_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 // ECC_C_SYND:RD:0:7:=0x00 +#define DENALI_CTL_43_DATA 0x00000000 // ECC_C_DATA:RD:0:32:=0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 // LONG_COUNT_MASK:RW:16:5:=0x00 ECC_C_ID:RD:8:6:=0x00 ECC_U_ID:RD:0:6:=0x00 +#define DENALI_CTL_45_DATA 0x01000200 // ZQCL:RW:16:12:=0x0100 ZQINIT:RW_D:0:12:=0x0200 +#define DENALI_CTL_46_DATA 0x02000040 // ZQ_ON_SREF_EXIT:RW:24:2:=0x02 ZQ_REQ:WR:16:2:=0x00 ZQCS:RW:0:12:=0x0040 +#define DENALI_CTL_47_DATA 0x00000040 // ZQ_INTERVAL:RW:0:32:=0x00000040 +#define DENALI_CTL_48_DATA 0x01000100 // ROW_DIFF:RW:24:3:=0x01 BANK_DIFF:RW:16:2:=0x00 ZQCS_ROTATE:RW:8:1:=0x01 ZQ_IN_PROGRESS:RD:0:1:=0x00 +#define DENALI_CTL_49_DATA 0xffff0a01 // COMMAND_AGE_COUNT:RW:24:8:=0xff AGE_COUNT:RW:16:8:=0xff APREBIT:RW_D:8:4:=0x0a COL_DIFF:RW:0:4:=0x01 +#define DENALI_CTL_50_DATA 0x01010101 // PLACEMENT_EN:RW:24:1:=0x01 BANK_SPLIT_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x01 ADDR_CMP_EN:RW:0:1:=0x01 +#define DENALI_CTL_51_DATA 0x01010101 // CS_SAME_EN:RW:24:1:=0x01 RW_SAME_PAGE_EN:RW:16:1:=0x01 RW_SAME_EN:RW:8:1:=0x01 PRIORITY_EN:RW:0:1:=0x01 +#define DENALI_CTL_52_DATA 0x01030101 // SWAP_EN:RW:24:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:16:3:=0x03 DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01 W2R_SPLIT_EN:RW:0:1:=0x01 +#define DENALI_CTL_53_DATA 0x0c030000 // BURST_ON_FLY_BIT:RW:24:4:=0x0c CS_MAP:RW:16:2:=0x03 INHIBIT_DRAM_CMD:RW:8:1:=0x00 DISABLE_RD_INTERLEAVE:RW:0:1:=0x00 +#define DENALI_CTL_54_DATA 0x00000000 // CONTROLLER_BUSY:RD:24:1:=0x00 IN_ORDER_ACCEPT:RW:16:1:=0x00 Q_FULLNESS:RW:8:3:=0x00 REDUC:RW:0:1:=0x00 +#define DENALI_CTL_55_DATA 0x00000100 // CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 CTRLUPD_REQ:WR:0:1:=0x00 +#define DENALI_CTL_56_DATA 0x00000000 // INT_STATUS:RD:0:23:=0x000000 +#define DENALI_CTL_57_DATA 0x00000000 // INT_ACK:WR:0:22:=0x000000 +#define DENALI_CTL_58_DATA 0x00000000 // INT_MASK:RW:0:23:=0x000000 +#define DENALI_CTL_59_DATA 0x00000000 // OUT_OF_RANGE_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_60_DATA 0x00000000 // OUT_OF_RANGE_SOURCE_ID:RD:16:6:=0x00 OUT_OF_RANGE_TYPE:RD:8:6:=0x00 OUT_OF_RANGE_LENGTH:RD:0:7:=0x00 +#define DENALI_CTL_61_DATA 0x00000000 // PORT_CMD_ERROR_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_62_DATA 0x01020000 // ODT_WR_MAP_CS0:RW:24:2:=0x01 ODT_RD_MAP_CS0:RW:16:2:=0x02 PORT_CMD_ERROR_TYPE:RD:8:3:=0x00 PORT_CMD_ERROR_ID:RD:0:6:=0x00 +#define DENALI_CTL_63_DATA 0x06050201 // TODTH_WR:RW:24:4:=0x06 TODTL_2CMD:RW:16:8:=0x05 ODT_WR_MAP_CS1:RW:8:2:=0x02 ODT_RD_MAP_CS1:RW:0:2:=0x01 +#define DENALI_CTL_64_DATA 0x02000106 // RD_TO_ODTH:RW:24:7:=0x02 WR_TO_ODTH:RW:16:7:=0x00 ODT_EN:RW:8:1:=0x01 TODTH_RD:RW:0:4:=0x06 +#define DENALI_CTL_65_DATA 0x00000000 // +#define DENALI_CTL_66_DATA 0x02020202 // W2W_DIFFCS_DLY:RW_D:24:4:=0x02 W2R_DIFFCS_DLY:RW_D:16:3:=0x02 R2W_DIFFCS_DLY:RW_D:8:3:=0x02 R2R_DIFFCS_DLY:RW_D:0:3:=0x02 +#define DENALI_CTL_67_DATA 0x00000200 // W2W_SAMECS_DLY:RW:24:3:=0x00 W2R_SAMECS_DLY:RW:16:3:=0x00 R2W_SAMECS_DLY:RW_D:8:3:=0x02 R2R_SAMECS_DLY:RW:0:3:=0x00 +#define DENALI_CTL_68_DATA 0x00000000 // SWLVL_LOAD:WR:24:1:=0x00 SW_LEVELING_MODE:RW:16:2:=0x00 OCD_ADJUST_PUP_CS_0:RW:8:5:=0x00 OCD_ADJUST_PDN_CS_0:RW:0:5:=0x00 +#define DENALI_CTL_69_DATA 0x00000000 // LVL_STATUS:RD:24:4:=0x00 SWLVL_OP_DONE:RD:16:1:=0x00 SWLVL_EXIT:WR:8:1:=0x00 SWLVL_START:WR:0:1:=0x00 +#define DENALI_CTL_70_DATA 0x00000000 // WRLVL_REQ:WR:24:1:=0x00 SWLVL_RESP_2:RD:16:8:=0x00 SWLVL_RESP_1:RD:8:8:=0x00 SWLVL_RESP_0:RD:0:8:=0x00 +#define DENALI_CTL_71_DATA 0x00280d00 // WRLVL_EN:RW:24:1:=0x00 WLMRD:RW:16:6:=0x28 WLDQSEN:RW:8:6:=0x0d WRLVL_CS:RW:0:1:=0x00 +#define DENALI_CTL_72_DATA 0x00000000 // WRLVL_ERROR_STATUS:RD:24:8:=0x00 RESERVED:RW:16:3:=0x00 WRLVL_INTERVAL:RW:0:16:=0x0000 +#define DENALI_CTL_73_DATA 0x00000100 // WRLVL_DELAY_0:RW+:8:16:=0x0001 WRLVL_REG_EN:RW:0:1:=0x00 +#define DENALI_CTL_74_DATA 0x00010001 // WRLVL_DELAY_2:RW+:16:16:=0x0001 WRLVL_DELAY_1:RW+:0:16:=0x0001 +#define DENALI_CTL_75_DATA 0x00000000 // RDLVL_EDGE:RW:24:1:=0x00 RDLVL_CS:RW:16:1:=0x00 RDLVL_GATE_REQ:WR:8:1:=0x00 RDLVL_REQ:WR:0:1:=0x00 +#define DENALI_CTL_76_DATA 0x00000000 // RDLVL_GATE_REG_EN:RW:16:1:=0x00 RDLVL_REG_EN:RW:8:1:=0x00 RDLVL_BEGIN_DELAY_EN:RW:0:1:=0x00 +#define DENALI_CTL_77_DATA 0x00000000 // RDLVL_END_DELAY_0:RD:16:16:=0x0000 RDLVL_BEGIN_DELAY_0:RD:0:16:=0x0000 +#define DENALI_CTL_78_DATA 0x00000000 // RDLVL_OFFSET_DELAY_0:RW:16:16:=0x0000 RDLVL_MIDPOINT_DELAY_0:RD:0:16:=0x0000 +#define DENALI_CTL_79_DATA 0x00212100 // RDLVL_DELAY_0:RW:8:16:=0x2121 RDLVL_OFFSET_DIR_0:RW:0:1:=0x00 +#define DENALI_CTL_80_DATA 0x00000001 // RDLVL_BEGIN_DELAY_1:RD:16:16:=0x0000 RDLVL_GATE_DELAY_0:RW+:0:16:=0x0001 +#define DENALI_CTL_81_DATA 0x00000000 // RDLVL_MIDPOINT_DELAY_1:RD:16:16:=0x0000 RDLVL_END_DELAY_1:RD:0:16:=0x0000 +#define DENALI_CTL_82_DATA 0x00000000 // RDLVL_OFFSET_DIR_1:RW:16:1:=0x00 RDLVL_OFFSET_DELAY_1:RW:0:16:=0x0000 +#define DENALI_CTL_83_DATA 0x00012121 // RDLVL_GATE_DELAY_1:RW+:16:16:=0x0001 RDLVL_DELAY_1:RW:0:16:=0x2121 +#define DENALI_CTL_84_DATA 0x00000000 // RDLVL_END_DELAY_2:RD:16:16:=0x0000 RDLVL_BEGIN_DELAY_2:RD:0:16:=0x0000 +#define DENALI_CTL_85_DATA 0x00000000 // RDLVL_OFFSET_DELAY_2:RW:16:16:=0x0000 RDLVL_MIDPOINT_DELAY_2:RD:0:16:=0x0000 +#define DENALI_CTL_86_DATA 0x00212100 // RDLVL_DELAY_2:RW:8:16:=0x2121 RDLVL_OFFSET_DIR_2:RW:0:1:=0x00 +#define DENALI_CTL_87_DATA 0x02020001 // AXI0_W_PRIORITY:RW:24:2:=0x02 AXI0_R_PRIORITY:RW:16:2:=0x02 RDLVL_GATE_DELAY_2:RW+:0:16:=0x0001 +#define DENALI_CTL_88_DATA 0x00020200 // AXI1_FIFO_TYPE_REG:RW:24:2:=0x00 AXI1_W_PRIORITY:RW:16:2:=0x02 AXI1_R_PRIORITY:RW:8:2:=0x02 AXI0_FIFO_TYPE_REG:RW:0:2:=0x00 +#define DENALI_CTL_89_DATA 0x02000202 // AXI3_R_PRIORITY:RW:24:2:=0x02 AXI2_FIFO_TYPE_REG:RW:16:2:=0x00 AXI2_W_PRIORITY:RW:8:2:=0x02 AXI2_R_PRIORITY:RW:0:2:=0x02 +#define DENALI_CTL_90_DATA 0x01000002 // PORT_ADDR_PROTECTION_EN:RW:24:1:=0x01 AXI3_FIFO_TYPE_REG:RW:8:2:=0x00 AXI3_W_PRIORITY:RW:0:2:=0x02 +#define DENALI_CTL_91_DATA 0x00000000 // AXI0_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_92_DATA 0x0003ffff // AXI0_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_93_DATA 0x00000000 // AXI0_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_94_DATA 0x0003ffff // AXI0_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_95_DATA 0x00000000 // AXI0_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_96_DATA 0x0003ffff // AXI0_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_97_DATA 0x00000000 // AXI0_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_98_DATA 0x0003ffff // AXI0_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_99_DATA 0x00000000 // AXI0_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_100_DATA 0x0003ffff // AXI0_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_101_DATA 0x00000000 // AXI0_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_102_DATA 0x0003ffff // AXI0_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_103_DATA 0x00000000 // AXI0_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_104_DATA 0x0003ffff // AXI0_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_105_DATA 0x00000000 // AXI0_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_106_DATA 0x0003ffff // AXI0_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_107_DATA 0x00000000 // AXI0_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_108_DATA 0x0003ffff // AXI0_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_109_DATA 0x00000000 // AXI0_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_110_DATA 0x0003ffff // AXI0_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_111_DATA 0x00000000 // AXI0_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_112_DATA 0x0003ffff // AXI0_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_113_DATA 0x00000000 // AXI0_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_114_DATA 0x0003ffff // AXI0_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_115_DATA 0x00000000 // AXI0_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_116_DATA 0x0003ffff // AXI0_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_117_DATA 0x00000000 // AXI0_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_118_DATA 0x0003ffff // AXI0_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_119_DATA 0x00000000 // AXI0_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_120_DATA 0x0003ffff // AXI0_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_121_DATA 0x00000000 // AXI0_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_122_DATA 0x0003ffff // AXI0_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_123_DATA 0x00000000 // AXI1_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_124_DATA 0x0003ffff // AXI1_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_125_DATA 0x00000000 // AXI1_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_126_DATA 0x0003ffff // AXI1_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_127_DATA 0x00000000 // AXI1_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_128_DATA 0x0003ffff // AXI1_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_129_DATA 0x00000000 // AXI1_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_130_DATA 0x0003ffff // AXI1_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_131_DATA 0x00000000 // AXI1_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_132_DATA 0x0003ffff // AXI1_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_133_DATA 0x00000000 // AXI1_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_134_DATA 0x0003ffff // AXI1_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_135_DATA 0x00000000 // AXI1_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_136_DATA 0x0003ffff // AXI1_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_137_DATA 0x00000000 // AXI1_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_138_DATA 0x0003ffff // AXI1_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_139_DATA 0x00000000 // AXI1_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_140_DATA 0x0003ffff // AXI1_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_141_DATA 0x00000000 // AXI1_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_142_DATA 0x0003ffff // AXI1_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_143_DATA 0x00000000 // AXI1_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_144_DATA 0x0003ffff // AXI1_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_145_DATA 0x00000000 // AXI1_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_146_DATA 0x0003ffff // AXI1_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_147_DATA 0x00000000 // AXI1_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_148_DATA 0x0003ffff // AXI1_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_149_DATA 0x00000000 // AXI1_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_150_DATA 0x0003ffff // AXI1_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_151_DATA 0x00000000 // AXI1_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_152_DATA 0x0003ffff // AXI1_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_153_DATA 0x00000000 // AXI1_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_154_DATA 0x0003ffff // AXI1_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_155_DATA 0x00000000 // AXI2_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_156_DATA 0x0003ffff // AXI2_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_157_DATA 0x00000000 // AXI2_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_158_DATA 0x0003ffff // AXI2_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_159_DATA 0x00000000 // AXI2_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_160_DATA 0x0003ffff // AXI2_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_161_DATA 0x00000000 // AXI2_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_162_DATA 0x0003ffff // AXI2_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_163_DATA 0x00000000 // AXI2_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_164_DATA 0x0003ffff // AXI2_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_165_DATA 0x00000000 // AXI2_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_166_DATA 0x0003ffff // AXI2_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_167_DATA 0x00000000 // AXI2_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_168_DATA 0x0003ffff // AXI2_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_169_DATA 0x00000000 // AXI2_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_170_DATA 0x0003ffff // AXI2_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_171_DATA 0x00000000 // AXI2_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_172_DATA 0x0003ffff // AXI2_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_173_DATA 0x00000000 // AXI2_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_174_DATA 0x0003ffff // AXI2_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_175_DATA 0x00000000 // AXI2_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_176_DATA 0x0003ffff // AXI2_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_177_DATA 0x00000000 // AXI2_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_178_DATA 0x0003ffff // AXI2_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_179_DATA 0x00000000 // AXI2_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_180_DATA 0x0003ffff // AXI2_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_181_DATA 0x00000000 // AXI2_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_182_DATA 0x0003ffff // AXI2_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_183_DATA 0x00000000 // AXI2_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_184_DATA 0x0003ffff // AXI2_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_185_DATA 0x00000000 // AXI2_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_186_DATA 0x0003ffff // AXI2_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_187_DATA 0x00000000 // AXI3_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_188_DATA 0x0003ffff // AXI3_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_189_DATA 0x00000000 // AXI3_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_190_DATA 0x0003ffff // AXI3_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_191_DATA 0x00000000 // AXI3_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_192_DATA 0x0003ffff // AXI3_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_193_DATA 0x00000000 // AXI3_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_194_DATA 0x0003ffff // AXI3_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_195_DATA 0x00000000 // AXI3_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_196_DATA 0x0003ffff // AXI3_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_197_DATA 0x00000000 // AXI3_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_198_DATA 0x0003ffff // AXI3_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_199_DATA 0x00000000 // AXI3_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_200_DATA 0x0003ffff // AXI3_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_201_DATA 0x00000000 // AXI3_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_202_DATA 0x0003ffff // AXI3_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_203_DATA 0x00000000 // AXI3_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_204_DATA 0x0003ffff // AXI3_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_205_DATA 0x00000000 // AXI3_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_206_DATA 0x0003ffff // AXI3_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_207_DATA 0x00000000 // AXI3_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_208_DATA 0x0003ffff // AXI3_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_209_DATA 0x00000000 // AXI3_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_210_DATA 0x0003ffff // AXI3_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_211_DATA 0x00000000 // AXI3_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_212_DATA 0x0003ffff // AXI3_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_213_DATA 0x00000000 // AXI3_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_214_DATA 0x0003ffff // AXI3_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_215_DATA 0x00000000 // AXI3_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_216_DATA 0x0003ffff // AXI3_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_217_DATA 0x00000000 // AXI3_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_218_DATA 0x0303ffff // AXI0_RANGE_PROT_BITS_0:RW:24:2:=0x03 AXI3_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_219_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_220_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_221_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_222_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_223_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_224_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_225_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_226_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_227_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_228_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_229_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_230_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_231_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_232_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_233_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_234_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_235_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_236_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_237_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_238_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_239_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_240_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_241_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_242_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_243_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_244_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_245_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_246_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_247_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_248_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_249_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_250_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_251_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_252_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_253_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_254_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_255_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_256_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_257_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_258_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_259_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_260_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_261_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_262_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_263_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_264_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_265_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_266_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_267_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_268_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_269_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_270_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_271_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_272_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_273_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_274_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_275_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_276_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_277_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_278_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_279_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_280_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_281_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_282_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_283_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_284_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_285_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_286_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_287_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_288_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_289_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_290_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_291_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_292_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_293_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_294_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_295_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_296_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_297_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_298_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_299_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_300_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_301_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_302_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_303_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_304_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_305_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_306_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_307_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_308_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_309_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_310_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_311_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_312_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_313_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_314_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_315_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_316_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_317_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_318_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_319_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_320_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_321_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_322_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_323_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_324_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_325_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_326_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_327_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_328_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_329_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_330_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_331_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_332_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_333_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_334_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_335_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_336_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_337_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_338_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_339_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_340_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_341_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_342_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_343_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_344_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_345_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_346_DATA 0x32030f0f // AXI0_BDW:RW:24:7:=0x32 ARB_CMD_Q_THRESHOLD:RW:16:3:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_347_DATA 0x01320001 // AXI1_BDW_OVFLOW:RW:24:1:=0x01 AXI1_BDW:RW:16:7:=0x32 AXI0_CURRENT_BDW:RD:8:7:=0x00 AXI0_BDW_OVFLOW:RW:0:1:=0x01 +#define DENALI_CTL_348_DATA 0x00013200 // AXI2_CURRENT_BDW:RD:24:7:=0x00 AXI2_BDW_OVFLOW:RW:16:1:=0x01 AXI2_BDW:RW:8:7:=0x32 AXI1_CURRENT_BDW:RD:0:7:=0x00 +#define DENALI_CTL_349_DATA 0x00000132 // CKE_STATUS:RD:24:2:=0x00 AXI3_CURRENT_BDW:RD:16:7:=0x00 AXI3_BDW_OVFLOW:RW:8:1:=0x01 AXI3_BDW:RW:0:7:=0x32 +#define DENALI_CTL_350_DATA 0x00000000 // DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00 +#define DENALI_CTL_351_DATA 0x000d0000 // TDFI_RDDATA_EN:RD:24:6:=0x00 TDFI_PHY_RDLAT:RW_D:16:6:=0x0d UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:6:=0x00 +#define DENALI_CTL_352_DATA 0x1e680000 // TDFI_CTRLUPD_MAX:RW:16:14:=0x1e68 TDFI_CTRLUPD_MIN:RD:8:4:=0x00 DRAM_CLK_DISABLE:RW:0:2:=0x00 +#define DENALI_CTL_353_DATA 0x02000200 // TDFI_PHYUPD_TYPE1:RW:16:16:=0x0200 TDFI_PHYUPD_TYPE0:RW:0:16:=0x0200 +#define DENALI_CTL_354_DATA 0x02000200 // TDFI_PHYUPD_TYPE3:RW:16:16:=0x0200 TDFI_PHYUPD_TYPE2:RW:0:16:=0x0200 +#define DENALI_CTL_355_DATA 0x00001e68 // TDFI_PHYUPD_RESP:RW:0:14:=0x1e68 +#define DENALI_CTL_356_DATA 0x00009808 // TDFI_CTRLUPD_INTERVAL:RW:0:32:=0x00009808 +#define DENALI_CTL_357_DATA 0x00020608 // TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x00 TDFI_CTRL_DELAY:RW_D:16:4:=0x02 WRLAT_ADJ:RW:8:6:=0x06 RDLAT_ADJ:RW:0:6:=0x08 +#define DENALI_CTL_358_DATA 0x000a0a01 // TDFI_WRLVL_WW:RW:16:10:=0x000a TDFI_WRLVL_EN:RW:8:8:=0x0a TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x01 +#define DENALI_CTL_359_DATA 0x00000000 // TDFI_WRLVL_RESP:RW:0:32:=0x00000000 +#define DENALI_CTL_360_DATA 0x00000000 // TDFI_WRLVL_MAX:RW:0:32:=0x00000000 +#define DENALI_CTL_361_DATA 0x04038000 // TDFI_WRLVL_RESPLAT:RW:24:8:=0x04 TDFI_WRLVL_DLL:RW:16:8:=0x03 DFI_WRLVL_MAX_DELAY:RW:0:16:=0x8000 +#define DENALI_CTL_362_DATA 0x07030a07 // TDFI_RDLVL_LOAD:RW:24:8:=0x07 TDFI_RDLVL_DLL:RW:16:8:=0x03 TDFI_RDLVL_EN:RW:8:8:=0x0a TDFI_WRLVL_LOAD:RW:0:8:=0x07 +#define DENALI_CTL_363_DATA 0x00ffff22 // RDLVL_MAX_DELAY:RW:8:16:=0xffff TDFI_RDLVL_RESPLAT:RW:0:8:=0x22 +#define DENALI_CTL_364_DATA 0x000f0010 // TDFI_RDLVL_RR:RW:16:10:=0x000f RDLVL_GATE_MAX_DELAY:RW:0:16:=0x0010 +#define DENALI_CTL_365_DATA 0x00000000 // TDFI_RDLVL_RESP:RW:0:32:=0x00000000 +#define DENALI_CTL_366_DATA 0x00000000 // RDLVL_RESP_MASK:RW:0:20:=0x000000 +#define DENALI_CTL_367_DATA 0x00000000 // RDLVL_EN:RW:24:1:=0x00 RDLVL_GATE_RESP_MASK:RW:0:20:=0x000000 +#define DENALI_CTL_368_DATA 0x00000000 // RDLVL_GATE_PREAMBLE_CHECK_EN:RW:8:1:=0x00 RDLVL_GATE_EN:RW:0:1:=0x00 +#define DENALI_CTL_369_DATA 0x00000000 // TDFI_RDLVL_MAX:RW:0:32:=0x00000000 +#define DENALI_CTL_370_DATA 0x00000204 // RDLVL_ERROR_STATUS:RD:16:14:=0x0000 RDLVL_GATE_DQ_ZERO_COUNT:RW:8:4:=0x02 RDLVL_DQ_ZERO_COUNT:RW:0:4:=0x04 +#define DENALI_CTL_371_DATA 0x00000000 // RDLVL_GATE_INTERVAL:RW:16:16:=0x0000 RDLVL_INTERVAL:RW:0:16:=0x0000 +#define DENALI_CTL_372_DATA 0x01000001 // OPTIMAL_RMODW_EN:RW:24:1:=0x01 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:16:8:=0x00 MEMCD_RMODW_FIFO_DEPTH:RD:8:8:=0x00 TDFI_PHY_WRDATA:RW:0:3:=0x01 +#define DENALI_CTL_373_DATA 0x00000001 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:5:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x01 +#define DENALI_CTL_374_DATA 0x00000000 // AXI3_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI2_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 AXI1_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:0:1:=0x00 + diff --git a/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h b/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h new file mode 100644 index 0000000000..cfef7fa0bf --- /dev/null +++ b/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h @@ -0,0 +1,399 @@ + +/* **************************************************************** + * CADENCE Copyright (c) 2001-2011 * + * Cadence Design Systems, Inc. * + * All rights reserved. * + * * + ****************************************************************** + * The values calculated from this script are meant to be * + * representative programmings. The values may not reflect the * + * actual required programming for production use. Please * + * closely review all programmed values for technical accuracy * + * before use in production parts. * + ****************************************************************** + * + * Module: regconfig.h + * Documentation: Register programming header file + * + ****************************************************************** + ****************************************************************** + * WARNING: This file was automatically generated. Manual + * editing may result in undetermined behavior. + ****************************************************************** + ******************************************************************/ + +#define DENALI_CTL_00_DATA 0x00000600 +#define DENALI_CTL_01_DATA 0x00000000 +#define DENALI_CTL_02_DATA 0x00000000 +#define DENALI_CTL_03_DATA 0x00000000 +#define DENALI_CTL_04_DATA 0x00000000 +#define DENALI_CTL_05_DATA 0x00000000 +#define DENALI_CTL_06_DATA 0x00000000 +#define DENALI_CTL_07_DATA 0x00000005 +#define DENALI_CTL_08_DATA 0x000186a0 +#define DENALI_CTL_09_DATA 0x0003d090 +#define DENALI_CTL_10_DATA 0x00000000 +#define DENALI_CTL_11_DATA 0x10000200 +#define DENALI_CTL_12_DATA 0x04040006 +#define DENALI_CTL_13_DATA 0x04121904 +#define DENALI_CTL_14_DATA 0x04041707 +#define DENALI_CTL_15_DATA 0x00891c0c +#define DENALI_CTL_16_DATA 0x07000503 +#define DENALI_CTL_17_DATA 0x01010008 +#define DENALI_CTL_18_DATA 0x0007030f +#define DENALI_CTL_19_DATA 0x01000000 +#define DENALI_CTL_20_DATA 0x0f340050 +#define DENALI_CTL_21_DATA 0x00000005 +#define DENALI_CTL_22_DATA 0x000c0003 +#define DENALI_CTL_23_DATA 0x00000000 +#define DENALI_CTL_24_DATA 0x00550200 +#define DENALI_CTL_25_DATA 0x00010000 +#define DENALI_CTL_26_DATA 0x00050500 +#define DENALI_CTL_27_DATA 0x00000000 +#define DENALI_CTL_28_DATA 0x00000000 +#define DENALI_CTL_29_DATA 0x00000000 +#define DENALI_CTL_30_DATA 0x00000000 +#define DENALI_CTL_31_DATA 0x00084000 +#define DENALI_CTL_32_DATA 0x00080046 +#define DENALI_CTL_33_DATA 0x00000000 +#define DENALI_CTL_34_DATA 0x00460840 +#define DENALI_CTL_35_DATA 0x00000008 +#define DENALI_CTL_36_DATA 0x00010000 +#define DENALI_CTL_37_DATA 0x00000000 +#define DENALI_CTL_38_DATA 0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 +#define DENALI_CTL_40_DATA 0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 +#define DENALI_CTL_43_DATA 0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 +#define DENALI_CTL_45_DATA 0x01000200 +#define DENALI_CTL_46_DATA 0x02000040 +#define DENALI_CTL_47_DATA 0x00000040 +#define DENALI_CTL_48_DATA 0x02000100 +#define DENALI_CTL_49_DATA 0xffff0a01 +#define DENALI_CTL_50_DATA 0x01010101 +#define DENALI_CTL_51_DATA 0x01010101 +#define DENALI_CTL_52_DATA 0x01030101 +#define DENALI_CTL_53_DATA 0x0c030000 +#define DENALI_CTL_54_DATA 0x00000000 +#define DENALI_CTL_55_DATA 0x00000100 +#define DENALI_CTL_56_DATA 0x00000000 +#define DENALI_CTL_57_DATA 0x00000000 +#define DENALI_CTL_58_DATA 0x00000000 +#define DENALI_CTL_59_DATA 0x00000000 +#define DENALI_CTL_60_DATA 0x00000000 +#define DENALI_CTL_61_DATA 0x00000000 +#define DENALI_CTL_62_DATA 0x01020000 +#define DENALI_CTL_63_DATA 0x06050201 +#define DENALI_CTL_64_DATA 0x02000106 +#define DENALI_CTL_65_DATA 0x00000000 +#define DENALI_CTL_66_DATA 0x02020202 +#define DENALI_CTL_67_DATA 0x00000200 +#define DENALI_CTL_68_DATA 0x00000000 +#define DENALI_CTL_69_DATA 0x00000000 +#define DENALI_CTL_70_DATA 0x00000000 +#define DENALI_CTL_71_DATA 0x00280d00 +#define DENALI_CTL_72_DATA 0x00000000 +#define DENALI_CTL_73_DATA 0x00000100 +#define DENALI_CTL_74_DATA 0x00010001 +#define DENALI_CTL_75_DATA 0x00000000 +#define DENALI_CTL_76_DATA 0x00000000 +#define DENALI_CTL_77_DATA 0x00000000 +#define DENALI_CTL_78_DATA 0x00000000 +#define DENALI_CTL_79_DATA 0x00222200 +#define DENALI_CTL_80_DATA 0x00000001 +#define DENALI_CTL_81_DATA 0x00000000 +#define DENALI_CTL_82_DATA 0x00000000 +#define DENALI_CTL_83_DATA 0x00012222 +#define DENALI_CTL_84_DATA 0x00000000 +#define DENALI_CTL_85_DATA 0x00000000 +#define DENALI_CTL_86_DATA 0x00222200 +#define DENALI_CTL_87_DATA 0x02020001 +#define DENALI_CTL_88_DATA 0x00020200 +#define DENALI_CTL_89_DATA 0x02000202 +#define DENALI_CTL_90_DATA 0x01000002 +#define DENALI_CTL_91_DATA 0x00000000 +#define DENALI_CTL_92_DATA 0x0003ffff +#define DENALI_CTL_93_DATA 0x00000000 +#define DENALI_CTL_94_DATA 0x0003ffff +#define DENALI_CTL_95_DATA 0x00000000 +#define DENALI_CTL_96_DATA 0x0003ffff +#define DENALI_CTL_97_DATA 0x00000000 +#define DENALI_CTL_98_DATA 0x0003ffff +#define DENALI_CTL_99_DATA 0x00000000 +#define DENALI_CTL_100_DATA 0x0003ffff +#define DENALI_CTL_101_DATA 0x00000000 +#define DENALI_CTL_102_DATA 0x0003ffff +#define DENALI_CTL_103_DATA 0x00000000 +#define DENALI_CTL_104_DATA 0x0003ffff +#define DENALI_CTL_105_DATA 0x00000000 +#define DENALI_CTL_106_DATA 0x0003ffff +#define DENALI_CTL_107_DATA 0x00000000 +#define DENALI_CTL_108_DATA 0x0003ffff +#define DENALI_CTL_109_DATA 0x00000000 +#define DENALI_CTL_110_DATA 0x0003ffff +#define DENALI_CTL_111_DATA 0x00000000 +#define DENALI_CTL_112_DATA 0x0003ffff +#define DENALI_CTL_113_DATA 0x00000000 +#define DENALI_CTL_114_DATA 0x0003ffff +#define DENALI_CTL_115_DATA 0x00000000 +#define DENALI_CTL_116_DATA 0x0003ffff +#define DENALI_CTL_117_DATA 0x00000000 +#define DENALI_CTL_118_DATA 0x0003ffff +#define DENALI_CTL_119_DATA 0x00000000 +#define DENALI_CTL_120_DATA 0x0003ffff +#define DENALI_CTL_121_DATA 0x00000000 +#define DENALI_CTL_122_DATA 0x0003ffff +#define DENALI_CTL_123_DATA 0x00000000 +#define DENALI_CTL_124_DATA 0x0003ffff +#define DENALI_CTL_125_DATA 0x00000000 +#define DENALI_CTL_126_DATA 0x0003ffff +#define DENALI_CTL_127_DATA 0x00000000 +#define DENALI_CTL_128_DATA 0x0003ffff +#define DENALI_CTL_129_DATA 0x00000000 +#define DENALI_CTL_130_DATA 0x0003ffff +#define DENALI_CTL_131_DATA 0x00000000 +#define DENALI_CTL_132_DATA 0x0003ffff +#define DENALI_CTL_133_DATA 0x00000000 +#define DENALI_CTL_134_DATA 0x0003ffff +#define DENALI_CTL_135_DATA 0x00000000 +#define DENALI_CTL_136_DATA 0x0003ffff +#define DENALI_CTL_137_DATA 0x00000000 +#define DENALI_CTL_138_DATA 0x0003ffff +#define DENALI_CTL_139_DATA 0x00000000 +#define DENALI_CTL_140_DATA 0x0003ffff +#define DENALI_CTL_141_DATA 0x00000000 +#define DENALI_CTL_142_DATA 0x0003ffff +#define DENALI_CTL_143_DATA 0x00000000 +#define DENALI_CTL_144_DATA 0x0003ffff +#define DENALI_CTL_145_DATA 0x00000000 +#define DENALI_CTL_146_DATA 0x0003ffff +#define DENALI_CTL_147_DATA 0x00000000 +#define DENALI_CTL_148_DATA 0x0003ffff +#define DENALI_CTL_149_DATA 0x00000000 +#define DENALI_CTL_150_DATA 0x0003ffff +#define DENALI_CTL_151_DATA 0x00000000 +#define DENALI_CTL_152_DATA 0x0003ffff +#define DENALI_CTL_153_DATA 0x00000000 +#define DENALI_CTL_154_DATA 0x0003ffff +#define DENALI_CTL_155_DATA 0x00000000 +#define DENALI_CTL_156_DATA 0x0003ffff +#define DENALI_CTL_157_DATA 0x00000000 +#define DENALI_CTL_158_DATA 0x0003ffff +#define DENALI_CTL_159_DATA 0x00000000 +#define DENALI_CTL_160_DATA 0x0003ffff +#define DENALI_CTL_161_DATA 0x00000000 +#define DENALI_CTL_162_DATA 0x0003ffff +#define DENALI_CTL_163_DATA 0x00000000 +#define DENALI_CTL_164_DATA 0x0003ffff +#define DENALI_CTL_165_DATA 0x00000000 +#define DENALI_CTL_166_DATA 0x0003ffff +#define DENALI_CTL_167_DATA 0x00000000 +#define DENALI_CTL_168_DATA 0x0003ffff +#define DENALI_CTL_169_DATA 0x00000000 +#define DENALI_CTL_170_DATA 0x0003ffff +#define DENALI_CTL_171_DATA 0x00000000 +#define DENALI_CTL_172_DATA 0x0003ffff +#define DENALI_CTL_173_DATA 0x00000000 +#define DENALI_CTL_174_DATA 0x0003ffff +#define DENALI_CTL_175_DATA 0x00000000 +#define DENALI_CTL_176_DATA 0x0003ffff +#define DENALI_CTL_177_DATA 0x00000000 +#define DENALI_CTL_178_DATA 0x0003ffff +#define DENALI_CTL_179_DATA 0x00000000 +#define DENALI_CTL_180_DATA 0x0003ffff +#define DENALI_CTL_181_DATA 0x00000000 +#define DENALI_CTL_182_DATA 0x0003ffff +#define DENALI_CTL_183_DATA 0x00000000 +#define DENALI_CTL_184_DATA 0x0003ffff +#define DENALI_CTL_185_DATA 0x00000000 +#define DENALI_CTL_186_DATA 0x0003ffff +#define DENALI_CTL_187_DATA 0x00000000 +#define DENALI_CTL_188_DATA 0x0003ffff +#define DENALI_CTL_189_DATA 0x00000000 +#define DENALI_CTL_190_DATA 0x0003ffff +#define DENALI_CTL_191_DATA 0x00000000 +#define DENALI_CTL_192_DATA 0x0003ffff +#define DENALI_CTL_193_DATA 0x00000000 +#define DENALI_CTL_194_DATA 0x0003ffff +#define DENALI_CTL_195_DATA 0x00000000 +#define DENALI_CTL_196_DATA 0x0003ffff +#define DENALI_CTL_197_DATA 0x00000000 +#define DENALI_CTL_198_DATA 0x0003ffff +#define DENALI_CTL_199_DATA 0x00000000 +#define DENALI_CTL_200_DATA 0x0003ffff +#define DENALI_CTL_201_DATA 0x00000000 +#define DENALI_CTL_202_DATA 0x0003ffff +#define DENALI_CTL_203_DATA 0x00000000 +#define DENALI_CTL_204_DATA 0x0003ffff +#define DENALI_CTL_205_DATA 0x00000000 +#define DENALI_CTL_206_DATA 0x0003ffff +#define DENALI_CTL_207_DATA 0x00000000 +#define DENALI_CTL_208_DATA 0x0003ffff +#define DENALI_CTL_209_DATA 0x00000000 +#define DENALI_CTL_210_DATA 0x0003ffff +#define DENALI_CTL_211_DATA 0x00000000 +#define DENALI_CTL_212_DATA 0x0003ffff +#define DENALI_CTL_213_DATA 0x00000000 +#define DENALI_CTL_214_DATA 0x0003ffff +#define DENALI_CTL_215_DATA 0x00000000 +#define DENALI_CTL_216_DATA 0x0003ffff +#define DENALI_CTL_217_DATA 0x00000000 +#define DENALI_CTL_218_DATA 0x0303ffff +#define DENALI_CTL_219_DATA 0xffffffff +#define DENALI_CTL_220_DATA 0x00030f0f +#define DENALI_CTL_221_DATA 0xffffffff +#define DENALI_CTL_222_DATA 0x00030f0f +#define DENALI_CTL_223_DATA 0xffffffff +#define DENALI_CTL_224_DATA 0x00030f0f +#define DENALI_CTL_225_DATA 0xffffffff +#define DENALI_CTL_226_DATA 0x00030f0f +#define DENALI_CTL_227_DATA 0xffffffff +#define DENALI_CTL_228_DATA 0x00030f0f +#define DENALI_CTL_229_DATA 0xffffffff +#define DENALI_CTL_230_DATA 0x00030f0f +#define DENALI_CTL_231_DATA 0xffffffff +#define DENALI_CTL_232_DATA 0x00030f0f +#define DENALI_CTL_233_DATA 0xffffffff +#define DENALI_CTL_234_DATA 0x00030f0f +#define DENALI_CTL_235_DATA 0xffffffff +#define DENALI_CTL_236_DATA 0x00030f0f +#define DENALI_CTL_237_DATA 0xffffffff +#define DENALI_CTL_238_DATA 0x00030f0f +#define DENALI_CTL_239_DATA 0xffffffff +#define DENALI_CTL_240_DATA 0x00030f0f +#define DENALI_CTL_241_DATA 0xffffffff +#define DENALI_CTL_242_DATA 0x00030f0f +#define DENALI_CTL_243_DATA 0xffffffff +#define DENALI_CTL_244_DATA 0x00030f0f +#define DENALI_CTL_245_DATA 0xffffffff +#define DENALI_CTL_246_DATA 0x00030f0f +#define DENALI_CTL_247_DATA 0xffffffff +#define DENALI_CTL_248_DATA 0x00030f0f +#define DENALI_CTL_249_DATA 0xffffffff +#define DENALI_CTL_250_DATA 0x00030f0f +#define DENALI_CTL_251_DATA 0xffffffff +#define DENALI_CTL_252_DATA 0x00030f0f +#define DENALI_CTL_253_DATA 0xffffffff +#define DENALI_CTL_254_DATA 0x00030f0f +#define DENALI_CTL_255_DATA 0xffffffff +#define DENALI_CTL_256_DATA 0x00030f0f +#define DENALI_CTL_257_DATA 0xffffffff +#define DENALI_CTL_258_DATA 0x00030f0f +#define DENALI_CTL_259_DATA 0xffffffff +#define DENALI_CTL_260_DATA 0x00030f0f +#define DENALI_CTL_261_DATA 0xffffffff +#define DENALI_CTL_262_DATA 0x00030f0f +#define DENALI_CTL_263_DATA 0xffffffff +#define DENALI_CTL_264_DATA 0x00030f0f +#define DENALI_CTL_265_DATA 0xffffffff +#define DENALI_CTL_266_DATA 0x00030f0f +#define DENALI_CTL_267_DATA 0xffffffff +#define DENALI_CTL_268_DATA 0x00030f0f +#define DENALI_CTL_269_DATA 0xffffffff +#define DENALI_CTL_270_DATA 0x00030f0f +#define DENALI_CTL_271_DATA 0xffffffff +#define DENALI_CTL_272_DATA 0x00030f0f +#define DENALI_CTL_273_DATA 0xffffffff +#define DENALI_CTL_274_DATA 0x00030f0f +#define DENALI_CTL_275_DATA 0xffffffff +#define DENALI_CTL_276_DATA 0x00030f0f +#define DENALI_CTL_277_DATA 0xffffffff +#define DENALI_CTL_278_DATA 0x00030f0f +#define DENALI_CTL_279_DATA 0xffffffff +#define DENALI_CTL_280_DATA 0x00030f0f +#define DENALI_CTL_281_DATA 0xffffffff +#define DENALI_CTL_282_DATA 0x00030f0f +#define DENALI_CTL_283_DATA 0xffffffff +#define DENALI_CTL_284_DATA 0x00030f0f +#define DENALI_CTL_285_DATA 0xffffffff +#define DENALI_CTL_286_DATA 0x00030f0f +#define DENALI_CTL_287_DATA 0xffffffff +#define DENALI_CTL_288_DATA 0x00030f0f +#define DENALI_CTL_289_DATA 0xffffffff +#define DENALI_CTL_290_DATA 0x00030f0f +#define DENALI_CTL_291_DATA 0xffffffff +#define DENALI_CTL_292_DATA 0x00030f0f +#define DENALI_CTL_293_DATA 0xffffffff +#define DENALI_CTL_294_DATA 0x00030f0f +#define DENALI_CTL_295_DATA 0xffffffff +#define DENALI_CTL_296_DATA 0x00030f0f +#define DENALI_CTL_297_DATA 0xffffffff +#define DENALI_CTL_298_DATA 0x00030f0f +#define DENALI_CTL_299_DATA 0xffffffff +#define DENALI_CTL_300_DATA 0x00030f0f +#define DENALI_CTL_301_DATA 0xffffffff +#define DENALI_CTL_302_DATA 0x00030f0f +#define DENALI_CTL_303_DATA 0xffffffff +#define DENALI_CTL_304_DATA 0x00030f0f +#define DENALI_CTL_305_DATA 0xffffffff +#define DENALI_CTL_306_DATA 0x00030f0f +#define DENALI_CTL_307_DATA 0xffffffff +#define DENALI_CTL_308_DATA 0x00030f0f +#define DENALI_CTL_309_DATA 0xffffffff +#define DENALI_CTL_310_DATA 0x00030f0f +#define DENALI_CTL_311_DATA 0xffffffff +#define DENALI_CTL_312_DATA 0x00030f0f +#define DENALI_CTL_313_DATA 0xffffffff +#define DENALI_CTL_314_DATA 0x00030f0f +#define DENALI_CTL_315_DATA 0xffffffff +#define DENALI_CTL_316_DATA 0x00030f0f +#define DENALI_CTL_317_DATA 0xffffffff +#define DENALI_CTL_318_DATA 0x00030f0f +#define DENALI_CTL_319_DATA 0xffffffff +#define DENALI_CTL_320_DATA 0x00030f0f +#define DENALI_CTL_321_DATA 0xffffffff +#define DENALI_CTL_322_DATA 0x00030f0f +#define DENALI_CTL_323_DATA 0xffffffff +#define DENALI_CTL_324_DATA 0x00030f0f +#define DENALI_CTL_325_DATA 0xffffffff +#define DENALI_CTL_326_DATA 0x00030f0f +#define DENALI_CTL_327_DATA 0xffffffff +#define DENALI_CTL_328_DATA 0x00030f0f +#define DENALI_CTL_329_DATA 0xffffffff +#define DENALI_CTL_330_DATA 0x00030f0f +#define DENALI_CTL_331_DATA 0xffffffff +#define DENALI_CTL_332_DATA 0x00030f0f +#define DENALI_CTL_333_DATA 0xffffffff +#define DENALI_CTL_334_DATA 0x00030f0f +#define DENALI_CTL_335_DATA 0xffffffff +#define DENALI_CTL_336_DATA 0x00030f0f +#define DENALI_CTL_337_DATA 0xffffffff +#define DENALI_CTL_338_DATA 0x00030f0f +#define DENALI_CTL_339_DATA 0xffffffff +#define DENALI_CTL_340_DATA 0x00030f0f +#define DENALI_CTL_341_DATA 0xffffffff +#define DENALI_CTL_342_DATA 0x00030f0f +#define DENALI_CTL_343_DATA 0xffffffff +#define DENALI_CTL_344_DATA 0x00030f0f +#define DENALI_CTL_345_DATA 0xffffffff +#define DENALI_CTL_346_DATA 0x32030f0f +#define DENALI_CTL_347_DATA 0x01320001 +#define DENALI_CTL_348_DATA 0x00013200 +#define DENALI_CTL_349_DATA 0x00000132 +#define DENALI_CTL_350_DATA 0x00000000 +#define DENALI_CTL_351_DATA 0x000d0000 +#define DENALI_CTL_352_DATA 0x1e680000 +#define DENALI_CTL_353_DATA 0x02000200 +#define DENALI_CTL_354_DATA 0x02000200 +#define DENALI_CTL_355_DATA 0x00001e68 +#define DENALI_CTL_356_DATA 0x00009808 +#define DENALI_CTL_357_DATA 0x00020608 +#define DENALI_CTL_358_DATA 0x000a0a01 +#define DENALI_CTL_359_DATA 0x00000000 +#define DENALI_CTL_360_DATA 0x00000000 +#define DENALI_CTL_361_DATA 0x04038000 +#define DENALI_CTL_362_DATA 0x07030a07 +#define DENALI_CTL_363_DATA 0x00ffff22 +#define DENALI_CTL_364_DATA 0x000f0010 +#define DENALI_CTL_365_DATA 0x00000000 +#define DENALI_CTL_366_DATA 0x00000000 +#define DENALI_CTL_367_DATA 0x00000000 +#define DENALI_CTL_368_DATA 0x00000000 +#define DENALI_CTL_369_DATA 0x00000000 +#define DENALI_CTL_370_DATA 0x00000204 +#define DENALI_CTL_371_DATA 0x00000000 +#define DENALI_CTL_372_DATA 0x01000001 +#define DENALI_CTL_373_DATA 0x00000001 +#define DENALI_CTL_374_DATA 0x00000000 diff --git a/include/usb.h b/include/usb.h index 80cb846720..42b001c3dd 100644 --- a/include/usb.h +++ b/include/usb.h @@ -11,12 +11,15 @@ #ifndef _USB_H_ #define _USB_H_ +#include <stdbool.h> #include <fdtdec.h> #include <usb_defs.h> #include <linux/usb/ch9.h> #include <asm/cache.h> #include <part.h> +extern bool usb_started; /* flag for the started/stopped USB status */ + /* * The EHCI spec says that we must align to at least 32 bytes. However, * some platforms require larger alignment. diff --git a/net/eth_bootdev.c b/net/eth_bootdev.c index 13e5fcd3bd..f7b4196f78 100644 --- a/net/eth_bootdev.c +++ b/net/eth_bootdev.c @@ -13,8 +13,8 @@ #include <bootflow.h> #include <command.h> #include <bootmeth.h> -#include <distro.h> #include <dm.h> +#include <extlinux.h> #include <init.h> #include <log.h> #include <net.h> @@ -36,7 +36,7 @@ static int eth_get_bootflow(struct udevice *dev, struct bootflow_iter *iter, return log_msg_ret("check", ret); /* - * Like distro boot, this assumes there is only one Ethernet device. + * Like extlinux boot, this assumes there is only one Ethernet device. * In this case, that means that @eth is ignored */ diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 8cf3f30e0f..6b29213416 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -19,9 +19,9 @@ /* Allow reseting the USB-started flag */ #if defined(CONFIG_USB_HOST) || defined(CONFIG_USB_GADGET) -extern char usb_started; +extern bool usb_started; #else -char usb_started; +#include <usb.h> #endif /* Check 'bootdev list' command */ @@ -306,6 +306,7 @@ static int bootdev_test_hunter(struct unit_test_state *uts) { struct bootstd_priv *std; + usb_started = false; test_set_skip_delays(true); /* get access to the used hunters */ @@ -346,6 +347,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) struct bootstd_priv *std; test_set_skip_delays(true); + usb_started = false; /* get access to the used hunters */ ut_assertok(bootstd_get_priv(&std)); @@ -474,6 +476,7 @@ BOOTSTD_TEST(bootdev_test_bootable, UT_TESTF_DM | UT_TESTF_SCAN_FDT); /* Check hunting for bootdev of a particular priority */ static int bootdev_test_hunt_prio(struct unit_test_state *uts) { + usb_started = false; test_set_skip_delays(true); console_record_reset_enable(); @@ -502,6 +505,8 @@ static int bootdev_test_hunt_label(struct unit_test_state *uts) struct bootstd_priv *std; int mflags; + usb_started = false; + /* get access to the used hunters */ ut_assertok(bootstd_get_priv(&std)); diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index fd0e1d6243..2b5f87d7f0 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -57,7 +57,7 @@ static int bootflow_cmd(struct unit_test_state *uts) ut_assert_nextlinen("---"); ut_assert_nextline("Scanning bootdev 'mmc2.bootdev':"); ut_assert_nextline("Scanning bootdev 'mmc1.bootdev':"); - ut_assert_nextline(" 0 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + ut_assert_nextline(" 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_nextline("No more bootdevs"); ut_assert_nextlinen("---"); ut_assert_nextline("(1 bootflow, 1 valid)"); @@ -67,7 +67,7 @@ static int bootflow_cmd(struct unit_test_state *uts) ut_assert_nextline("Showing bootflows for bootdev 'mmc1.bootdev'"); ut_assert_nextline("Seq Method State Uclass Part Name Filename"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 0 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + ut_assert_nextline(" 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_nextlinen("---"); ut_assert_nextline("(1 bootflow, 1 valid)"); ut_assert_console_end(); @@ -136,7 +136,7 @@ static int bootflow_cmd_glob(struct unit_test_state *uts) ut_assert_nextlinen("---"); ut_assert_nextline("Scanning bootdev 'mmc2.bootdev':"); ut_assert_nextline("Scanning bootdev 'mmc1.bootdev':"); - ut_assert_nextline(" 0 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + ut_assert_nextline(" 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_nextline("Scanning bootdev 'mmc0.bootdev':"); ut_assert_nextline("No more bootdevs"); ut_assert_nextlinen("---"); @@ -147,7 +147,7 @@ static int bootflow_cmd_glob(struct unit_test_state *uts) ut_assert_nextline("Showing all bootflows"); ut_assert_nextline("Seq Method State Uclass Part Name Filename"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 0 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + ut_assert_nextline(" 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_nextlinen("---"); ut_assert_nextline("(1 bootflow, 1 valid)"); ut_assert_console_end(); @@ -167,22 +167,22 @@ static int bootflow_cmd_scan_e(struct unit_test_state *uts) ut_assert_nextline("Seq Method State Uclass Part Name Filename"); ut_assert_nextlinen("---"); ut_assert_nextline("Scanning bootdev 'mmc2.bootdev':"); - ut_assert_nextline(" 0 syslinux media mmc 0 mmc2.bootdev.whole <NULL>"); - ut_assert_nextline(" ** No partition found, err=-93"); + ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole <NULL>"); + ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported"); ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole <NULL>"); - ut_assert_nextline(" ** No partition found, err=-93"); + ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported"); ut_assert_nextline("Scanning bootdev 'mmc1.bootdev':"); - ut_assert_nextline(" 2 syslinux media mmc 0 mmc1.bootdev.whole <NULL>"); - ut_assert_nextline(" ** No partition found, err=-2"); + ut_assert_nextline(" 2 extlinux media mmc 0 mmc1.bootdev.whole <NULL>"); + ut_assert_nextline(" ** No partition found, err=-2: No such file or directory"); ut_assert_nextline(" 3 efi media mmc 0 mmc1.bootdev.whole <NULL>"); - ut_assert_nextline(" ** No partition found, err=-2"); - ut_assert_nextline(" 4 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + ut_assert_nextline(" ** No partition found, err=-2: No such file or directory"); + ut_assert_nextline(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_nextline(" 5 efi fs mmc 1 mmc1.bootdev.part_1 efi/boot/bootsbox.efi"); ut_assert_skip_to_line("Scanning bootdev 'mmc0.bootdev':"); ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole <NULL>"); - ut_assert_nextline(" ** No partition found, err=-93"); + ut_assert_nextline(" ** No partition found, err=-93: Protocol not supported"); ut_assert_nextline("No more bootdevs"); ut_assert_nextlinen("---"); ut_assert_nextline("(64 bootflows, 1 valid)"); @@ -192,9 +192,9 @@ static int bootflow_cmd_scan_e(struct unit_test_state *uts) ut_assert_nextline("Showing all bootflows"); ut_assert_nextline("Seq Method State Uclass Part Name Filename"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 0 syslinux media mmc 0 mmc2.bootdev.whole <NULL>"); + ut_assert_nextline(" 0 extlinux media mmc 0 mmc2.bootdev.whole <NULL>"); ut_assert_nextline(" 1 efi media mmc 0 mmc2.bootdev.whole <NULL>"); - ut_assert_skip_to_line(" 4 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + ut_assert_skip_to_line(" 4 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_skip_to_line(" 3f efi media mmc 0 mmc0.bootdev.whole <NULL>"); ut_assert_nextlinen("---"); ut_assert_nextline("(64 bootflows, 1 valid)"); @@ -218,7 +218,7 @@ static int bootflow_cmd_info(struct unit_test_state *uts) ut_assert_nextline("Name: mmc1.bootdev.part_1"); ut_assert_nextline("Device: mmc1.bootdev"); ut_assert_nextline("Block dev: mmc1.blk"); - ut_assert_nextline("Method: syslinux"); + ut_assert_nextline("Method: extlinux"); ut_assert_nextline("State: ready"); ut_assert_nextline("Partition: 1"); ut_assert_nextline("Subdir: (none)"); @@ -251,7 +251,7 @@ static int bootflow_scan_boot(struct unit_test_state *uts) ut_assertok(inject_response(uts)); ut_assertok(run_command("bootflow scan -b", 0)); ut_assert_nextline( - "** Booting bootflow 'mmc1.bootdev.part_1' with syslinux"); + "** Booting bootflow 'mmc1.bootdev.part_1' with extlinux"); ut_assert_nextline("Ignoring unknown command: ui"); /* @@ -282,7 +282,7 @@ static int bootflow_iter(struct unit_test_state *uts) ut_asserteq(0, iter.cur_method); ut_asserteq(0, iter.part); ut_asserteq(0, iter.max_part); - ut_asserteq_str("syslinux", iter.method->name); + ut_asserteq_str("extlinux", iter.method->name); ut_asserteq(0, bflow.err); /* @@ -309,7 +309,7 @@ static int bootflow_iter(struct unit_test_state *uts) ut_asserteq(0, iter.cur_method); ut_asserteq(0, iter.part); ut_asserteq(0x1e, iter.max_part); - ut_asserteq_str("syslinux", iter.method->name); + ut_asserteq_str("extlinux", iter.method->name); ut_asserteq(0, bflow.err); ut_asserteq(BOOTFLOWST_MEDIA, bflow.state); bootflow_free(&bflow); @@ -330,7 +330,7 @@ static int bootflow_iter(struct unit_test_state *uts) ut_asserteq(0, iter.cur_method); ut_asserteq(1, iter.part); ut_asserteq(0x1e, iter.max_part); - ut_asserteq_str("syslinux", iter.method->name); + ut_asserteq_str("extlinux", iter.method->name); ut_asserteq(0, bflow.err); ut_asserteq(BOOTFLOWST_READY, bflow.state); bootflow_free(&bflow); @@ -351,7 +351,7 @@ static int bootflow_iter(struct unit_test_state *uts) ut_asserteq(0, iter.cur_method); ut_asserteq(2, iter.part); ut_asserteq(0x1e, iter.max_part); - ut_asserteq_str("syslinux", iter.method->name); + ut_asserteq_str("extlinux", iter.method->name); ut_asserteq(0, bflow.err); ut_asserteq(BOOTFLOWST_MEDIA, bflow.state); bootflow_free(&bflow); @@ -489,7 +489,7 @@ static int bootflow_cmd_boot(struct unit_test_state *uts) ut_assertok(inject_response(uts)); ut_asserteq(1, run_command("bootflow boot", 0)); ut_assert_nextline( - "** Booting bootflow 'mmc1.bootdev.part_1' with syslinux"); + "** Booting bootflow 'mmc1.bootdev.part_1' with extlinux"); ut_assert_nextline("Ignoring unknown command: ui"); /* @@ -614,7 +614,7 @@ static int bootflow_cmd_hunt_label(struct unit_test_state *uts) ut_assert_nextline("Scanning bootdev 'mmc2.bootdev':"); ut_assert_nextline("Scanning bootdev 'mmc1.bootdev':"); ut_assert_nextline( - " 0 syslinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); + " 0 extlinux ready mmc 1 mmc1.bootdev.part_1 /extlinux/extlinux.conf"); ut_assert_nextline("Scanning bootdev 'mmc0.bootdev':"); ut_assert_skip_to_line("(1 bootflow, 1 valid)"); ut_assert_console_end(); diff --git a/test/boot/bootmeth.c b/test/boot/bootmeth.c index 0098ef3efd..e498eee036 100644 --- a/test/boot/bootmeth.c +++ b/test/boot/bootmeth.c @@ -21,7 +21,7 @@ static int bootmeth_cmd_list(struct unit_test_state *uts) ut_assertok(run_command("bootmeth list", 0)); ut_assert_nextline("Order Seq Name Description"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 0 0 syslinux Syslinux boot from a block device"); + ut_assert_nextline(" 0 0 extlinux Extlinux boot from a block device"); ut_assert_nextline(" 1 1 efi EFI boot from an .efi file"); if (IS_ENABLED(CONFIG_BOOTMETH_GLOBAL)) ut_assert_nextline(" glob 2 firmware0 VBE simple"); @@ -39,16 +39,16 @@ static int bootmeth_cmd_order(struct unit_test_state *uts) { /* Select just one bootmethod */ console_record_reset_enable(); - ut_assertok(run_command("bootmeth order syslinux", 0)); + ut_assertok(run_command("bootmeth order extlinux", 0)); ut_assert_console_end(); ut_assertnonnull(env_get("bootmeths")); - ut_asserteq_str("syslinux", env_get("bootmeths")); + ut_asserteq_str("extlinux", env_get("bootmeths")); /* Only that one should be listed */ ut_assertok(run_command("bootmeth list", 0)); ut_assert_nextline("Order Seq Name Description"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 0 0 syslinux Syslinux boot from a block device"); + ut_assert_nextline(" 0 0 extlinux Extlinux boot from a block device"); ut_assert_nextlinen("---"); ut_assert_nextline("(1 bootmeth)"); ut_assert_console_end(); @@ -57,7 +57,7 @@ static int bootmeth_cmd_order(struct unit_test_state *uts) ut_assertok(run_command("bootmeth list -a", 0)); ut_assert_nextline("Order Seq Name Description"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 0 0 syslinux Syslinux boot from a block device"); + ut_assert_nextline(" 0 0 extlinux Extlinux boot from a block device"); ut_assert_nextline(" - 1 efi EFI boot from an .efi file"); if (IS_ENABLED(CONFIG_BOOTMETH_GLOBAL)) ut_assert_nextline(" glob 2 firmware0 VBE simple"); @@ -67,12 +67,12 @@ static int bootmeth_cmd_order(struct unit_test_state *uts) ut_assert_console_end(); /* Check the -a flag with the reverse order */ - ut_assertok(run_command("bootmeth order \"efi syslinux\"", 0)); + ut_assertok(run_command("bootmeth order \"efi extlinux\"", 0)); ut_assert_console_end(); ut_assertok(run_command("bootmeth list -a", 0)); ut_assert_nextline("Order Seq Name Description"); ut_assert_nextlinen("---"); - ut_assert_nextline(" 1 0 syslinux Syslinux boot from a block device"); + ut_assert_nextline(" 1 0 extlinux Extlinux boot from a block device"); ut_assert_nextline(" 0 1 efi EFI boot from an .efi file"); if (IS_ENABLED(CONFIG_BOOTMETH_GLOBAL)) ut_assert_nextline(" glob 2 firmware0 VBE simple"); @@ -90,17 +90,17 @@ static int bootmeth_cmd_order(struct unit_test_state *uts) "(3 bootmeths)" : "(2 bootmeths)"); /* Try reverse order */ - ut_assertok(run_command("bootmeth order \"efi syslinux\"", 0)); + ut_assertok(run_command("bootmeth order \"efi extlinux\"", 0)); ut_assert_console_end(); ut_assertok(run_command("bootmeth list", 0)); ut_assert_nextline("Order Seq Name Description"); ut_assert_nextlinen("---"); ut_assert_nextline(" 0 1 efi EFI boot from an .efi file"); - ut_assert_nextline(" 1 0 syslinux Syslinux boot from a block device"); + ut_assert_nextline(" 1 0 extlinux Extlinux boot from a block device"); ut_assert_nextlinen("---"); ut_assert_nextline("(2 bootmeths)"); ut_assertnonnull(env_get("bootmeths")); - ut_asserteq_str("efi syslinux", env_get("bootmeths")); + ut_asserteq_str("efi extlinux", env_get("bootmeths")); ut_assert_console_end(); return 0; @@ -140,7 +140,7 @@ static int bootmeth_env(struct unit_test_state *uts) /* Select just one bootmethod */ console_record_reset_enable(); - ut_assertok(env_set("bootmeths", "syslinux")); + ut_assertok(env_set("bootmeths", "extlinux")); ut_asserteq(1, std->bootmeth_count); /* Select an invalid bootmethod */ @@ -149,7 +149,7 @@ static int bootmeth_env(struct unit_test_state *uts) ut_assert_nextlinen("## Error inserting"); ut_assert_console_end(); - ut_assertok(env_set("bootmeths", "efi syslinux")); + ut_assertok(env_set("bootmeths", "efi extlinux")); ut_asserteq(2, std->bootmeth_count); ut_assert_console_end(); diff --git a/test/dm/blk.c b/test/dm/blk.c index 0aa04c64ef..446c4423e6 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -16,9 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Allow resetting the USB-started flag */ -extern char usb_started; - /* Test that block devices can be created */ static int dm_test_blk_base(struct unit_test_state *uts) { diff --git a/tools/Makefile b/tools/Makefile index 38699b069d..d793cf3bec 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -122,6 +122,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + renesas_spkgimage.o \ vybridimage.o \ stm32image.o \ $(ROCKCHIP_OBS) \ diff --git a/tools/renesas_spkgimage.c b/tools/renesas_spkgimage.c new file mode 100644 index 0000000000..fa0a468cc4 --- /dev/null +++ b/tools/renesas_spkgimage.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Generate Renesas RZ/N1 BootROM header (SPKG) + * (C) Copyright 2022 Schneider Electric + * + * Based on spkg_utility.c + * (C) Copyright 2016 Renesas Electronics Europe Ltd + */ + +#include "imagetool.h" +#include <limits.h> +#include <image.h> +#include <stdarg.h> +#include <stdint.h> +#include <u-boot/crc.h> +#include "renesas_spkgimage.h" + +/* Note: the ordering of the bitfields does not matter */ +struct config_file { + unsigned int version:1; + unsigned int ecc_block_size:2; + unsigned int ecc_enable:1; + unsigned int ecc_scheme:3; + unsigned int ecc_bytes:8; + unsigned int blp_len; + unsigned int padding; +}; + +static struct config_file conf; + +static int check_range(const char *name, int val, int min, int max) +{ + if (val < min) { + fprintf(stderr, "Warning: param '%s' adjusted to min %d\n", + name, min); + val = min; + } + + if (val > max) { + fprintf(stderr, "Warning: param '%s' adjusted to max %d\n", + name, max); + val = max; + } + + return val; +} + +static int spkgimage_parse_config_line(char *line, size_t line_num) +{ + char *saveptr; + char *delim = "\t "; + char *name = strtok_r(line, delim, &saveptr); + char *val_str = strtok_r(NULL, delim, &saveptr); + int value = atoi(val_str); + + if (!strcmp("VERSION", name)) { + conf.version = check_range(name, value, 1, 15); + } else if (!strcmp("NAND_ECC_ENABLE", name)) { + conf.ecc_enable = check_range(name, value, 0, 1); + } else if (!strcmp("NAND_ECC_BLOCK_SIZE", name)) { + conf.ecc_block_size = check_range(name, value, 0, 2); + } else if (!strcmp("NAND_ECC_SCHEME", name)) { + conf.ecc_scheme = check_range(name, value, 0, 7); + } else if (!strcmp("NAND_BYTES_PER_ECC_BLOCK", name)) { + conf.ecc_bytes = check_range(name, value, 0, 255); + } else if (!strcmp("ADD_DUMMY_BLP", name)) { + conf.blp_len = value ? SPKG_BLP_SIZE : 0; + } else if (!strcmp("PADDING", name)) { + if (strrchr(val_str, 'K')) + value = value * 1024; + else if (strrchr(val_str, 'M')) + value = value * 1024 * 1024; + conf.padding = check_range(name, value, 1, INT_MAX); + } else { + fprintf(stderr, + "config error: unknown keyword on line %ld\n", + line_num); + return -EINVAL; + } + + return 0; +} + +static int spkgimage_parse_config_file(char *filename) +{ + FILE *fcfg; + char line[256]; + size_t line_num = 0; + + fcfg = fopen(filename, "r"); + if (!fcfg) + return -EINVAL; + + while (fgets(line, sizeof(line), fcfg)) { + line_num += 1; + + /* Skip blank lines and comments */ + if (line[0] == '\n' || line[0] == '#') + continue; + + /* Strip any trailing newline */ + line[strcspn(line, "\n")] = 0; + + /* Parse the line */ + if (spkgimage_parse_config_line(line, line_num)) + return -EINVAL; + } + + fclose(fcfg); + + /* Avoid divide-by-zero later on */ + if (!conf.padding) + conf.padding = 1; + + return 0; +} + +static int spkgimage_check_params(struct image_tool_params *params) +{ + if (!params->addr) { + fprintf(stderr, "Error: Load Address must be set.\n"); + return -EINVAL; + } + + if (!params->imagename || !params->imagename[0]) { + fprintf(stderr, "Error: Image name must be set.\n"); + return -EINVAL; + } + + if (!params->datafile) { + fprintf(stderr, "Error: Data filename must be set.\n"); + return -EINVAL; + } + + return 0; +} + +static int spkgimage_verify_header(unsigned char *ptr, int size, + struct image_tool_params *param) +{ + struct spkg_file *file = (struct spkg_file *)ptr; + struct spkg_hdr *header = (struct spkg_hdr *)ptr; + char marker[4] = SPKG_HEADER_MARKER; + uint32_t payload_length; + uint32_t crc; + uint8_t *crc_buf; + + /* Check the marker bytes */ + if (memcmp(header->marker, marker, 4)) { + fprintf(stderr, "Error: invalid marker bytes\n"); + return -EINVAL; + } + + /* Check the CRC */ + crc = crc32(0, ptr, SPKG_HEADER_SIZE - SPKG_CRC_SIZE); + if (crc != header->crc) { + fprintf(stderr, "Error: invalid header CRC=\n"); + return -EINVAL; + } + + /* Check all copies of header are the same */ + for (int i = 1; i < SPKG_HEADER_COUNT; i++) { + if (memcmp(&header[0], &header[i], SPKG_HEADER_SIZE)) { + fprintf(stderr, "Error: header %d mismatch\n", i); + return -EINVAL; + } + } + + /* Check the payload CRC */ + payload_length = le32_to_cpu(header->payload_length) >> 8; + crc_buf = file->payload + payload_length - SPKG_CRC_SIZE; + crc = crc32(0, file->payload, payload_length - SPKG_CRC_SIZE); + if (crc_buf[0] != (crc & 0xff) || + crc_buf[1] != (crc >> 8 & 0xff) || + crc_buf[2] != (crc >> 16 & 0xff) || + crc_buf[3] != (crc >> 24 & 0xff)) { + fprintf(stderr, "Error: invalid payload CRC\n"); + return -EINVAL; + } + + return 0; +} + +static void spkgimage_print_header(const void *ptr, + struct image_tool_params *image) +{ + const struct spkg_hdr *h = ptr; + uint32_t offset = le32_to_cpu(h->execution_offset); + + printf("Image type\t: Renesas SPKG Image\n"); + printf("Marker\t\t: %c%c%c%c\n", + h->marker[0], h->marker[1], h->marker[2], h->marker[3]); + printf("Version\t\t: %d\n", h->version); + printf("ECC\t\t: "); + if (h->ecc & 0x20) + printf("Scheme %d, Block size %d, Strength %d\n", + h->ecc_scheme, (h->ecc >> 1) & 3, h->ecc_bytes); + else + printf("Not enabled\n"); + printf("Payload length\t: %d\n", le32_to_cpu(h->payload_length) >> 8); + printf("Load address\t: 0x%08x\n", le32_to_cpu(h->load_address)); + printf("Execution offset: 0x%08x (%s mode)\n", offset & ~1, + offset & 1 ? "THUMB" : "ARM"); + printf("Header checksum\t: 0x%08x\n", le32_to_cpu(h->crc)); +} + +/* + * This is the same as the macro version in include/kernel.h. + * However we cannot include that header, because for host tools, + * it ends up pulling in the host /usr/include/linux/kernel.h, + * which lacks the definition of roundup(). + */ +static inline uint32_t roundup(uint32_t x, uint32_t y) +{ + return ((x + y - 1) / y) * y; +} + +static int spkgimage_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + struct stat s; + struct spkg_file *out_buf; + + /* Parse the config file */ + if (spkgimage_parse_config_file(params->imagename)) { + fprintf(stderr, "Error parsing config file\n"); + exit(EXIT_FAILURE); + } + + /* Get size of input data file */ + if (stat(params->datafile, &s)) { + fprintf(stderr, "Could not stat data file: %s: %s\n", + params->datafile, strerror(errno)); + exit(EXIT_FAILURE); + } + params->orig_file_size = s.st_size; + + /* Determine size of resulting SPKG file */ + uint32_t header_len = SPKG_HEADER_SIZE * SPKG_HEADER_COUNT; + uint32_t payload_len = conf.blp_len + s.st_size + SPKG_CRC_SIZE; + uint32_t total_len = header_len + payload_len; + + /* Round up to next multiple of padding size */ + uint32_t padded_len = roundup(total_len, conf.padding); + + /* Number of padding bytes to add */ + conf.padding = padded_len - total_len; + + /* Fixup payload_len to include padding bytes */ + payload_len += conf.padding; + + /* Prepare the header */ + struct spkg_hdr header = { + .marker = SPKG_HEADER_MARKER, + .version = conf.version, + .ecc = (conf.ecc_enable << 5) | (conf.ecc_block_size << 1), + .ecc_scheme = conf.ecc_scheme, + .ecc_bytes = conf.ecc_bytes, + .payload_length = cpu_to_le32(payload_len << 8), + .load_address = cpu_to_le32(params->addr), + .execution_offset = cpu_to_le32(params->ep - params->addr), + }; + header.crc = crc32(0, (uint8_t *)&header, + sizeof(header) - SPKG_CRC_SIZE); + + /* The SPKG contains 8 copies of the header */ + out_buf = malloc(sizeof(struct spkg_file)); + if (!out_buf) { + fprintf(stderr, "Error: Data filename must be set.\n"); + return -ENOMEM; + } + tparams->hdr = out_buf; + tparams->header_size = sizeof(struct spkg_file); + + /* Fill the SPKG with the headers */ + for (int i = 0; i < SPKG_HEADER_COUNT; i++) + memcpy(&out_buf->header[i], &header, sizeof(header)); + + /* Extra bytes to allocate in the output file */ + return conf.blp_len + conf.padding + 4; +} + +static void spkgimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + uint8_t *payload = ptr + SPKG_HEADER_SIZE * SPKG_HEADER_COUNT; + uint8_t *file_end = payload + conf.blp_len + params->orig_file_size; + uint8_t *crc_buf = file_end + conf.padding; + uint32_t crc; + + /* Make room for the Dummy BLp header */ + memmove(payload + conf.blp_len, payload, params->orig_file_size); + + /* Fill the SPKG with the Dummy BLp */ + memset(payload, 0x88, conf.blp_len); + + /* + * mkimage copy_file() pads the input file with zeros. + * Replace those zeros with flash friendly one bits. + * The original version skipped the first 4 bytes, + * probably an oversight, but for consistency we + * keep the same behaviour. + */ + if (conf.padding >= 4) + memset(file_end + 4, 0xff, conf.padding - 4); + + /* Add Payload CRC */ + crc = crc32(0, payload, crc_buf - payload); + crc_buf[0] = crc; + crc_buf[1] = crc >> 8; + crc_buf[2] = crc >> 16; + crc_buf[3] = crc >> 24; +} + +static int spkgimage_check_image_types(uint8_t type) +{ + return type == IH_TYPE_RENESAS_SPKG ? 0 : -EINVAL; +} + +/* + * spkgimage type parameter definition + */ +U_BOOT_IMAGE_TYPE( + spkgimage, + "Renesas SPKG Image", + 0, + NULL, + spkgimage_check_params, + spkgimage_verify_header, + spkgimage_print_header, + spkgimage_set_header, + NULL, + spkgimage_check_image_types, + NULL, + spkgimage_vrec_header +); diff --git a/tools/renesas_spkgimage.h b/tools/renesas_spkgimage.h new file mode 100644 index 0000000000..367e113de9 --- /dev/null +++ b/tools/renesas_spkgimage.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Renesas RZ/N1 Package Table format + * (C) 2015-2016 Renesas Electronics Europe, LTD + * All rights reserved. + * + * Converted to mkimage plug-in + * (C) Copyright 2022 Schneider Electric + */ + +#ifndef _SPKGIMAGE_H_ +#define _SPKGIMAGE_H_ + +#ifdef __GNUC__ +#define __packed __attribute((packed)) +#else +#define __packed +#endif + +#define SPKG_HEADER_MARKER {'R', 'Z', 'N', '1'} +#define SPKG_HEADER_SIZE 24 +#define SPKG_HEADER_COUNT 8 +#define SPKG_BLP_SIZE 264 +#define SPKG_CRC_SIZE 4 + +/** + * struct spkg_hdr - SPKG header + * @marker: magic pattern "RZN1" + * @version: header version (currently 1) + * @ecc: ECC enable and block size. + * @ecc_scheme: ECC algorithm selction + * @ecc_bytes: ECC bytes per block + * @payload_length: length of the payload (including CRC) + * @load_address: address in memory where payload should be loaded + * @execution_offset: offset from @load_address where execution starts + * @crc: 32-bit CRC of the above header fields + * + * SPKG header format is defined by Renesas. It is documented in the Reneasas + * RZ/N1 User Manual, Chapter 7.4 ("SPKG format"). + * + * The BootROM searches this header in order to find and validate the boot + * payload. It is therefore mandatory to wrap the payload in this header. + * + * The ECC-related fields @ecc @ecc_scheme @ecc_bytes are used only when + * booting from NAND flash, and they are only used while fetching the payload. + * These values are used to initialize the ECC controller. To avoid using + * non-portable bitfields, struct spkg_hdr uses uint8_t for these fields, so + * the user must shift the values into the correct spot. + * + * The payload will be loaded into memory at @payload_address. + * Execution then jumps to @payload_address + @execution_offset. + * The LSB of @execution_offset selects between ARM and Thumb mode, + * as per the usual ARM interworking convention. + */ +struct spkg_hdr { + uint8_t marker[4]; /* aka magic */ + uint8_t version; + uint8_t ecc; + uint8_t ecc_scheme; + uint8_t ecc_bytes; + uint32_t payload_length; /* only HIGHER 24 bits */ + uint32_t load_address; + uint32_t execution_offset; + uint32_t crc; /* of this header */ +} __packed; + +/** + * struct spkg_file - complete SPKG image + * + * A SPKG image consists of 8 identical copies of struct spkg_hdr, each one + * occupying 24 bytes, for a total of 192 bytes. + * + * This is followed by the payload (the u-boot binary), and a 32-bit CRC. + * + * Optionally, the payload can be being with security header ("BLp_header"). + * This feature is not currently supported in mkimage. + * + * The payload is typically padded with 0xFF bytes so as to bring the total + * image size to a multiple of the flash erase size (often 64kB). + */ +struct spkg_file { + struct spkg_hdr header[SPKG_HEADER_COUNT]; + uint8_t payload[0]; + /* then the CRC */ +} __packed; + +#endif |