summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2022-06-20 08:07:45 -0400
committerTom Rini <trini@konsulko.com>2022-07-05 17:04:59 -0400
commit3dc2987f5c9b79e19ea6b0e69e01a817310abaac (patch)
tree805f9479527bb5be5254ceb5bade28ee9b3719b9 /include
parenta552ffc9d270769286d7a0697913689c31537bfa (diff)
downloadu-boot-3dc2987f5c9b79e19ea6b0e69e01a817310abaac.tar.gz
Convert CONFIG_PCIE1 et al to Kconfig
This converts the following to Kconfig: CONFIG_PCIE1 CONFIG_PCIE2 CONFIG_PCIE3 CONFIG_PCIE4 CONFIG_PCI1 Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'include')
-rw-r--r--include/configs/MPC8548CDS.h4
-rw-r--r--include/configs/P1010RDB.h3
-rw-r--r--include/configs/P2041RDB.h3
-rw-r--r--include/configs/P3041DS.h2
-rw-r--r--include/configs/P4080DS.h2
-rw-r--r--include/configs/P5040DS.h1
-rw-r--r--include/configs/T102xRDB.h3
-rw-r--r--include/configs/T104xRDB.h4
-rw-r--r--include/configs/T208xQDS.h4
-rw-r--r--include/configs/T208xRDB.h4
-rw-r--r--include/configs/T4240RDB.h5
-rw-r--r--include/configs/corenet_ds.h2
-rw-r--r--include/configs/kmcent2.h1
-rw-r--r--include/configs/ls1012afrwy.h2
-rw-r--r--include/configs/ls1012aqds.h2
-rw-r--r--include/configs/ls1012ardb.h2
-rw-r--r--include/configs/ls1021aiot.h4
-rw-r--r--include/configs/ls1021aqds.h4
-rw-r--r--include/configs/ls1021atsn.h2
-rw-r--r--include/configs/ls1021atwr.h4
-rw-r--r--include/configs/ls1043a_common.h4
-rw-r--r--include/configs/ls1046a_common.h5
-rw-r--r--include/configs/p1_p2_rdb_pc.h3
23 files changed, 0 insertions, 70 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index ce559e907c..bec2ca0f81 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -16,10 +16,6 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI1 /* PCI controller 1 */
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#undef CONFIG_PCI2
-
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 813516892c..5f64bd944b 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -63,9 +63,6 @@
/* High Level Configuration Options */
#if defined(CONFIG_PCI)
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-
/*
* PCI Windows
* Memory space is mapped 1-1, but I/O space must start from 0.
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 4a1fccff59..d7df5795cc 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -33,9 +33,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index 6063113634..bc8aa3ce05 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -9,8 +9,6 @@
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_PCIE3
-#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_SRIO
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 6615dd091e..6375c65d48 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -9,8 +9,6 @@
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_PCIE3
-
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
index 6e6e5bec66..fb73f0b953 100644
--- a/include/configs/P5040DS.h
+++ b/include/configs/P5040DS.h
@@ -9,7 +9,6 @@
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
-#define CONFIG_PCIE3
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 2ccfd87bfb..cdae8a88df 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -352,9 +352,6 @@
* General PCIe
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 1c2052608e..8222c67470 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -61,10 +61,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
/*
* These can be toggled for performance analysis, otherwise use default.
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index eda03dad22..53fc49fdcf 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -368,10 +368,6 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 290fd7cf74..b3648ae06f 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -321,10 +321,6 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-#define CONFIG_PCIE4 /* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 29447e4895..3edae6b01b 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -12,8 +12,6 @@
#include <linux/stringify.h>
-#define CONFIG_PCIE4
-
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
@@ -44,9 +42,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
/*
* These can be toggled for performance analysis, otherwise use default.
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index c0952e0928..59ec064156 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -36,8 +36,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
/*
* These can be toggled for performance analysis, otherwise use default.
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 3b4ddb0f94..ed24733abf 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -140,7 +140,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1 /* PCIE controller 1 */
/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 7f083c597e..ee67215a09 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -25,8 +25,6 @@
func(USB, usb, 0) \
func(DHCP, dhcp, na)
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index b5992366cf..9dbf1a7ab3 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -82,8 +82,6 @@
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index c57b598d70..f71ab2c80c 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -36,8 +36,6 @@
#define __PHY_ETH2_MASK 0xFB
#define __PHY_ETH1_MASK 0xFD
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index f43ea2bd6e..6556f1aa65 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -97,10 +97,6 @@
#define TSEC2_PHYIDX 0
#endif
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controler 1 */
-#define CONFIG_PCIE2 /* PCIE controler 2 */
-
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 1faa38b082..00825b373e 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -301,10 +301,6 @@
#endif
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
index 3ff694f6b5..791df844c1 100644
--- a/include/configs/ls1021atsn.h
+++ b/include/configs/ls1021atsn.h
@@ -80,8 +80,6 @@
#define FSL_QSPI_FLASH_NUM 2
/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index eff919116e..921399e31d 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -171,10 +171,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 8363969d55..db00a0a002 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -110,10 +110,6 @@
/* PCIe */
#ifndef SPL_NO_PCIE
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index e139aa93e1..3a1106777f 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -76,11 +76,6 @@
/* I2C */
-/* PCIe */
-#define CONFIG_PCIE1 /* PCIE controller 1 */
-#define CONFIG_PCIE2 /* PCIE controller 2 */
-#define CONFIG_PCIE3 /* PCIE controller 3 */
-
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 3ba95b4b6c..a639dbac78 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -102,9 +102,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
View Lorry Controller Status